JP7470457B2 - 表面処理装置および半導体装置の製造装置 - Google Patents

表面処理装置および半導体装置の製造装置 Download PDF

Info

Publication number
JP7470457B2
JP7470457B2 JP2022554990A JP2022554990A JP7470457B2 JP 7470457 B2 JP7470457 B2 JP 7470457B2 JP 2022554990 A JP2022554990 A JP 2022554990A JP 2022554990 A JP2022554990 A JP 2022554990A JP 7470457 B2 JP7470457 B2 JP 7470457B2
Authority
JP
Japan
Prior art keywords
bonding
surface treatment
treatment device
chip
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022554990A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2022074719A1 (https=
JPWO2022074719A5 (https=
Inventor
広 菊地
瑾 李
徹朗 高野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Robotics Co Ltd
Original Assignee
Yamaha Robotics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Robotics Co Ltd filed Critical Yamaha Robotics Co Ltd
Publication of JPWO2022074719A1 publication Critical patent/JPWO2022074719A1/ja
Publication of JPWO2022074719A5 publication Critical patent/JPWO2022074719A5/ja
Application granted granted Critical
Publication of JP7470457B2 publication Critical patent/JP7470457B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0448—Apparatus for applying a liquid, a resin, an ink or the like
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07152—Means for cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07173—Means for moving chips, wafers or other parts, e.g. conveyor belts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/327—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Pressure Welding/Diffusion-Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
JP2022554990A 2020-10-05 2020-10-05 表面処理装置および半導体装置の製造装置 Active JP7470457B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/037776 WO2022074719A1 (ja) 2020-10-05 2020-10-05 表面処理装置および半導体装置の製造装置

Publications (3)

Publication Number Publication Date
JPWO2022074719A1 JPWO2022074719A1 (https=) 2022-04-14
JPWO2022074719A5 JPWO2022074719A5 (https=) 2023-07-14
JP7470457B2 true JP7470457B2 (ja) 2024-04-18

Family

ID=81126739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022554990A Active JP7470457B2 (ja) 2020-10-05 2020-10-05 表面処理装置および半導体装置の製造装置

Country Status (6)

Country Link
US (1) US12489004B2 (https=)
EP (1) EP4227980A4 (https=)
JP (1) JP7470457B2 (https=)
KR (1) KR102894616B1 (https=)
CN (1) CN116325100A (https=)
WO (1) WO2022074719A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022150172A (ja) * 2021-03-26 2022-10-07 株式会社ディスコ ウエーハの貼り合わせ方法
FR3144695B1 (fr) * 2022-12-28 2026-04-03 Commissariat Energie Atomique Procédé de collage hybride direct de puce à plaque
JP2024097401A (ja) * 2023-01-06 2024-07-19 ヤマハロボティクスホールディングス株式会社 半導体チップのアライメント方法、接合方法、半導体装置、並びに電子部品製造システム
JP7659910B2 (ja) * 2023-04-24 2025-04-10 ヤマハロボティクスホールディングス株式会社 プラズマ処理方法及び接合システム

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015211130A (ja) 2014-04-25 2015-11-24 ボンドテック株式会社 基板接合装置および基板接合方法
WO2017155002A1 (ja) 2016-03-11 2017-09-14 ボンドテック株式会社 基板接合方法
WO2018062467A1 (ja) 2016-09-30 2018-04-05 ボンドテック株式会社 基板接合方法および基板接合装置
JP2018201022A (ja) 2014-04-25 2018-12-20 須賀　唯知 基板接合装置および基板接合方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012175043A (ja) 2011-02-24 2012-09-10 Tokyo Electron Ltd 接合装置、接合システム、接合方法、プログラム及びコンピュータ記憶媒体
JP2013243333A (ja) * 2012-04-24 2013-12-05 Tadatomo Suga チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
JP6337400B2 (ja) 2012-04-24 2018-06-06 須賀　唯知 チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
US10964664B2 (en) * 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015211130A (ja) 2014-04-25 2015-11-24 ボンドテック株式会社 基板接合装置および基板接合方法
JP2018201022A (ja) 2014-04-25 2018-12-20 須賀　唯知 基板接合装置および基板接合方法
WO2017155002A1 (ja) 2016-03-11 2017-09-14 ボンドテック株式会社 基板接合方法
WO2018062467A1 (ja) 2016-09-30 2018-04-05 ボンドテック株式会社 基板接合方法および基板接合装置

Also Published As

Publication number Publication date
JPWO2022074719A1 (https=) 2022-04-14
EP4227980A1 (en) 2023-08-16
US20230369079A1 (en) 2023-11-16
WO2022074719A1 (ja) 2022-04-14
EP4227980A4 (en) 2024-09-25
KR20230054731A (ko) 2023-04-25
CN116325100A (zh) 2023-06-23
US12489004B2 (en) 2025-12-02
KR102894616B1 (ko) 2025-12-02

Similar Documents

Publication Publication Date Title
JP7470457B2 (ja) 表面処理装置および半導体装置の製造装置
US9142532B2 (en) Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer
JP6612632B2 (ja) 基板処理装置および基板処理方法
KR20130111533A (ko) 접합시스템, 기판 처리 시스템, 접합방법, 프로그램 및 컴퓨터 저장매체
JP5352546B2 (ja) 接合システム、接合方法、プログラム及びコンピュータ記憶媒体
US8978671B2 (en) Substrate processing method and substrate processing apparatus
JP7850727B2 (ja) 処理方法及びプラズマ処理装置
US11491567B2 (en) Soldering device and a method for producing a solder connection of components using adhesive material for temporary connection of the components
JP7612428B2 (ja) ダイボンディング装置、剥離治具および半導体装置の製造方法
KR20160086277A (ko) 접합 장치, 접합 시스템, 접합 방법 및 컴퓨터 기억 매체
US20210335741A1 (en) Systems for thermally treating conductive elements on semiconductor and wafer structures
JP2019204832A (ja) 部品実装システム、基板接合システム、部品実装方法および基板接合方法
US6918421B2 (en) Thin film forming apparatus and thin film forming method
JP6055387B2 (ja) 接合方法、プログラム、コンピュータ記憶媒体及び接合システム
US8187923B2 (en) Laser release process for very thin Si-carrier build
US10332759B2 (en) Processing apparatus
KR20230004254A (ko) 칩의 제조 방법
TWI799989B (zh) 表面處理裝置及半導體裝置的製造裝置
TWI870271B (zh) 防止產生氣泡的加熱固晶方法
US20160351422A1 (en) Multiple Swivel Arm Design in Hybrid Bonder
JP3915624B2 (ja) 電子部品装着装置および電子部品装着方法
JP2004119701A (ja) 接合方法および装置
WO2025206207A1 (ja) 実装前処理装置、実装システム及び実装前処理方法

Legal Events

Date Code Title Description
A529 Written submission of copy of amendment under article 34 pct

Free format text: JAPANESE INTERMEDIATE CODE: A5211

Effective date: 20230320

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230320

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240116

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240205

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240401

R150 Certificate of patent or registration of utility model

Ref document number: 7470457

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150