JP7381221B2 - ワイドバンドギャップ半導体ウェハを処理する方法、複数の薄膜ワイドバンドギャップ半導体ウェハを形成する方法およびワイドバンドギャップ半導体ウェハ - Google Patents
ワイドバンドギャップ半導体ウェハを処理する方法、複数の薄膜ワイドバンドギャップ半導体ウェハを形成する方法およびワイドバンドギャップ半導体ウェハ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 259
- 238000000034 method Methods 0.000 title claims description 80
- 238000012545 processing Methods 0.000 title claims description 35
- 235000012431 wafers Nutrition 0.000 title description 241
- 239000010409 thin film Substances 0.000 title description 28
- 239000010410 layer Substances 0.000 claims description 247
- 239000013078 crystal Substances 0.000 claims description 55
- 238000000151 deposition Methods 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 27
- 230000008021 deposition Effects 0.000 claims description 19
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 19
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000001465 metallisation Methods 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- 239000011241 protective layer Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 19
- 230000008569 process Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 239000010408 film Substances 0.000 description 5
- 229910052799 carbon Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 230000001419 dependent effect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000000638 solvent extraction Methods 0.000 description 3
- 230000008719 thickening Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000032683 aging Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000001182 laser chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000006735 deficit Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
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Description
Claims (17)
- ワイドバンドギャップ半導体ウェハを処理する方法(100)であって、前記方法(100)は、
炭化ケイ素ウェハであるワイドバンドギャップ半導体ウェハの後面に、ポリシリコンカーバイド層またはモリブデン層である非単結晶支持体層(320)を堆積(110)するステップと、
前記ワイドバンドギャップ半導体ウェハの前面にエピタキシャル層を堆積(120)するステップと、
前記エピタキシャル層の少なくとも一部を含むデバイスウェハと、前記非単結晶支持体層(320)を含む残留ウェハと、が得られるよう、前記前面に平行に延在する分割領域に沿って、前記ワイドバンドギャップ半導体ウェハを分割(130)するステップと、
前記残留ウェハの前記非単結晶支持体層(320)に別の非単結晶支持体層を堆積するステップと、
を含む方法(100)。 - 前記非単結晶支持体層(320)の熱膨張係数は、前記ワイドバンドギャップ半導体ウェハの熱膨張係数の最大10%だけ、前記ワイドバンドギャップ半導体ウェハの熱膨張係数と異なる、
請求項1記載の方法(100)。 - 前記非単結晶支持体層(320)を、最小50μm/hの堆積速度で堆積(110)する、
請求項1または2記載の方法(100)。 - 前記非単結晶支持体層(320)を含む前記残留ウェハの全厚さは、最小200μmかつ最大1500μmである、
請求項1から3までのいずれか1項記載の方法(100)。 - 前記非単結晶支持体層(320)を堆積(110)するステップ中、前記ワイドバンドギャップ半導体ウェハの前記前面に保護層を配置する、
請求項1から4までのいずれか1項記載の方法(100)。 - 前記別の非単結晶支持体層の材料は、前記非単結晶支持体層(320)の材料とは異なる、
請求項1から5までのいずれか1項記載の方法(100)。 - 前記非単結晶支持体層(320)および前記別の非単結晶支持体層を含む前記残留ウェハの厚さは、前記ワイドバンドギャップ半導体ウェハを分割(130)するステップの前には、最大300μmだけ、前記ワイドバンドギャップ半導体ウェハの厚さと異なる、
請求項1から6までのいずれか1項記載の方法(100)。 - 前記別の非単結晶支持体層は、別のデバイスウェハの全厚さの最小90%かつ最大110%の厚さを有する、
請求項1から7までのいずれか1項記載の方法(100)。 - 前記方法(100)はさらに、
前記残留ウェハの前面に別のエピタキシャル層を堆積するステップと、
前記別のエピタキシャル層を含む別のデバイスウェハと、前記非単結晶支持体層(320)を含む別の残留ウェハと、が得られるよう、前記残留ウェハの前記前面に平行に延在する別の分割領域に沿って、前記残留ウェハを分割するステップと、
を含む、
請求項1から8までのいずれか1項記載の方法(100)。 - 前記方法(100)はさらに、
前記非単結晶支持体層(320)を堆積(110)するステップの後、前記ワイドバンドギャップ半導体ウェハ内にワイドバンドギャップ半導体デバイスのドープ領域を形成するステップを含む、
請求項1から9までのいずれか1項記載の方法(100)。 - 前記方法(100)はさらに、
前記非単結晶支持体層を堆積(110)するステップの後、前記ワイドバンドギャップ半導体ウェハの前記前面に、ワイドバンドギャップ半導体デバイスのメタライゼーション構造を形成するステップを含む、
請求項1から10までのいずれか1項記載の方法(100)。 - 分割(130)するステップの前に、前記ワイドバンドギャップ半導体ウェハの前記前面に、少なくとも1つのゲートトレンチおよびトランジスタのゲート電極を形成する、
請求項1から11までのいずれか1項記載の方法(100)。 - 分割(130)するステップの後、最高1000℃の温度で、前記デバイスウェハを処理する、
請求項1から12までのいずれか1項記載の方法(100)。 - 炭化ケイ素ウェハであるワイドバンドギャップ半導体ウェハ(300)であって、
最小250μmの厚さを有する単結晶ワイドバンドギャップ半導体層(310)と、
前記単結晶ワイドバンドギャップ半導体層(310)の表面に配置された、最小150μmの厚さを有し、ポリシリコンカーバイド層またはモリブデン層である非単結晶支持体層(320)と、
を含み、
前記非単結晶支持体層(320)の少なくとも一部の熱膨張係数は、前記単結晶ワイドバンドギャップ半導体層(310)の熱膨張係数の最大10%だけ、前記単結晶ワイドバンドギャップ半導体層(310)の熱膨張係数と異なり、
前記非単結晶支持体層(320)の第1の部分層は、第1の材料を含み、
前記非単結晶支持体層(320)の第2の部分層は、第2の材料を含み、
前記第1の材料は、前記第2の材料とは異なる、
ワイドバンドギャップ半導体ウェハ(300)。 - 炭化ケイ素半導体ウェハを処理する方法(100)であって、前記方法(100)は、
炭化ケイ素半導体ウェハを提供するステップと、
前記炭化ケイ素半導体ウェハの前面にエピタキシャル層を堆積(120)するステップと、
前記エピタキシャル層の少なくとも一部を含む第1のデバイスウェハと、第1の残留ウェハと、が得られるよう、前記前面に平行に延在する第1の分割領域に沿って、前記炭化ケイ素半導体ウェハを分離(130)するステップと、
前記第1の残留ウェハの後面に、ポリシリコンカーバイド層またはモリブデン層である第1の非単結晶支持体層(320)を堆積するステップと、
前記第1の非単結晶支持体層を堆積するステップの後、前記第1の残留ウェハの前面に、エピタキシャル層を堆積するステップと、
前記エピタキシャル層の少なくとも一部を含む第2のデバイスウェハと、前記第1の非単結晶支持体層を含む第2の残留ウェハと、が得られるよう、前記第1の残留ウェハ内で前記前面に平行に延在する第2の分割領域に沿って、前記第1の残留ウェハを分離するステップと、
を含む方法(100)。 - 前記方法はさらに、
前記第2の残留ウェハの前記第1の非単結晶支持体層に、ポリシリコンカーバイド層またはモリブデン層である第2の非単結晶支持体層(320)を堆積するステップと、
前記第2の非単結晶支持体層(320)を堆積するステップの後、前記第2の残留ウェハの前面に、エピタキシャル層を堆積するステップと、
前記エピタキシャル層の少なくとも一部を含む第3のデバイスウェハと、前記第1の非単結晶支持体層および前記第2の非単結晶支持体層を含む第3の残留ウェハと、が得られるよう、前記第2の残留ウェハ内で前記前面に平行に延在する第3の分割領域に沿って、前記第2の残留ウェハを分離するステップと、
を含む、
請求項15記載の方法。 - 前記第1の非単結晶支持体層の厚さを含む前記第1の残留ウェハの厚さは、前記炭化ケイ素半導体ウェハの分割前には、最大200μmだけ、前記炭化ケイ素半導体ウェハの厚さと異なる、および/または、
前記第1の非単結晶支持体層および前記第2の非単結晶支持体層の厚さを含む前記第2の残留ウェハの厚さは、前記第1の残留ウェハの分割前には、最大200μmだけ、前記第1の残留ウェハの厚さと異なる、
請求項16記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102018111450.8 | 2018-05-14 | ||
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US20190348328A1 (en) | 2019-11-14 |
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