JP7316399B2 - アンテナを備えたパッケージング構造及びその製作方法 - Google Patents
アンテナを備えたパッケージング構造及びその製作方法 Download PDFInfo
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- JP7316399B2 JP7316399B2 JP2022010949A JP2022010949A JP7316399B2 JP 7316399 B2 JP7316399 B2 JP 7316399B2 JP 2022010949 A JP2022010949 A JP 2022010949A JP 2022010949 A JP2022010949 A JP 2022010949A JP 7316399 B2 JP7316399 B2 JP 7316399B2
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- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Description
第1金属層を具備する載置板を提供し、且つ前記第1金属層に、内部に第1犠牲金属ポスト、及び前記第1金属層に接続される第1導通用ビアポストが封入される少なくとも1層のアンテナ層を施すステップと、
最終層の前記アンテナ層をベースとして、前記第1導通用ビアポストに接続される相互接続回路、前記相互接続回路に接続される第2導通用ビアポスト及びパッケージングキャビティを含む部材パッケージング層を施すステップと、
前記パッケージングキャビティ内にチップを封入してから、前記部材パッケージング層をベースとして第2金属層を施すステップと、
載置板を分離させ、前記第1金属層を表面アンテナ回路に仕上げ、前記第2金属層を前記第2導通用ビアポストに接続される外層回路に仕上げるステップと、
前記第1犠牲金属ポストを除去して凹溝を得るステップと、
前記凹溝の内壁に前記表面アンテナ回路に接続される側壁アンテナ回路を施すステップと、
前記外層回路に導電ピンを施すステップと、
前記凹溝に沿って切断してパッケージを得るステップとを含む。
生産資料により、パターン転写とパターン電気メッキの方式によって前記第1金属層に第1部分の層間ビアポストと第1部分の第1犠牲金属ポストを施して、1層目のアンテナ層半完成品を得るステップと、
1層目の前記アンテナ層半完成品に積層押圧を行って、1層目のアンテナ層を得るステップとを含む。
押圧後の前記アンテナ層に薄肉化処理を行って、前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストを露出させる薄肉化処理と、
パターン転写の方式によって前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストにパッドを施し、又は、パターン転写の方式によって前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストにパッド及び対応する前記パッドに接続される内層アンテナ回路を施すパターン作成と、
生産資料により、パターン転写とパターン電気メッキの方式によってパッドをベースとして次の一部分の前記層間ビアポストと次の一部分の前記第1犠牲金属ポストを施して、次の層のアンテナ層半完成品を得る半完成品加工と、
次の層の前記アンテナ層半完成品に積層押圧を行う積層押圧と、
複数層の前記アンテナ層の加工が完了するまで、生産資料により、基板研削、パターン作成、半完成品加工及び積層押圧を繰り返すステップとを更に含む。
最終層の前記アンテナ層に薄肉化処理を行うステップと、
パターン転写、パターン電気メッキ及び積層押圧の方式によって薄肉化後の前記アンテナ層に、前記相互接続回路の所在する少なくとも1層の相互接続回路層を施すステップとを含む。
最終層の前記相互接続回路層であって前記パッケージングキャビティ内の相互接続回路に保護金属を施すステップと、
前記最終層の前記相互接続回路層に前記第2導通用ビアポストを施し、前記保護金属に第2犠牲金属ポストを施して、部材パッケージング層半完成品を得るステップと、
前記部材パッケージング層半完成品に積層押圧及び薄肉化処理を行うステップと、
エッチングの方式によって前記第2犠牲金属ポストと前記保護金属を除去して、前記パッケージングキャビティを形成するステップとを更に含む。
前記チップのピンが前記パッケージングキャビティ内に位置する前記相互接続回路に接続されるように、前記チップを前記パッケージングキャビティ内に貼り付けるステップと、
前記パッケージングキャビティをプラスチック封止するステップとを含む。
前記チップのピンが前記相互接続回路層から離れた一側に向かうように、前記チップを前記パッケージングキャビティ内に貼り付けるステップと、
前記パッケージングキャビティをプラスチック封止するステップとを含む。
レーザーによる穴あけ方式によって前記チップのピンを露出させるステップと、
前記第2金属層が前記チップのピンに接続されるように、パターン転写とパターン電気メッキの方式によって前記部材パッケージング層をベースとして前記第2金属層を施すステップとを含む。
前記凹溝の内壁に金属シード層を施すステップと、
前記第1金属層と前記第2金属層に感光遮蔽膜を施し、且つ前記感光遮蔽膜の前記凹溝に対応する位置に開口するステップと、
前記凹溝内に金属を堆積させて、前記側壁アンテナ回路を形成するステップと、
前記感光遮蔽膜と前記金属シード層を除去するステップとを含む。
前記外層回路に溶接防止層を施し、且つ前記溶接防止層の前記導電ピンに対応する位置に開口するステップを更に含む。
110:第1金属層
120:表面アンテナ回路
130:側壁アンテナ回路
200:アンテナ層
210:第1犠牲金属ポスト
220:第1導通用ビアポスト
221:層間ビアポスト
230:凹溝
240:パッド
300:部材パッケージング層
310:相互接続回路
320:第2導通用ビアポスト
330:パッケージングキャビティ
340:保護金属
350:第2犠牲金属ポスト
400:チップ
500:第2金属層
510:外層回路
600:導電ピン
700:パッケージ
800:溶接防止層
Claims (15)
- 内部に第1導通用ビアポストと第2導通用ビアポストが封入されたパッケージと、
前記パッケージの第1表面及び側壁に設置されるアンテナ回路と、
前記パッケージ内に封入され、且つ前記第1導通用ビアポストを介して前記アンテナ回路に接続される相互接続回路と、
前記パッケージの第2表面に設置され、且つ前記第2導通用ビアポストを介して前記相互接続回路に接続され、更に導電ピンを接続した外層回路と、
前記パッケージ内に封入され、且つ前記相互接続回路又は前記外層回路に接続されるチップとを含むことを特徴とするアンテナを備えたパッケージング構造。 - 前記パッケージの側壁に位置するアンテナ回路は階段構造となることを特徴とする請求項1に記載のアンテナを備えたパッケージング構造。
- 前記第1導通用ビアポストは、縦方向に接続される複数の部分の層間ビアポストを含み、隣接する2部分の前記層間ビアポストの間にパッドが設置されていることを特徴とする請求項2に記載のアンテナを備えたパッケージング構造。
- 前記パッケージ内であって前記パッドと同一の層内に、対応する前記パッドに接続される内層アンテナ回路が設置されていることを特徴とする請求項3に記載のアンテナを備えたパッケージング構造。
- 第1金属層を具備する載置板を提供し、且つ前記第1金属層に、内部に第1犠牲金属ポスト、及び前記第1金属層に接続される第1導通用ビアポストが封入される少なくとも1層のアンテナ層を施すステップと、
最終層の前記アンテナ層をベースとして、前記第1導通用ビアポストに接続される相互接続回路、前記相互接続回路に接続される第2導通用ビアポスト及びパッケージングキャビティを含む部材パッケージング層を施すステップと、
前記パッケージングキャビティ内にチップを封入してから、前記部材パッケージング層をベースとして第2金属層を施すステップと、
載置板を分離させ、前記第1金属層を表面アンテナ回路に仕上げ、前記第2金属層を前記第2導通用ビアポストに接続される外層回路に仕上げるステップと、
前記第1犠牲金属ポストを除去して凹溝を得るステップと、前記凹溝の内壁に前記表面アンテナ回路に接続される側壁アンテナ回路を施すステップと、
前記外層回路に導電ピンを施すステップと、
前記凹溝に沿って切断してパッケージを得るステップとを含むことを特徴とするアンテナを備えたパッケージング構造の製作方法。 - 前記第1金属層に少なくとも1層の前記アンテナ層を施すステップは、
生産資料により、パターン転写とパターン電気メッキの方式によって前記第1金属層に第1部分の層間ビアポストと第1部分の前記第1犠牲金属ポストを施して、1層目のアンテナ層半完成品を得るステップと、
1層目の前記アンテナ層半完成品に積層押圧を行って、1層目の前記アンテナ層を得るステップとを含むことを特徴とする請求項5に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記第1金属層に少なくとも1層のアンテナ層を施すステップは、
押圧後の前記アンテナ層に薄肉化処理を行って、前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストを露出させる薄肉化処理と、
パターン転写の方式によって前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストにパッドを施し、又は、パターン転写の方式によって前記第1部分の前記層間ビアポストと前記第1部分の前記第1犠牲金属ポストにパッド及び対応する前記パッドに接続される内層アンテナ回路を施すパターン作成と、
生産資料により、パターン転写とパターン電気メッキの方式によってパッドをベースとして次の一部分の前記層間ビアポストと次の一部分の前記第1犠牲金属ポストを施して、次の層の前記アンテナ層半完成品を得る半完成品加工と、次の層の前記アンテナ層半完成品に積層押圧を行う積層押圧と、
複数層の前記アンテナ層の加工が完了するまで、生産資料により、基板研削、パターン作成、半完成品加工及び積層押圧を繰り返すステップとを更に含むことを特徴とする請求項6に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記最終層の前記アンテナ層をベースとして前記部材パッケージング層を施すステップは、
前記最終層の前記アンテナ層に薄肉化処理を行うステップと、
パターン転写、パターン電気メッキ及び積層押圧の方式によって薄肉化後の前記アンテナ層に、前記相互接続回路の所在する少なくとも1層の相互接続回路層を施すステップとを含むことを特徴とする請求項5に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記最終層の前記アンテナ層をベースとして前記部材パッケージング層を施すステップは、
前記最終層の前記相互接続回路層であって前記パッケージングキャビティ内の前記相互接続回路に保護金属を施すステップと、
前記最終層の前記相互接続回路層に前記第2導通用ビアポストを施し、前記保護金属に第2犠牲金属ポストを施して、部材パッケージング層半完成品を得るステップと、
前記部材パッケージング層半完成品に積層押圧及び薄肉化処理を行うステップと、
エッチングの方式によって前記第2犠牲金属ポストと前記保護金属を除去して、前記パッケージングキャビティを形成するステップとを更に含むことを特徴とする請求項8に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記パッケージングキャビティ内に前記チップを封入するステップは、
前記チップのピンが前記パッケージングキャビティ内に位置する前記相互接続回路に接続されるように、前記チップを前記パッケージングキャビティ内に貼り付けるステップと、
前記パッケージングキャビティをプラスチック封止するステップとを含むことを特徴とする請求項9に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記パッケージングキャビティ内に前記チップを封入するステップは、
前記チップのピンが前記相互接続回路層から離れた一側に向かうように、前記チップを前記パッケージングキャビティ内に貼り付けるステップと、
前記パッケージングキャビティをプラスチック封止するステップとを含むことを特徴とする請求項9に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記部材パッケージング層をベースとして前記第2金属層を施すステップは、
レーザーによる穴あけ方式によって前記チップのピンを露出させるステップと、
前記第2金属層が前記チップのピンに接続されるように、パターン転写とパターン電気メッキの方式によって前記部材パッケージング層をベースとして前記第2金属層を施すステップとを含むことを特徴とする請求項11に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記凹溝の内壁に前記側壁アンテナ回路を施すステップは、
前記凹溝の内壁に金属シード層を施すステップと、
前記第1金属層と前記第2金属層に感光遮蔽膜を施し、且つ前記感光遮蔽膜の前記凹溝に対応する位置に開口するステップと、
前記凹溝内に金属を堆積させて、前記側壁アンテナ回路を形成するステップと、
前記感光遮蔽膜と前記金属シード層を除去するステップとを含むことを特徴とする請求項5に記載のアンテナを備えたパッケージング構造の製作方法。 - 前記凹溝の内壁は階段構造となることを特徴とする請求項5又は13に記載のアンテナを備えたパッケージング構造の製作方法。
- 前記外層回路に前記導電ピンを施す前に、
前記外層回路に溶接防止層を施し、且つ前記溶接防止層の前記導電ピンに対応する位置に開口するステップを更に含むことを特徴とする請求項5に記載のアンテナを備えたパッケージング構造の製作方法。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005005985A (ja) | 2003-06-11 | 2005-01-06 | Sony Chem Corp | アンテナ素子及びアンテナ実装基板 |
JP2012165329A (ja) | 2011-02-09 | 2012-08-30 | Alps Electric Co Ltd | 通信モジュール |
JP2017191835A (ja) | 2016-04-12 | 2017-10-19 | Tdk株式会社 | 電子回路モジュール及びその製造方法 |
JP2020503685A (ja) | 2016-12-28 | 2020-01-30 | レイセオン カンパニー | 多層無線周波数回路のための相互接続システム及び製造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3695123B2 (ja) * | 1997-04-18 | 2005-09-14 | 株式会社村田製作所 | アンテナ装置およびそれを用いた通信機 |
EP2736001A1 (fr) * | 2012-11-27 | 2014-05-28 | Gemalto SA | Module électronique à interface de communication tridimensionnelle |
US10050013B2 (en) * | 2015-12-29 | 2018-08-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging methods |
EP4340012A2 (en) * | 2016-04-28 | 2024-03-20 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with integrated antenna arrangement, electronic apparatus, radio communication method |
CN108666300A (zh) * | 2017-03-31 | 2018-10-16 | 欣兴电子股份有限公司 | 芯片封装结构及其制造方法 |
US10867938B2 (en) * | 2017-09-25 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure |
KR102059814B1 (ko) * | 2018-07-12 | 2019-12-27 | 삼성전기주식회사 | 안테나 모듈 |
CN109244046A (zh) * | 2018-10-26 | 2019-01-18 | 中芯长电半导体(江阴)有限公司 | 扇出型天线封装结构及封装方法 |
CN109768031A (zh) * | 2019-03-04 | 2019-05-17 | 中芯长电半导体(江阴)有限公司 | 天线的封装结构及封装方法 |
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CN111403297A (zh) * | 2020-03-26 | 2020-07-10 | 甬矽电子(宁波)股份有限公司 | Ic射频天线结构的制作方法、ic射频天线结构和半导体器件 |
CN111585002B (zh) * | 2020-05-20 | 2021-05-14 | 甬矽电子(宁波)股份有限公司 | 双向喇叭封装天线结构、其制作方法和电子设备 |
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JP2005005985A (ja) | 2003-06-11 | 2005-01-06 | Sony Chem Corp | アンテナ素子及びアンテナ実装基板 |
JP2012165329A (ja) | 2011-02-09 | 2012-08-30 | Alps Electric Co Ltd | 通信モジュール |
JP2017191835A (ja) | 2016-04-12 | 2017-10-19 | Tdk株式会社 | 電子回路モジュール及びその製造方法 |
JP2020503685A (ja) | 2016-12-28 | 2020-01-30 | レイセオン カンパニー | 多層無線周波数回路のための相互接続システム及び製造方法 |
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