JP7295867B2 - 高電流能力を有するフィーダ設計 - Google Patents
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Description
●制限された注入効率及び高オーミック接触抵抗に起因するPiNダイオードの高電流時の相対的に高順方向電圧降下
●ショットキーモードにおけるPN接合での電圧降下に起因するスナップバック効果を引き起こす高順方向電圧時のショットキーからPiNダイオードへの特性の切り換え
●デバイスの性能及び寿命を劣化させるイオン注入によって引き起こされるバイポーラ劣化
を含む。
イオン注入P領域
利点:
●プロセス温度及び/又は注入ドーズに応じて、マスク、酸化物、又はフォトレジストマスクによる選択的なドープ領域
●ドーピングの良好な制御性及びウェーハに亘る均一性
●周知のドーピング技術
欠点:
〇注入損傷から残っている欠陥中心における再結合に起因する注入エミッタの低効率→MPS整流器のサージ電流能力の制限
〇注入ドーズの増加に伴う注入損傷の増加に起因するドーピングレベルの制限
〇一般的に使用されるSiCにおけるアクセプター及びドナードーパントの不拡散→注入pn接合は、注入プロファイルが終了し、注入損傷が大きい場所に位置する
〇注入エネルギーの制限に起因する厚さの制限、1μmの厚さは、注入イオンに応じて400~1000keVの注入エネルギーを要求する
〇高エネルギー注入は高コストのプロセスである
エピタキシャルP領域
利点:
●優れた高ドープ材料品質に起因する高注入効率
●グリッドの厚さ及びドーピングプロファイルの制御
●深いドープ構造が可能、グリッドの厚さは問題なし
●高濃度であっても損傷のないドーピング
●半導体-半金属転移に近い高ドーピング濃度が可能
欠点:
〇エピタキシャルグリッドの鋭い角部は、デバイスの阻止電圧を制限する電界集中をもたらす
〇CMP又は平坦化プロセスが必要となる場合がある
a)上にドリフト層及びn型SiC材料(3)を有する基板を提供するステップと、
b)SiCのエピタキシャル成長によってp型層を追加するステップと、
c)少なくとも1つのエピタキシャル成長p型領域(7)を得るために、追加されたp型層の不要な部分をエッチングで取り除くステップと、
d)n型SiC材料(3)においてイオン注入によって少なくとも2つのp型グリッド(4、5)を作製するステップと、
e)SiCのエピタキシャル成長によってn型層(8)を追加するステップと
を含む。
Claims (25)
- 基板(1)、前記基板(1)上のドリフト層(2)、及びn型SiC材料(3)における少なくとも2つのp型グリッド(4、5)を備えるSiC半導体材料のPiNダイオード構造であって、
前記n型SiC材料(3)は、前記ドリフト層(2)上にあり、前記PiNダイオード構造は、SiCのn型エピタキシャル成長層(8)を備え、前記n型エピタキシャル成長層(8)は、前記少なくとも2つのp型グリッド(4、5)及び前記n型SiC材料(3)と接触し、前記n型エピタキシャル成長層(8)は、少なくとも1つのエピタキシャル成長p型領域(7)と接触し、オーミックコンタクト(9)が、前記少なくとも1つのエピタキシャル成長p型領域(7)と接触し、前記基板(1)と平行な平面における前記少なくとも1つのエピタキシャル成長p型領域(7)の投影が、前記少なくとも1つのエピタキシャル成長p型領域(7)の前記投影を制限する境界線(l)を有し、
前記少なくとも2つのp型グリッド(4、5)のうちの1つのp型グリッド(5)は、少なくとも、前記基板(1)に平行な平面における前記p型グリッド(5)の投影が前記境界線(l)上にあり、且つ前記境界線(l)の周囲にあって、前記境界線(l)から前記周囲における任意の点の距離が最大0.5μmであるように与えられ、
前記p型グリッド(5)はまた、前記少なくとも1つのエピタキシャル成長p型領域(7)の下部から前記p型グリッド(5)の上部の距離が0~5μmであるようにのみ与えられ、上方向が、前記基板(1)から垂直に離間する方向によって与えられることを特徴とする、PiNダイオード構造。 - 前記少なくとも1つのエピタキシャル成長p型領域(7)は、前記少なくとも2つのp型グリッド(4、5)のうちの少なくとも1つと接触している、請求項1に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)は、前記少なくとも2つのp型グリッド(4、5)と接触していない、請求項1に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)はそれぞれ、複数のイオン注入グリッドを含む、請求項1~3の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)の幅は、5~500μmである、請求項1~4の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)の厚さは、1~3μmである、請求項1~5の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)のドーピング濃度は、前記n型SiC材料(3)に最も近接する部分から前記オーミックコンタクト(9)に最も近接する部分まで変化する、請求項1~6の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)のドーピング濃度は、前記オーミックコンタクト(9)に最も近接する部分で最も高い、請求項7に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)のドーピング濃度は、ドーピング濃度が1×1019cm-3~3×1020cm-3である前記オーミックコンタクト(9)に最も近接する層を除いて5×1017cm-3~1×1019cm-3である、請求項8に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)と前記n型SiC材料(3)における前記少なくとも2つのp型グリッド(4、5)との間に空間があり、前記少なくとも1つのエピタキシャル成長p型領域(7)と前記少なくとも2つのp型グリッド(4、5)との間の接続を伴う、請求項1~9の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも1つのエピタキシャル成長p型領域(7)は、n型SiC材料(3)における前記少なくとも2つのp型グリッド(4、5)上に直接与えられる、請求項1~9の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)のドーピング濃度は、3×1017cm-3~3×1020cm-3であり、前記少なくとも2つのp型グリッド(4、5)の厚さは、0.5~2.5μmであり、前記少なくとも2つのp型グリッド(4、5)の部材の各々の幅は、少なくとも0.5μmである、請求項1~11の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)のうちの2つの隣接するp型グリッドの間の距離は1~5μmである、請求項1~12の何れか一項に記載のPiNダイオード構造。
- 前記n型エピタキシャル成長層(8)の厚さは、少なくとも0.5μmであり、ドーピング濃度は、1×1014cm-3~1×1017cm-3である、請求項1~13の何れか一項に記載のPiNダイオード構造。
- 前記n型エピタキシャル成長層(8)の厚さは、前記少なくとも1つのエピタキシャル成長p型領域(7)より少なくとも0.5μm厚い、請求項1~14の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)は複数のグリッド部材を含む、請求項1~15の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)は複数のグリッド部材を含み、各グリッド部材は上部及び下部を備え、前記上部は、前記n型エピタキシャル成長層(8)に面し、前記上部は、エピタキシャル成長を使用して製造され、前記下部は、イオン注入を使用して製造されている、請求項1~16の何れか一項に記載のPiNダイオード構造。
- 前記少なくとも2つのp型グリッド(4、5)は、イオン注入によって製造されている、請求項1~17の何れか一項に記載のPiNダイオード構造。
- 請求項1~18の何れか一項に記載のPiNダイオード構造を備えるデバイス。
- 前記デバイスは、MOSFET、JFET、JBSダイオード、及び絶縁ゲートバイポーラトランジスタ(IGBT)からなるグループから選択される、請求項19に記載のデバイス。
- 前記デバイスは、少なくとも2つの構成要素の集積である、請求項20に記載のデバイス。
- SiCにおける請求項1~18の何れか一項に記載のPiNダイオード構造の製造方法であって、
a)上にドリフト層及びn型SiC材料(3)を有する基板を提供するステップと、
b)SiCのエピタキシャル成長によってp型層を追加するステップと、
c)少なくとも1つのエピタキシャル成長p型領域(7)を得るために、前記追加されたp型層の不要な部分をエッチングで取り除くステップと、
d)前記n型SiC材料(3)において少なくとも2つのp型グリッド(4、5)を作製するステップと、
e)SiCのエピタキシャル成長によってn型層(8)を追加するステップと
を含み、
前記少なくとも1つのエピタキシャル成長p型領域(7)上に少なくとも部分的にオーミックコンタクト(9)を追加するステップを含む方法。 - ステップd)はステップb)の前に実行される、請求項22に記載の方法。
- ステップd)はイオン注入によって実行される、請求項22又は23に記載の方法。
- 前記ステップa)、d)、e)、b)、c)の順序で実行され、前記少なくとも1つのエピタキシャル成長p型領域(7)のために意図された領域において、ステップe)の後に前記n型層(8)にトレンチをエッチングする追加のステップを有する、請求項24に記載の方法。
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