JP7247514B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP7247514B2 JP7247514B2 JP2018195372A JP2018195372A JP7247514B2 JP 7247514 B2 JP7247514 B2 JP 7247514B2 JP 2018195372 A JP2018195372 A JP 2018195372A JP 2018195372 A JP2018195372 A JP 2018195372A JP 7247514 B2 JP7247514 B2 JP 7247514B2
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Description
<半導体装置の構造>
本発明の第1の実施形態に係る半導体装置は、図1に示すように、第1導電型(n-型)のドリフト層2と、ドリフト層2の上面側に配置された第2導電型(p型)のベース領域7を備えるトレンチゲート型のMOSFETである。ベース領域7の上部にはドリフト層2よりも高不純物密度のn+型の第1主電極領域(ソース領域)8が設けられている。ソース領域8及びベース領域7を貫通してトレンチ21が設けられ、トレンチ21の底面及び側面にはゲート絶縁膜10が設けられている。
次に位置ズレ幅の設定方法を説明する。図7中には、最初のアライメントマーク104が形成されるドレイン領域1の上に、例えば1枚のエピタキシャル成長膜がドリフト層2として成膜される場合が例示されている。図7に示すように互いに位置がずれた最初のアライメントマーク104及び転写されたアライメントマーク104aを、半導体装置の主面を正面視する方向から見た場合、同形状のアライメントマークが二重に観察される。
Δx=t×tanθ ・・・(1)
と設定される。
(2)第1の埋込領域5a,5bの作製にはアライメントマークAM1を用い、第2の埋込領域6a,6b及びトレンチ21の作製にはアライメントマークAM2を共通して用いた。
(3)第1の埋込領域5a,5bの作製にはアライメントマークAM1を用い、第2の埋込領域6a,6bの作製にはアライメントマークAM2を用い、トレンチ21の作製にはアライメントマークAM3を用いた。アライメントマークは共通化しなかった。
次に、図11~図21を用いて、第1の実施形態に係る半導体装置の製造方法を説明する。尚、以下に述べるトレンチゲート型MOSFETの製造方法は一例であり、特許請求の範囲に記載した趣旨の範囲であれば、これ以外の種々の製造方法により実現可能であることは勿論である。
<半導体装置の構造>
図24に示すように、第2の実施形態に係る半導体装置は、第1の隙間がベースコンタクト領域9aの<11-20>方向の下側の一端に設けられている。またベースコンタクト領域9aの<11-20>方向の上側である、第1の隙間と反対側には非コンタクト領域50が更に設けられている。非コンタクト領域50はベースコンタクト領域9a及びソース領域8のいずれよりも低不純物密度である。ベースコンタクト領域9aは<1-100>方向の幅wpを有し、非コンタクト領域50は<1-100>方向の幅waを有する。非コンタクト領域50の<1-100>方向の幅はベースコンタクト領域9aとほぼ同じである。図25に示すように第1の隙間にはベース領域7の上面が露出する。
第2の実施形態に係る半導体装置の製造方法では、第1の実施形態に係る製造方法において図11~図13を用いて説明した、ドレイン領域1の上側にベース領域7を形成する工程までは、第1の実施形態の場合と同様である。しかし第2の実施形態では、ベース領域7の上部にソース領域8となるn型の第1予定領域8pを形成する工程を、活性化後のソース領域8の開口部の<11-20>方向の幅が、位置ズレ幅Δxより大きくなるように、n型の不純物イオンの注入幅を制御して実施する。そして第1予定領域8pの開口部と同じ幅の開口部を有する、ベースコンタクト領域9aとなる第2予定領域9apを形成する点が、第1の実施形態の場合と異なる。
一方、活性化後のソース領域8の開口部の<11-20>方向の幅が位置ズレ幅Δx以下の場合、ベースコンタクト領域9aの形成が担保されない。図29中には、n型の不純物イオンの注入幅が位置ズレ幅Δxと同じ場合が例示されている。比較例の場合、p型不純物イオンはすべて第1予定領域8pに重なって注入される。そのため図30に示すように、活性化後、隣り合うソース領域8に挟まれた部分には、幅waの非コンタクト領域50が形成されるのみであり、ベースコンタクト領域が形成されない。
本発明は、図31に示すように、<11-20>方向に沿った第1の隙間に加え、<1-100>方向に沿った第2の隙間が設けられてもよい。図31中には、第1の実施形態で説明した第1の隙間に加え、<1-100>方向に沿ったベースコンタクト領域9aとソース領域8との間に、幅wgを有する第2の隙間が設けられた場合が例示されている。第2の隙間は、図31中のベースコンタクト領域9aの左右にそれぞれ設けられている。
本発明は上記の開示した実施の形態によって説明したが、この開示の一部をなす論述及び図面は、本発明を限定するものであると理解すべきではない。本開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかになると考えられるべきである。
2…ドリフト層
3…電流拡散層
4…ゲート底部保護領域
5a,5b…ベース底部埋込領域(第1の埋込領域)
6a,6b…ベース底部埋込領域(第2の埋込領域)
7…ベース領域
8…ソース領域(第1主電極領域)
8p…第1予定領域
9a,9b,19a…ベースコンタクト領域
9ap…第2予定領域
10…ゲート絶縁膜
11…ゲート埋込電極
12…層間絶縁膜
13a,13b…ソースコンタクト層
14…下部バリアメタル層
15…上部バリアメタル層
16…ソース電極
17…ドレイン電極
21…トレンチ
22…コンタクト溝
23…ベースコンタクトプラグ
33…フォトレジスト膜
31,35,35a…イオン注入用マスク
50,50b…非コンタクト領域
50p…第3予定領域
100…半導体ウェハ
101…オリエンテーションフラット
102,102a…表面
103…半導体チップ
104,104a…アライメントマーク
θ…オフ角
t…エピタキシャル成長膜の厚み
wg,wg1,wg2,wg3,wgy…隙間の幅
w1,w2…イオン注入用マスクの張り出し幅
w8p…第1予定領域の開口部の幅
wa…非コンタクト領域の幅
wp…ベースコンタクト領域の幅
Δx…アライメントマークの位置ズレ幅
Claims (11)
- 第1導電型の炭化珪素のドリフト層と、
前記ドリフト層の上に配置された第2導電型のベース領域と、
前記ベース領域の上部に選択的に埋め込まれた、前記ドリフト層よりも高不純物密度の第1導電型の第1主電極領域と、
<11-20>方向に沿った前記第1主電極領域との間に第1の隙間が形成されるように前記ベース領域の上部に選択的に埋め込まれた、前記ベース領域よりも高不純物密度の第2導電型のベースコンタクト領域と、
前記第1主電極領域と前記ドリフト層との間の前記ベース領域に接するゲート絶縁膜を介して設けられたゲート電極と、
前記ドリフト層の下面側に配置され、上面が<0001>方向に対して<11-20>方向にオフ角θを有すると共に、上面に位置決め用のアライメントマークが設けられた第1導電型の第2主電極領域と、を備え、
前記ドリフト層及び前記ベース領域のうち少なくとも一方はエピタキシャル成長膜であり、
前記第1の隙間の幅が、オフ角及びエピタキシャル成長に起因する前記アライメントマークの位置ズレ幅Δxに応じて設定され、
すべての前記エピタキシャル成長膜の厚みの和をtとした場合、前記アライメントマークの前記位置ズレ幅Δxとして、t×tanθが設定され、
前記第1の隙間の幅は、設定された前記位置ズレ幅Δx以上である
ことを特徴とする半導体装置。 - 前記ドリフト層及び前記ベース領域の両方が前記エピタキシャル成長膜である
ことを特徴とする請求項1に記載の半導体装置。 - 半導体装置は、複数のトレンチが<11-20>方向に沿ってストライプ状に延びるトレンチゲート型である
ことを特徴とする請求項1又は2に記載の半導体装置。 - トレンチの側壁の結晶面は、(11-20)a面又は(1-100)m面である
ことを特徴とする請求項3に記載の半導体装置。 - エピタキシャル成長に起因する前記位置ズレ幅Δxは、0.112μmである
ことを特徴とする請求項1~4のいずれか一項に記載の半導体装置。 - 前記第1の隙間の幅は、エピタキシャル成長に起因する前記アライメントマークの前記位置ズレ幅Δxに加え、半導体装置を位置決めする位置決め装置に起因する変動幅を更に加えて設定されている
ことを特徴とする請求項1~5のいずれか一項に記載の半導体装置。 - 前記位置決め装置に起因する前記変動幅が、0.2μmである
ことを特徴とする請求項6に記載の半導体装置。 - 第1導電型の炭化珪素のドリフト層と、
前記ドリフト層の上に配置された第2導電型のベース領域と、
前記ベース領域の上部に選択的に埋め込まれた、前記ドリフト層よりも高不純物密度の第1導電型の第1主電極領域と、
<11-20>方向に沿った前記第1主電極領域との間に第1の隙間が形成されるように前記ベース領域の上部に選択的に埋め込まれた、前記ベース領域よりも高不純物密度の第2導電型のベースコンタクト領域と、
前記第1主電極領域と前記ドリフト層との間の前記ベース領域に接するゲート絶縁膜を介して設けられたゲート電極と、
前記ドリフト層の下面側に配置され、上面が<0001>方向に対して<11-20>方向にオフ角θを有すると共に、上面に位置決め用のアライメントマークが設けられた第1導電型の第2主電極領域と、を備え、
前記ドリフト層及び前記ベース領域のうち少なくとも一方はエピタキシャル成長膜であり、
前記ベースコンタクト領域の幅が、オフ角及びエピタキシャル成長に起因する前記アライメントマークの位置ズレ幅Δxに応じて設定され、
すべての前記エピタキシャル成長膜の厚みの和をtとした場合、前記アライメントマークの前記位置ズレ幅Δxとして、t×tanθが設定され、
前記第1の隙間は<11-20>方向の一端に設けられ、
前記ベースコンタクト領域の<11-20>方向の前記第1の隙間と反対側に設けられた、前記ベースコンタクト領域及び前記第1主電極領域のいずれよりも低不純物密度の非コンタクト領域を更に備え、
前記ベースコンタクト領域の幅及び前記非コンタクト領域の幅の和が前記位置ズレ幅Δxより大きくなるように、前記ベースコンタクト領域の幅が設定されている
ことを特徴とする半導体装置。 - 更に、<1-100>方向に沿った前記ベースコンタクト領域と前記第1主電極領域との間に第2の隙間が形成されている
ことを特徴とする請求項1~8のいずれか一項に記載の半導体装置。 - 第1導電型で、上面が<0001>方向に対して<11-20>方向にオフ角θを有する炭化珪素の半導体基板の上面にアライメントマークを形成する工程と、
前記半導体基板の上に第1導電型のドリフト層を形成する工程と、
前記ドリフト層の上に第2導電型のベース領域を形成する工程と、
前記ベース領域の上部に、前記ドリフト層よりも高不純物密度の第1導電型の不純物イオンを注入して、第1主電極領域となる第1予定領域を、平面パターンで開口部を有するように選択的に形成する工程と、
前記第1予定領域の上に、開口部の<11-20>方向の端部が、隣り合う前記第1予定領域の開口部の内側に張り出して、前記第1予定領域の開口部の端部を覆うように、イオン注入用マスクを選択的にパターニングして成膜する工程と、
パターニングした前記イオン注入用マスクを介して、前記ベース領域の上部に第2導電型の不純物イオンを注入して、ベースコンタクト領域となる第2予定領域を形成する工程と、
前記第1予定領域を活性化して前記第1主電極領域を形成する工程と、
前記第2予定領域を活性化して前記ベースコンタクト領域を形成する工程と、
前記第1主電極領域と前記ドリフト層との間の前記ベース領域に接してゲート絶縁膜を成膜する工程と、
前記ゲート絶縁膜の表面上にゲート電極を形成する工程と、
前記半導体基板を第2主電極領域とする工程と、
を含み、
前記ドリフト層を形成する工程及び前記ベース領域を形成する工程のうち少なくとも一方はエピタキシャル成長によって実施し、
すべてのエピタキシャル成長膜の厚みの和をtとした場合に前記アライメントマークの位置ズレ幅Δxをt×tanθと設定し、
前記イオン注入用マスクを成膜する工程は、活性化後の前記ベースコンタクト領域と前記第1主電極領域との間に形成される<11-20>方向の隙間が、設定された前記位置ズレ幅Δx以上であるように張り出し幅を制御して実施する
ことを特徴とする半導体装置の製造方法。 - 第1導電型で、上面が<0001>方向に対して<11-20>方向にオフ角θを有する炭化珪素の半導体基板の上面にアライメントマークを形成する工程と、
前記半導体基板の上に第1導電型のドリフト層を形成する工程と、
前記ドリフト層の上に第2導電型のベース領域を形成する工程と、
前記ベース領域の上部に、前記ドリフト層よりも高不純物密度の第1導電型の不純物イオンを注入して、第1主電極領域となる第1予定領域を、平面パターンで開口部を有するように選択的に形成する工程と、
前記第1予定領域の上に、前記第1予定領域の開口部の幅と同じ幅の開口部を有するイオン注入用マスクをパターニングして成膜する工程と、
パターニングした前記イオン注入用マスクを介して、前記ベース領域の上部に第2導電型の不純物イオンを注入して、ベースコンタクト領域となる第2予定領域を形成する工程と、
前記第1予定領域を活性化して前記第1主電極領域を形成する工程と、
前記第2予定領域を活性化して前記ベースコンタクト領域を形成する工程と、
前記第1主電極領域と前記ドリフト層との間の前記ベース領域に接してゲート絶縁膜を成膜する工程と、
前記ゲート絶縁膜の表面上にゲート電極を形成する工程と、
前記半導体基板を第2主電極領域とする工程と、
を含み、
前記ドリフト層を形成する工程及び前記ベース領域を形成する工程のうち少なくとも一方はエピタキシャル成長によって実施し、
すべてのエピタキシャル成長膜の厚みの和をtとした場合に前記アライメントマークの位置ズレ幅Δxをt×tanθと設定し、
前記第1予定領域を形成する工程は、活性化後の前記第1主電極領域の開口部の<11-20>方向の幅が前記位置ズレ幅Δxより大きくなるように、不純物イオンの注入幅を制御して実施する
ことを特徴とする半導体装置の製造方法。
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