JP7163162B2 - 半導体パッケージ - Google Patents

半導体パッケージ Download PDF

Info

Publication number
JP7163162B2
JP7163162B2 JP2018231106A JP2018231106A JP7163162B2 JP 7163162 B2 JP7163162 B2 JP 7163162B2 JP 2018231106 A JP2018231106 A JP 2018231106A JP 2018231106 A JP2018231106 A JP 2018231106A JP 7163162 B2 JP7163162 B2 JP 7163162B2
Authority
JP
Japan
Prior art keywords
substrate
semiconductor chip
resin
layer
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018231106A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020096018A (ja
JP2020096018A5 (https=
Inventor
聖二 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2018231106A priority Critical patent/JP7163162B2/ja
Priority to US16/699,265 priority patent/US11705400B2/en
Priority to CN201911242024.7A priority patent/CN111293101B/zh
Publication of JP2020096018A publication Critical patent/JP2020096018A/ja
Publication of JP2020096018A5 publication Critical patent/JP2020096018A5/ja
Application granted granted Critical
Publication of JP7163162B2 publication Critical patent/JP7163162B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/016Manufacture or treatment using moulds
    • H10W74/017Auxiliary layers for moulds, e.g. release layers or layers preventing residue
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/127Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed characterised by arrangements for sealing or adhesion
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/40Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • H10W72/242Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/321Structures or relative sizes of die-attach connectors
    • H10W72/325Die-attach connectors having a filler embedded in a matrix
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/353Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/351Materials of die-attach connectors
    • H10W72/353Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)
JP2018231106A 2018-12-10 2018-12-10 半導体パッケージ Active JP7163162B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2018231106A JP7163162B2 (ja) 2018-12-10 2018-12-10 半導体パッケージ
US16/699,265 US11705400B2 (en) 2018-12-10 2019-11-29 Semiconductor package
CN201911242024.7A CN111293101B (zh) 2018-12-10 2019-12-06 半导体封装

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018231106A JP7163162B2 (ja) 2018-12-10 2018-12-10 半導体パッケージ

Publications (3)

Publication Number Publication Date
JP2020096018A JP2020096018A (ja) 2020-06-18
JP2020096018A5 JP2020096018A5 (https=) 2021-12-16
JP7163162B2 true JP7163162B2 (ja) 2022-10-31

Family

ID=70971162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018231106A Active JP7163162B2 (ja) 2018-12-10 2018-12-10 半導体パッケージ

Country Status (3)

Country Link
US (1) US11705400B2 (https=)
JP (1) JP7163162B2 (https=)
CN (1) CN111293101B (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11094625B2 (en) 2019-01-02 2021-08-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with improved interposer structure
CN114975297A (zh) * 2021-02-20 2022-08-30 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
US20230187367A1 (en) * 2021-12-10 2023-06-15 Advanced Semiconductor Engineering, Inc. Electronic package structure and method for manufacturing the same
JP7740628B2 (ja) * 2021-12-20 2025-09-17 新光電気工業株式会社 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP7841286B2 (ja) * 2022-02-28 2026-04-07 新光電気工業株式会社 電子部品内蔵基板及びその製造方法
CN115151060A (zh) * 2022-07-27 2022-10-04 无锡豪帮高科股份有限公司 一种液晶面板驱动用传感器的叠板工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134818A (ja) 2009-12-24 2011-07-07 Shinko Electric Ind Co Ltd 半導体素子内蔵基板
JP2018530160A (ja) 2015-10-02 2018-10-11 クアルコム,インコーポレイテッド 集積回路(IC)パッケージの間にギャップコントローラを備えるパッケージオンパッケージ(PoP)デバイス
US20190103364A1 (en) 2017-09-29 2019-04-04 Samsung Electronics Co., Ltd. Semiconductor package

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW423081B (en) * 1998-01-19 2001-02-21 Citizen Watch Co Ltd Semiconductor package
JP4625260B2 (ja) * 2004-02-04 2011-02-02 株式会社日立メディアエレクトロニクス 薄膜バルク共振子の製造方法
US7989707B2 (en) 2005-12-14 2011-08-02 Shinko Electric Industries Co., Ltd. Chip embedded substrate and method of producing the same
US8304296B2 (en) * 2010-06-23 2012-11-06 Stats Chippac Ltd. Semiconductor packaging system with multipart conductive pillars and method of manufacture thereof
JP6076653B2 (ja) * 2012-08-29 2017-02-08 新光電気工業株式会社 電子部品内蔵基板及び電子部品内蔵基板の製造方法
KR102245770B1 (ko) * 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US10229859B2 (en) * 2016-08-17 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10622340B2 (en) * 2016-11-21 2020-04-14 Samsung Electronics Co., Ltd. Semiconductor package
JP6917295B2 (ja) * 2017-12-25 2021-08-11 新光電気工業株式会社 電子部品内蔵基板、シート基板
KR102448248B1 (ko) * 2018-05-24 2022-09-27 삼성전자주식회사 Pop형 반도체 패키지 및 그 제조 방법
US11075151B2 (en) * 2018-06-29 2021-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with controllable standoff
US10825774B2 (en) * 2018-08-01 2020-11-03 Samsung Electronics Co., Ltd. Semiconductor package
KR102573760B1 (ko) * 2018-08-01 2023-09-04 삼성전자주식회사 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011134818A (ja) 2009-12-24 2011-07-07 Shinko Electric Ind Co Ltd 半導体素子内蔵基板
JP2018530160A (ja) 2015-10-02 2018-10-11 クアルコム,インコーポレイテッド 集積回路(IC)パッケージの間にギャップコントローラを備えるパッケージオンパッケージ(PoP)デバイス
US20190103364A1 (en) 2017-09-29 2019-04-04 Samsung Electronics Co., Ltd. Semiconductor package

Also Published As

Publication number Publication date
CN111293101B (zh) 2024-10-29
JP2020096018A (ja) 2020-06-18
US11705400B2 (en) 2023-07-18
CN111293101A (zh) 2020-06-16
US20200185326A1 (en) 2020-06-11

Similar Documents

Publication Publication Date Title
JP7163162B2 (ja) 半導体パッケージ
JP6230794B2 (ja) 電子部品内蔵基板及びその製造方法
US9935053B2 (en) Electronic component integrated substrate
JP5951414B2 (ja) 電子部品内蔵基板及び電子部品内蔵基板の製造方法
JP4830120B2 (ja) 電子パッケージ及びその製造方法
KR20080060160A (ko) 전자 부품 내장 기판
JP6454384B2 (ja) 電子部品内蔵基板及びその製造方法
JP6713289B2 (ja) 半導体装置及び半導体装置の製造方法
JP4051570B2 (ja) 半導体装置の製造方法
JP2006100385A (ja) 半導体装置
JP3972209B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2003133366A (ja) 半導体装置及びその製造方法
US12245376B2 (en) Embedded printed circuit board
JP7841286B2 (ja) 電子部品内蔵基板及びその製造方法
JP2007266640A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
KR100942772B1 (ko) 솔더 레지스트와 언더필 잉크 주입 공정이 생략된 플립 칩실장 기술
JP2007110114A (ja) パッケージ基板、半導体パッケージ及び半導体パッケージ作製方法
KR100752648B1 (ko) 솔더 조인트 신뢰성이 개선된 반도체 패키지 및 그제조방법
JPH1197574A (ja) バンプを有する電子部品
JP5794853B2 (ja) 半導体装置の製造方法
CN120727716A (zh) 电子元件内置基板及其制造方法
JP2007019378A (ja) 電子部品、その電子部品を積層してなる積層型部品モジュール及びその電子部品の製造方法
JP2010278480A (ja) 半導体装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211108

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20211108

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20220915

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20221004

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20221019

R150 Certificate of patent or registration of utility model

Ref document number: 7163162

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150