JP7158392B2 - パワー半導体モジュール - Google Patents
パワー半導体モジュール Download PDFInfo
- Publication number
- JP7158392B2 JP7158392B2 JP2019542089A JP2019542089A JP7158392B2 JP 7158392 B2 JP7158392 B2 JP 7158392B2 JP 2019542089 A JP2019542089 A JP 2019542089A JP 2019542089 A JP2019542089 A JP 2019542089A JP 7158392 B2 JP7158392 B2 JP 7158392B2
- Authority
- JP
- Japan
- Prior art keywords
- power semiconductor
- encapsulant
- semiconductor module
- semiconductor device
- support member
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 156
- 239000008393 encapsulating agent Substances 0.000 claims description 92
- 230000001681 protective effect Effects 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 33
- 229920001296 polysiloxane Polymers 0.000 claims description 21
- 239000003566 sealing material Substances 0.000 claims description 21
- 239000000945 filler Substances 0.000 claims description 5
- 229920006336 epoxy molding compound Polymers 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 description 27
- 239000002184 metal Substances 0.000 description 27
- 239000000919 ceramic Substances 0.000 description 14
- 229910000679 solder Inorganic materials 0.000 description 11
- 230000007774 longterm Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- 238000000465 moulding Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 229910010293 ceramic material Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000012864 cross contamination Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L2224/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
同様に、制御信号を分配するためのプリント回路基板(PCB)は、シリコーンゲルに埋め込まれてもよいが、封止材と接触しなくてもよい。
封止材は、保護材料と接触する接触領域を有していてもよい。封止材は、接触領域において構造化されていてもよい。接触領域は、例えば、封止材の側面に配置されており、かつパワー半導体装置から離れている。したがって、保護材は、封止材と直接に接触している。保護材は、構造化された位置または領域において、封止材と少なくとも部分的に接触している。
図1および図2に示される実施の形態を参照すると、パワー半導体モジュール10は、図示されない少なくとも1つのパワー半導体装置14を支持している支持部材12を有している。図1によれば、支持部材12は、セラミック材から形成され得る基板を含んでいる。支持部材12は、ベース板16の上に配置されている。支持部材12は、はんだ18の層によってベース板16に取り付けられている。
Claims (13)
- 少なくとも1つのパワー半導体装置(14)を支持する支持部材(12)を有するパワー半導体モジュールであって、
前記支持部材(12)は、前記パワー半導体装置(14)とともに筐体(20)内に少なくとも部分的に配置されており、
前記支持部材(12)および前記パワー半導体装置(14)は、封止材(22)によって少なくとも部分的に覆われており、
前記封止材(22)に加えて、前記筐体(20)内に保護材(24)が設けられており、
前記保護材(24)は、シリコーンゲルによって形成され、
前記保護材(24)は、前記支持部材(12)、前記パワー半導体装置(14)および前記封止材(22)のうち少なくともいずれか1つを少なくとも部分的に覆い、
前記封止材(22)は、前記保護材(24)と接触する接触領域(30)を有し、
前記接触領域(30)は、前記パワー半導体装置(14)から離れる方向に並び前記保護材(24)に入り込んでいる複数の凸部(28、32)、および/または、前記パワー半導体装置(14)から離れる方向に並んでいる、複数の凹部(34)を有している、パワー半導体モジュール。 - 少なくとも1つの前記パワー半導体装置(14)の少なくとも1つの端部(15)は、前記封止材(22)によって覆われている、請求項1に記載のパワー半導体モジュール。
- 少なくとも1つの前記パワー半導体装置(14)の自由領域は、前記封止材(22)によって完全に覆われている、請求項2に記載のパワー半導体モジュール。
- 少なくとも1つの前記パワー半導体装置(14)は、ワイヤボンディング(50)によって電気的に接続されており、
前記ワイヤボンディング(50)は、前記封止材(22)によって完全に覆われている、請求項1~3のいずれか1項に記載のパワー半導体モジュール。 - 前記支持部材(12)は、前記封止材(22)から露出している接続領域(40)を有しており、
前記接続領域(40)は、端子板(39)を受け入れられるように設計されている、請求項1~4のいずれか1項に記載のパワー半導体モジュール。 - 前記端子板(39)は、前記接続領域(40)上に配置されており、
前記端子板(39)は、前記封止材(22)から離れている、請求項5に記載のパワー半導体モジュール。 - 前記パワー半導体装置(14)は、プレスフィット端子(54)によって電気的に接続されている、請求項1~6のいずれか1項に記載のパワー半導体モジュール。
- 前記支持部材(12)は、基板を有している、請求項1~7のいずれか1項に記載のパワー半導体モジュール。
- 前記基板の自由領域は、前記封止材(22)に完全に覆われている、請求項8に記載のパワー半導体モジュール。
- 前記封止材(22)は、前記筐体(20)と直接に接触していない、請求項1~9のいずれか1項に記載のパワー半導体モジュール。
- 前記筐体(20)は、T字型に形成されており、
凸部(36)は、前記筐体(20)の内容積に入り込み、かつ前記保護材(24)と接触する、請求項1~10のいずれか1項に記載のパワー半導体モジュール。 - 前記封止材(22)は、エポキシ成形化合物およびエポキシ樹脂のいずれかによって形成されている、請求項1~11のいずれか1項に記載のパワー半導体モジュール。
- 前記封止材(22)は、フィラーを有している、請求項1~12のいずれか1項に記載のパワー半導体モジュール。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP17154673.2 | 2017-02-03 | ||
EP17154673 | 2017-02-03 | ||
PCT/EP2018/052436 WO2018141813A1 (en) | 2017-02-03 | 2018-01-31 | Power semiconductor module |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020506551A JP2020506551A (ja) | 2020-02-27 |
JP7158392B2 true JP7158392B2 (ja) | 2022-10-21 |
Family
ID=57963137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2019542089A Active JP7158392B2 (ja) | 2017-02-03 | 2018-01-31 | パワー半導体モジュール |
Country Status (5)
Country | Link |
---|---|
US (1) | US10854524B2 (ja) |
EP (1) | EP3577684B1 (ja) |
JP (1) | JP7158392B2 (ja) |
CN (1) | CN110268519A (ja) |
WO (1) | WO2018141813A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE112019002851T5 (de) * | 2018-06-06 | 2021-03-04 | Mitsubishi Electric Corporation | Halbleiterbauelement und leistungswandlervorrichtung |
US10796998B1 (en) * | 2019-04-10 | 2020-10-06 | Gan Systems Inc. | Embedded packaging for high voltage, high temperature operation of power semiconductor devices |
KR20210129483A (ko) * | 2020-04-20 | 2021-10-28 | 현대자동차주식회사 | 솔더링 구조, 이를 갖는 파워 모듈 및 파워 모듈의 제조 방법 |
US11342248B2 (en) | 2020-07-14 | 2022-05-24 | Gan Systems Inc. | Embedded die packaging for power semiconductor devices |
DE102021206587A1 (de) * | 2021-06-25 | 2022-12-29 | Robert Bosch Gesellschaft mit beschränkter Haftung | Elektrische Anordnung mit Positionierhilfe und Herstellungsverfahren |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219420A (ja) | 2009-03-18 | 2010-09-30 | Fuji Electric Systems Co Ltd | 半導体装置 |
JP2011165836A (ja) | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2013016684A (ja) | 2011-07-05 | 2013-01-24 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2015041659A (ja) | 2013-08-21 | 2015-03-02 | 株式会社三社電機製作所 | 半導体装置 |
JP2015198227A (ja) | 2014-04-03 | 2015-11-09 | 富士電機株式会社 | 半導体装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5194933A (en) | 1990-10-05 | 1993-03-16 | Fuji Electric Co., Ltd. | Semiconductor device using insulation coated metal substrate |
JP3417297B2 (ja) * | 1998-06-12 | 2003-06-16 | 株式会社日立製作所 | 半導体装置 |
JP2003086764A (ja) * | 2001-09-12 | 2003-03-20 | Toshiba Corp | 半導体装置 |
US7067905B2 (en) * | 2002-08-08 | 2006-06-27 | Micron Technology, Inc. | Packaged microelectronic devices including first and second casings |
JP2007012831A (ja) | 2005-06-30 | 2007-01-18 | Hitachi Ltd | パワー半導体装置 |
US8237260B2 (en) * | 2008-11-26 | 2012-08-07 | Infineon Technologies Ag | Power semiconductor module with segmented base plate |
JP2013055150A (ja) * | 2011-09-01 | 2013-03-21 | Toshiba Corp | 半導体装置及びその製造方法 |
US9147637B2 (en) | 2011-12-23 | 2015-09-29 | Infineon Technologies Ag | Module including a discrete device mounted on a DCB substrate |
JP5900620B2 (ja) | 2012-07-05 | 2016-04-06 | 三菱電機株式会社 | 半導体装置 |
US9418909B1 (en) * | 2015-08-06 | 2016-08-16 | Xilinx, Inc. | Stacked silicon package assembly having enhanced lid adhesion |
-
2018
- 2018-01-31 JP JP2019542089A patent/JP7158392B2/ja active Active
- 2018-01-31 CN CN201880010080.5A patent/CN110268519A/zh active Pending
- 2018-01-31 EP EP18704184.3A patent/EP3577684B1/en active Active
- 2018-01-31 WO PCT/EP2018/052436 patent/WO2018141813A1/en unknown
-
2019
- 2019-08-05 US US16/531,296 patent/US10854524B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219420A (ja) | 2009-03-18 | 2010-09-30 | Fuji Electric Systems Co Ltd | 半導体装置 |
JP2011165836A (ja) | 2010-02-09 | 2011-08-25 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP2013016684A (ja) | 2011-07-05 | 2013-01-24 | Mitsubishi Electric Corp | 半導体装置および半導体装置の製造方法 |
JP2015041659A (ja) | 2013-08-21 | 2015-03-02 | 株式会社三社電機製作所 | 半導体装置 |
JP2015198227A (ja) | 2014-04-03 | 2015-11-09 | 富士電機株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
CN110268519A (zh) | 2019-09-20 |
EP3577684A1 (en) | 2019-12-11 |
US20190363029A1 (en) | 2019-11-28 |
JP2020506551A (ja) | 2020-02-27 |
EP3577684B1 (en) | 2023-08-09 |
US10854524B2 (en) | 2020-12-01 |
WO2018141813A1 (en) | 2018-08-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP7158392B2 (ja) | パワー半導体モジュール | |
KR101505551B1 (ko) | 온도 감지소자가 장착된 반도체 파워 모듈 패키지 및 그제조방법 | |
US10720373B2 (en) | Semiconductor power device with corresponding package and related manufacturing process | |
US7868436B2 (en) | Semiconductor device | |
US20160254255A1 (en) | Power semiconductor module and composite module | |
US20130207121A1 (en) | Power conversion device | |
US9466542B2 (en) | Semiconductor device | |
US11362008B2 (en) | Power semiconductor module embedded in a mold compounded with an opening | |
US20140001613A1 (en) | Semiconductor package | |
JP4967701B2 (ja) | 電力半導体装置 | |
US9373566B2 (en) | High power electronic component with multiple leadframes | |
JP6095303B2 (ja) | 半導体装置および半導体装置の製造方法 | |
CN111799233A (zh) | 具有连接至半导体管芯的上表面处的端子的导电夹的四边封装 | |
US8810014B2 (en) | Semiconductor package including conductive member disposed between the heat dissipation member and the lead frame | |
WO2021005915A1 (ja) | 半導体装置 | |
US9099451B2 (en) | Power module package and method of manufacturing the same | |
US11417591B2 (en) | Semiconductor module | |
KR101626534B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
KR102378171B1 (ko) | 커플드 반도체 패키지 | |
US20230420318A1 (en) | Semiconductor module | |
KR102228938B1 (ko) | 커플드 반도체 패키지 | |
JP2021040113A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191007 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210120 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20211129 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20211216 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220208 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220506 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220913 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20221011 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7158392 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |