JP7131583B2 - 接合方法及び接合装置 - Google Patents
接合方法及び接合装置 Download PDFInfo
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- JP7131583B2 JP7131583B2 JP2020122432A JP2020122432A JP7131583B2 JP 7131583 B2 JP7131583 B2 JP 7131583B2 JP 2020122432 A JP2020122432 A JP 2020122432A JP 2020122432 A JP2020122432 A JP 2020122432A JP 7131583 B2 JP7131583 B2 JP 7131583B2
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- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
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Description
特許文献1 特開2012-186243号公報
Claims (17)
- 第1の基板と第2の基板とを接合する方法であって、
前記第1の基板の一部の領域に突出部を形成し、前記第1の基板の前記一部の領域以外の領域を平坦にする、形成段階と、
前記第1の基板に前記突出部が形成された状態で、前記第1の基板の位置を計測する計測段階と、
前記第1の基板の前記突出部を前記第2の基板の表面に接触させて接触領域を形成し、前記第1の基板の保持を解放して前記接触領域を拡大させることにより前記第1の基板および前記第2の基板を接合する接合段階と、
を含む接合方法。 - 第1の基板と第2の基板とを接合する方法であって、
前記第1の基板の一部の領域に突出部を形成する形成段階であって、前記第1の基板の前記一部の領域以外の領域を前記第2の基板に向けて凹状となるように湾曲させる、形成段階と、
前記第1の基板に前記突出部が形成された状態で、前記第1の基板の位置を計測する計測段階と、
前記第1の基板の前記突出部を前記第2の基板の表面に接触させて接触領域を形成し、前記第1の基板の保持を解放して前記接触領域を拡大させることにより前記第1の基板および前記第2の基板を接合する接合段階と、
を含む接合方法。 - 前記形成段階は、前記第1の基板を保持する保持部の保持面に予め設けられた突起部に前記第1の基板の前記一部の領域を当接させ、前記第1の基板の他の部分を前記保持面に保持することにより、前記第1の基板に前記突出部を形成する請求項1または2に記載の接合方法。
- 前記第1の基板に前記突出部が形成された状態で、前記第1の基板および前記第2の基板の位置合わせを行う位置合わせ段階を含む請求項1から3のいずれか一項に記載の接合方法。
- 前記接合段階において前記第2の基板を保持する請求項1から4のいずれか一項に記載の接合方法。
- 前記第2の基板を湾曲させる段階を有し、
前記接合段階では、前記第1の基板の前記突出部と、湾曲した前記第2の基板の表面とを接触させる請求項1から5のいずれか一項に記載の接合方法。 - 前記接合段階は、前記第1の基板の前記突出部を前記第2の基板に接触させた後、前記突出部および前記第2の基板の間に所定の接合強度が形成された後に、前記接触領域の拡大を開始する請求項1から6のいずれか一項に記載の接合方法。
- 前記接合段階は、前記第1の基板の前記突出部を前記第2の基板に接触させた後、前記第1の基板および前記第2の基板の少なくとも一方の振動が収束した後に、前記接触領域の拡大を開始する請求項1から7のいずれか一項に記載の接合方法。
- 前記接合段階は、前記第1の基板の前記突出部を前記第2の基板に接触させた後に前記第1の基板の保持を解放したとき、解放された前記第1の基板の振動が収束するまで、前記第1の基板の一部を保持し続けることにより、前記接触領域の拡大を抑制する段階を更に有する請求項1から8のいずれか一項に記載の接合方法。
- 前記第1の基板の前記突出部を前記第2の基板の表面に接触させる前に、少なくとも前記突出部に隣接する領域において前記第1の基板の保持を解除する段階を含む請求項1から9のいずれか一項に記載の接合方法。
- 第1の基板と第2の基板とを接合する接合装置であって、
前記第1の基板の一部の領域に突出部を形成し、前記第1の基板の前記一部の領域以外の領域を平坦にする、形成部と、
前記第1の基板に前記突出部が形成された状態で、前記第1の基板の位置を計測する計測部と、
前記第1の基板の前記突出部を前記第2の基板の表面の一部に接触させて接触領域を形成し、前記第1の基板の保持を解放して前記接触領域を拡大させることにより前記第1の基板および前記第2の基板を接合する接合部と、
を備える接合装置。 - 第1の基板と第2の基板とを接合する接合装置であって、
前記第1の基板の一部の領域に突出部を形成する形成部であって、前記第1の基板の前記一部の領域以外の領域を前記第2の基板に向けて凹状となるように湾曲させる、形成部と、
前記第1の基板に前記突出部が形成された状態で、前記第1の基板の位置を計測する計測部と、
前記第1の基板の前記突出部を前記第2の基板の表面の一部に接触させて接触領域を形成し、前記第1の基板の保持を解放して前記接触領域を拡大させることにより前記第1の基板および前記第2の基板を接合する接合部と、
を備える接合装置。 - 前記第1の基板に前記突出部が形成された状態で、前記第1の基板および前記第2の基板の位置合わせを行う位置合わせ部を備える請求項11または12に記載の接合装置。
- 前記第1の基板を保持する保持部を備え、
前記保持部は、前記第1の基板を保持する保持面を有する本体部を有し、
前記形成部は、前記本体部に設けられ、少なくとも一部が前記保持面から突出した突起部材を有し、
前記保持面に保持された前記第1の基板の一部の領域に前記突起部材が当接することにより、前記第1の基板の前記一部に前記突出部を形成する請求項11から13のいずれか一項に記載の接合装置。 - 前記保持面には凹部が形成されており、
前記突起部材は、前記凹部内に配されており、前記凹部の深さよりも大きな高さを有する当接部を有する請求項14に記載の接合装置。 - 前記突起部材は、前記本体部に対して着脱可能に固定される請求項14または15に記載の接合装置。
- 前記突起部材は、当接した前記第1の基板の一部を吸着する吸着部を有する請求項14から16のいずれか一項に記載の接合装置。
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JP2022133848A JP7435670B2 (ja) | 2016-11-16 | 2022-08-25 | 接合方法及び接合装置 |
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TW201826333A (zh) * | 2016-11-16 | 2018-07-16 | 日商尼康股份有限公司 | 保持構件、接合裝置、及接合方法 |
US11721596B2 (en) * | 2018-08-29 | 2023-08-08 | Tokyo Electron Limited | Parameter adjustment method of bonding apparatus and bonding system |
JP2020043263A (ja) * | 2018-09-12 | 2020-03-19 | キオクシア株式会社 | 半導体装置およびその製造方法 |
TWI828760B (zh) * | 2018-10-25 | 2024-01-11 | 日商尼康股份有限公司 | 基板貼合裝置、參數計算裝置、基板貼合方法及參數計算方法 |
FR3094563A1 (fr) * | 2019-03-29 | 2020-10-02 | Soitec | Procede de fabrication d’un substrat de type semi-conducteur sur isolant |
KR20220038395A (ko) * | 2019-07-25 | 2022-03-28 | 도쿄엘렉트론가부시키가이샤 | 접합 장치 및 접합 방법 |
TWI769957B (zh) * | 2021-11-25 | 2022-07-01 | 天虹科技股份有限公司 | 基板鍵合機台 |
WO2024002494A1 (de) * | 2022-07-01 | 2024-01-04 | Ev Group E. Thallner Gmbh | Verfahren zum bonden eines ersten substrats mit einem zweiten substrat, vorrichtung zum bonden und anordnung aus erstem und zweitem substrat |
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WO2016060274A1 (ja) | 2014-10-17 | 2016-04-21 | ボンドテック株式会社 | 基板どうしの接合方法、基板接合装置 |
WO2016093284A1 (ja) | 2014-12-10 | 2016-06-16 | 株式会社ニコン | 基板重ね合わせ装置および基板重ね合わせ方法 |
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- 2017-11-16 JP JP2018551689A patent/JPWO2018092861A1/ja active Pending
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Also Published As
Publication number | Publication date |
---|---|
US20210225651A1 (en) | 2021-07-22 |
JP7435670B2 (ja) | 2024-02-21 |
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KR20220098256A (ko) | 2022-07-11 |
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US11004686B2 (en) | 2021-05-11 |
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