JP7066603B2 - 配線基板および実装構造体 - Google Patents
配線基板および実装構造体 Download PDFInfo
- Publication number
- JP7066603B2 JP7066603B2 JP2018238684A JP2018238684A JP7066603B2 JP 7066603 B2 JP7066603 B2 JP 7066603B2 JP 2018238684 A JP2018238684 A JP 2018238684A JP 2018238684 A JP2018238684 A JP 2018238684A JP 7066603 B2 JP7066603 B2 JP 7066603B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- layer
- cavity
- wiring board
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Die Bonding (AREA)
Description
面が、該下面と絶縁樹脂膜とに当接する接着樹脂を介してキャビティの底面上に位置していることを特徴とするものである。
ップ絶縁樹脂層2は、絶縁粒子、およびエポキシ樹脂やポリイミド樹脂等の絶縁材料を含んでいる。
4 支持層
10,20 配線基板
9 絶縁樹脂膜
C キャビティ
Claims (3)
- 第1絶縁樹脂層と、
該第1絶縁樹脂層の上面に位置する第2絶縁樹脂層と、
前記第1絶縁樹脂層の上面に位置し、少なくとも上面外周部が前記第2絶縁樹脂層の下面に位置する導体から成る支持層と、
該支持層上の前記第2絶縁樹脂層に位置し、底面に前記支持層の少なくとも一部が露出するキャビティと、を備え、
前記キャビティの底面に、網目状の絶縁樹脂膜が、前記支持層の上面に位置していることを特徴とする配線基板。 - 前記絶縁樹脂膜が前記キャビティの底面の外周部のみに位置することを特徴とする請求項1記載の配線基板。
- 請求項1または2に記載の配線基板と、
電子部品と、を有しており、
前記電子部品の下面が、該下面と前記絶縁樹脂膜とに当接する接着樹脂を介して前記底面上に位置していることを特徴とする実装構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018238684A JP7066603B2 (ja) | 2018-12-20 | 2018-12-20 | 配線基板および実装構造体 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018238684A JP7066603B2 (ja) | 2018-12-20 | 2018-12-20 | 配線基板および実装構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020102493A JP2020102493A (ja) | 2020-07-02 |
JP7066603B2 true JP7066603B2 (ja) | 2022-05-13 |
Family
ID=71139853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018238684A Active JP7066603B2 (ja) | 2018-12-20 | 2018-12-20 | 配線基板および実装構造体 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP7066603B2 (ja) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266196A (ja) | 2006-03-28 | 2007-10-11 | Dainippon Printing Co Ltd | 多層プリント配線板及びその製造方法 |
JP2009158770A (ja) | 2007-12-27 | 2009-07-16 | Kyocer Slc Technologies Corp | 配線基板の製造方法 |
JP2010177303A (ja) | 2009-01-27 | 2010-08-12 | Panasonic Corp | 半導体装置および半導体装置に用いられる樹脂基板の製造方法 |
JP2011243751A (ja) | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | 回路基板およびその製造方法 |
JP2013520007A (ja) | 2010-02-12 | 2013-05-30 | エルジー イノテック カンパニー リミテッド | 印刷回路基板及びその製造方法 |
JP2016096292A (ja) | 2014-11-17 | 2016-05-26 | 新光電気工業株式会社 | 配線基板及び電子部品装置と配線基板の製造方法及び電子部品装置の製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10126062A (ja) * | 1996-10-24 | 1998-05-15 | Toppan Printing Co Ltd | 多層配線板 |
JP5830958B2 (ja) * | 2011-06-23 | 2015-12-09 | 日産自動車株式会社 | 半導体モジュール |
JP6228412B2 (ja) * | 2013-09-18 | 2017-11-08 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置 |
-
2018
- 2018-12-20 JP JP2018238684A patent/JP7066603B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266196A (ja) | 2006-03-28 | 2007-10-11 | Dainippon Printing Co Ltd | 多層プリント配線板及びその製造方法 |
JP2009158770A (ja) | 2007-12-27 | 2009-07-16 | Kyocer Slc Technologies Corp | 配線基板の製造方法 |
JP2010177303A (ja) | 2009-01-27 | 2010-08-12 | Panasonic Corp | 半導体装置および半導体装置に用いられる樹脂基板の製造方法 |
JP2013520007A (ja) | 2010-02-12 | 2013-05-30 | エルジー イノテック カンパニー リミテッド | 印刷回路基板及びその製造方法 |
JP2011243751A (ja) | 2010-05-18 | 2011-12-01 | Unimicron Technology Corp | 回路基板およびその製造方法 |
JP2016096292A (ja) | 2014-11-17 | 2016-05-26 | 新光電気工業株式会社 | 配線基板及び電子部品装置と配線基板の製造方法及び電子部品装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2020102493A (ja) | 2020-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10398038B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
US9893016B2 (en) | Multilayer wiring board having wiring structure for mounting multiple electronic components and method for manufacturing the same | |
US8772646B2 (en) | Printed wiring board and method for manufacturing printed wiring board | |
JP4332162B2 (ja) | 配線基板の製造方法 | |
US9872401B2 (en) | Circuit substrate and method for manufacturing the same | |
JP6092117B2 (ja) | 印刷回路基板及びその製造方法 | |
TWI336220B (en) | A method of forming a high density printed wiring board for mounting a semiconductor | |
US9723728B2 (en) | Wiring board with built-in electronic component and method for manufacturing the same | |
US20160073515A1 (en) | Wiring board with built-in electronic component and method for manufacturing the same | |
JP2015146346A (ja) | 多層配線板 | |
JP2016201424A (ja) | プリント配線板およびその製造方法 | |
US20190327830A1 (en) | Printed wiring board and method for manufacturing the same | |
TW201444440A (zh) | 配線基板及其製造方法 | |
JP7066603B2 (ja) | 配線基板および実装構造体 | |
US9837342B2 (en) | Multilayer wiring board and method for manufacturing same | |
KR101199174B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
TWI576021B (zh) | Printed wiring board and manufacturing method thereof | |
JP7111314B2 (ja) | プリント回路基板及びその製造方法 | |
JP6779088B2 (ja) | 配線基板の製造方法 | |
JP2015207710A (ja) | 配線基板 | |
US20130037312A1 (en) | High density trace formation method by laser ablation | |
TWI576020B (zh) | Printed wiring board and manufacturing method thereof | |
JP2014123592A (ja) | プリント配線板の製造方法及びプリント配線板 | |
KR101231522B1 (ko) | 인쇄회로기판 및 그의 제조 방법 | |
JP2006253176A (ja) | 基板及び電子部品の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210610 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20210830 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20220317 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220405 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220427 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7066603 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |