JP7058312B2 - シリコン系半導体デバイスの切断・パッシベーション方法、及びシリコン系半導体デバイス - Google Patents
シリコン系半導体デバイスの切断・パッシベーション方法、及びシリコン系半導体デバイス Download PDFInfo
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Description
切断プロセスを利用して前記シリコン系半導体デバイスの所定領域を切断し、前記所定領域に関連する第1表面を形成するステップと、
前記第1表面を平滑化して、前記第1表面の表面形態を調整することで、前記第1表面のうちの非縁部領域の凸部と凹部の高さの差を20nm未満にするステップと、
前記平滑化後の前記第1表面をパッシベーションして、第1パッシベーション層を前記第1表面上に形成するステップと、を含むシリコン系半導体デバイスの切断・パッシベーション方法を提供する。
前記第1表面のうちの非縁部領域を高エネルギー粒子で衝撃すること
及び/又は、荒い表面のある器具を用いて前記第1表面を摩擦するこを含む。
化学気相堆積法、物理気相堆積法、原子層堆積法、酸化パッシベーション法のうちの1種又は複数種の組み合わせにより、前記第1表面をパッシベーションすることを含み、
前記パッシベーションにおいて、前記シリコン系半導体デバイスの温度が450℃未満であり、且つ前記シリコン系半導体デバイスの温度が300℃よりも高い時間が、1200秒未満である。
又は、オゾン酸化法で前記第1表面をパッシベーションして、厚さ8nm以下の酸化ケイ素層を前記第1表面に形成する。
前記アニーリングの温度が200℃~500℃であり、且つ前記シリコン系半導体デバイスの温度が430℃よりも高い時間が、40秒未満であり、
前記アニーリングの時間が、10min以下である。
前記第4表面及び前記第5表面のそれぞれに第2パッシベーション層が存在し、前記第2パッシベーション層は窒化ケイ素膜層又は酸窒化ケイ素膜層を含む。
切断プロセスを利用して前記シリコン系半導体デバイスの所定領域を切断し、前記所定領域に関連する第1表面を形成するステップS101と、
前記第1表面を平滑化して、前記第1表面の表面形態を調整することで、前記第1表面のうちの非縁部領域の凸部と凹部の高さの差を20nm未満にするステップS102と、
前記平滑化後の前記第1表面をパッシベーションして、第1パッシベーション層を前記第1表面上に形成するステップS103と、を含むシリコン系半導体デバイスの切断・パッシベーション方法を提供する。
ここで、使用される酸化剤は、たとえば、窒素ガス、水蒸気及び酸素ガスを含む混合物である。形成する酸化ケイ素層の厚さは、≦10nm、さらに1~10nm、さらに1~8nm、さらに1~5nmなどとしてもよい。酸化処理温度は、150~250℃、さらに150~230℃、さらに160~220℃などとしてもい。酸化処理の時間は、≦30min、さらに1~30min、さらに5~25min、さらに5~20minなどとしてもい。
前記第4表面及び前記第5表面のそれぞれに第2パッシベーション層が存在し、前記第2パッシベーション層は積層構造であり得る。前記第2パッシベーション層は、窒化ケイ素膜層又は酸窒化ケイ素膜層を含み、またほかの膜層構造、たとえば、酸化アルミニウム層及び/又は酸化ケイ素層を含んでもよい。
第1パッシベーション層は、酸化ケイ素層であり、酸化反応により製造され得る。熱酸素が高温を必要とするため、表面平滑化ステップと同時に実施でき、そのステップは、具体的には以下のとおりである。
第1パッシベーション層は、酸化ケイ素層であり、オゾン酸化法により製造され得、そのステップは、具体的には以下のとおりである。
第1パッシベーション層は窒化ケイ素層であり、化学堆積法により製造され得、そのステップは、具体的には、以下のとおりである。
10-第1表面;101-第1パッシベーション層;
20-第2表面;201-低濃度ドープ層;202-高濃度ドープ層;203-正面パッシベーション層;204-正面反射防止層;205-金属電極;
30-第3表面;301-裏面パッシベーション層;302-裏面反射層;303-裏面電極;304-裏面高濃度ドープ領域;
40-第6表面;401-第3パッシベーション層。
Claims (3)
- 切断プロセスを利用して切断対象シリコン系半導体デバイスの所定領域を切断し、切断面または断裂面としての第1表面を有するシリコン系半導体デバイスを得るステップと、
前記第1表面の非縁部領域を高エネルギー粒子で衝撃することにより前記第1表面を平滑化して、前記第1表面の表面形態を調整することで、前記第1表面の非縁部領域中の凸部と凹部の高さの差を20nm未満にするステップと、
オゾン酸化法で前記平滑化後の前記第1表面をパッシベーションして、厚さが8nm以下の酸化ケイ素層である第1パッシベーション層を前記第1表面上に形成するステップと、を含むことを特徴とするシリコン系半導体デバイスの切断・パッシベーション方法。 - 前記平滑化において、前記シリコン系半導体デバイスの温度が350℃未満であり、且つ前記シリコン系半導体デバイスの温度が300℃よりも高い時間が、600秒以下である、ことを特徴とする請求項1に記載のシリコン系半導体デバイスの切断・パッシベーション方法。
- 前記第1表面にパッシベーションを行った後、前記第1表面をアニーリングし、
前記アニーリングの温度が200℃~500℃であり、且つ前記シリコン系半導体デバイスの温度が430℃よりも高い時間が、40秒未満であり、
前記アニーリングの時間が、10min以下である、ことを特徴とする請求項1または2に記載のシリコン系半導体デバイスの切断・パッシベーション方法。
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