JP6995629B2 - 演算回路 - Google Patents

演算回路 Download PDF

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Publication number
JP6995629B2
JP6995629B2 JP2018000451A JP2018000451A JP6995629B2 JP 6995629 B2 JP6995629 B2 JP 6995629B2 JP 2018000451 A JP2018000451 A JP 2018000451A JP 2018000451 A JP2018000451 A JP 2018000451A JP 6995629 B2 JP6995629 B2 JP 6995629B2
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JP
Japan
Prior art keywords
circuit
value
real
lut
values
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JP2018000451A
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English (en)
Japanese (ja)
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JP2019121171A5 (https=
JP2019121171A (ja
Inventor
健治 川合
亮 粟田
和人 武井
公昭 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Electronics Corp
NTT Inc
NTT Inc USA
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NTT Electronics Corp
Nippon Telegraph and Telephone Corp
NTT Inc USA
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Application filed by NTT Electronics Corp, Nippon Telegraph and Telephone Corp, NTT Inc USA filed Critical NTT Electronics Corp
Priority to JP2018000451A priority Critical patent/JP6995629B2/ja
Priority to US16/959,968 priority patent/US11360741B2/en
Priority to PCT/JP2018/046495 priority patent/WO2019135354A1/ja
Priority to CN201880085302.XA priority patent/CN111615700B/zh
Publication of JP2019121171A publication Critical patent/JP2019121171A/ja
Publication of JP2019121171A5 publication Critical patent/JP2019121171A5/ja
Priority to US17/643,507 priority patent/US12386591B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Complex Calculations (AREA)
  • Nonlinear Science (AREA)
JP2018000451A 2018-01-05 2018-01-05 演算回路 Active JP6995629B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2018000451A JP6995629B2 (ja) 2018-01-05 2018-01-05 演算回路
US16/959,968 US11360741B2 (en) 2018-01-05 2018-12-18 Arithmetic circuit
PCT/JP2018/046495 WO2019135354A1 (ja) 2018-01-05 2018-12-18 演算回路
CN201880085302.XA CN111615700B (zh) 2018-01-05 2018-12-18 运算电路
US17/643,507 US12386591B2 (en) 2018-01-05 2021-12-09 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018000451A JP6995629B2 (ja) 2018-01-05 2018-01-05 演算回路

Publications (3)

Publication Number Publication Date
JP2019121171A JP2019121171A (ja) 2019-07-22
JP2019121171A5 JP2019121171A5 (https=) 2021-02-04
JP6995629B2 true JP6995629B2 (ja) 2022-01-14

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ID=67144123

Family Applications (1)

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JP2018000451A Active JP6995629B2 (ja) 2018-01-05 2018-01-05 演算回路

Country Status (4)

Country Link
US (2) US11360741B2 (https=)
JP (1) JP6995629B2 (https=)
CN (1) CN111615700B (https=)
WO (1) WO2019135354A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6863907B2 (ja) * 2018-01-05 2021-04-21 日本電信電話株式会社 演算回路
US11403068B2 (en) * 2020-08-24 2022-08-02 Xilinx, Inc. Efficient hardware implementation of the exponential function using hyperbolic functions
CN114968172B (zh) * 2022-04-13 2025-10-28 深圳云豹智能股份有限公司 查找表电路、芯片及计算机设备

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2004171263A (ja) 2002-11-20 2004-06-17 Sharp Corp 演算装置
JP2004265346A (ja) 2003-03-04 2004-09-24 Sony Corp 離散コサイン変換装置および逆離散コサイン変換装置
US20050201457A1 (en) 2004-03-10 2005-09-15 Allred Daniel J. Distributed arithmetic adaptive filter and method
JP2012169926A (ja) 2011-02-15 2012-09-06 Fujitsu Ltd Ｃｒｃ演算回路

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US5226002A (en) * 1991-06-28 1993-07-06 Industrial Technology Research Institute Matrix multiplier circuit
JP3473647B2 (ja) * 1994-12-28 2003-12-08 Ｎｅｃインフロンティア株式会社 エコーサプレッサ回路
JPH0981541A (ja) * 1995-09-12 1997-03-28 Matsushita Electric Ind Co Ltd 累算器
TW302578B (en) * 1996-04-10 1997-04-11 United Microelectronics Corp The digital filter bank structure and its application method
CN1227608C (zh) * 1998-02-05 2005-11-16 英泰利克斯公司 基于n元组或随机存取存储器的神经网络分类系统和方法
JP3139466B2 (ja) * 1998-08-28 2001-02-26 日本電気株式会社 乗算器及び積和演算器
JP2000132539A (ja) * 1998-10-28 2000-05-12 Matsushita Electric Ind Co Ltd 演算装置
US6477203B1 (en) * 1998-10-30 2002-11-05 Agilent Technologies, Inc. Signal processing distributed arithmetic architecture
US6989843B2 (en) * 2000-06-29 2006-01-24 Sun Microsystems, Inc. Graphics system with an improved filtering adder tree
JP3820144B2 (ja) * 2001-12-12 2006-09-13 シャープ株式会社 信号評価装置および信号評価方法
US7007052B2 (en) * 2001-10-30 2006-02-28 Texas Instruments Incorporated Efficient real-time computation
JP4129618B2 (ja) * 2002-05-22 2008-08-06 日本電気株式会社 演算装置及び方法
US6982662B2 (en) * 2003-03-06 2006-01-03 Texas Instruments Incorporated Method and apparatus for efficient conversion of signals using look-up table
JP4086868B2 (ja) * 2005-09-06 2008-05-14 Ｎｅｃエレクトロニクス株式会社 表示装置、コントローラドライバ、近似演算補正回路、及び表示パネルの駆動方法
US8593483B2 (en) * 2009-10-20 2013-11-26 Apple Inc. Temporal filtering techniques for image signal processing
KR20120077164A (ko) * 2010-12-30 2012-07-10 삼성전자주식회사 Ｓｉｍｄ 구조를 사용하는 복소수 연산을 위한 사용하는 장치 및 방법
US20130185345A1 (en) * 2012-01-16 2013-07-18 Designart Networks Ltd Algebraic processor
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CN102681815B (zh) * 2012-05-11 2016-03-16 深圳市清友能源技术有限公司 用加法器树状结构的有符号乘累加算法的方法
KR101551641B1 (ko) * 2015-04-02 2015-09-08 한석진 비선형 데이터의 평균 계산 장치
US9489482B1 (en) * 2015-06-15 2016-11-08 International Business Machines Corporation Reliability-optimized selective voltage binning
KR102359265B1 (ko) * 2015-09-18 2022-02-07 삼성전자주식회사 프로세싱 장치 및 프로세싱 장치에서 연산을 수행하는 방법
JP6863907B2 (ja) * 2018-01-05 2021-04-21 日本電信電話株式会社 演算回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004171263A (ja) 2002-11-20 2004-06-17 Sharp Corp 演算装置
JP2004265346A (ja) 2003-03-04 2004-09-24 Sony Corp 離散コサイン変換装置および逆離散コサイン変換装置
US20050201457A1 (en) 2004-03-10 2005-09-15 Allred Daniel J. Distributed arithmetic adaptive filter and method
JP2012169926A (ja) 2011-02-15 2012-09-06 Fujitsu Ltd Ｃｒｃ演算回路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
易 茹，外３名，"遅延デジタルフィルタの分散型積和演算回路を用いたＦＰＧＡ実装の検討"，第２回電気学会東京支部栃木支所・群馬支所合同研究発表会，日本，電気学会東京支部栃木支所・群馬支所，2012年02月29日，第18-20頁，第25-26頁，［検索日 2019.03.19］インターネット：＜ＵＲＬ：https://kobaweb.ei.st.gunma-u.ac.jp/news/pdf/2011/ETT-11-07ekijo.pdf＞

Also Published As

Publication number Publication date
JP2019121171A (ja) 2019-07-22
WO2019135354A1 (ja) 2019-07-11
CN111615700B (zh) 2023-12-08
US11360741B2 (en) 2022-06-14
US12386591B2 (en) 2025-08-12
US20210064342A1 (en) 2021-03-04
CN111615700A (zh) 2020-09-01
US20220100472A1 (en) 2022-03-31

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