JP6967252B2 - 電子部品の製造方法、及び電子部品 - Google Patents

電子部品の製造方法、及び電子部品 Download PDF

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Publication number
JP6967252B2
JP6967252B2 JP2017216616A JP2017216616A JP6967252B2 JP 6967252 B2 JP6967252 B2 JP 6967252B2 JP 2017216616 A JP2017216616 A JP 2017216616A JP 2017216616 A JP2017216616 A JP 2017216616A JP 6967252 B2 JP6967252 B2 JP 6967252B2
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Japan
Prior art keywords
plating
plating layer
layer
nickel
phosphorus
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Application number
JP2017216616A
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English (en)
Japanese (ja)
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JP2019085631A5 (enExample
JP2019085631A (ja
Inventor
怜史 大矢
由加利 小野
早紀 中木原
廣一 志方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualtec Co Ltd
Original Assignee
Qualtec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Qualtec Co Ltd filed Critical Qualtec Co Ltd
Priority to JP2017216616A priority Critical patent/JP6967252B2/ja
Publication of JP2019085631A publication Critical patent/JP2019085631A/ja
Publication of JP2019085631A5 publication Critical patent/JP2019085631A5/ja
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Publication of JP6967252B2 publication Critical patent/JP6967252B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Die Bonding (AREA)
  • Chemically Coating (AREA)
JP2017216616A 2017-11-09 2017-11-09 電子部品の製造方法、及び電子部品 Active JP6967252B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017216616A JP6967252B2 (ja) 2017-11-09 2017-11-09 電子部品の製造方法、及び電子部品

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017216616A JP6967252B2 (ja) 2017-11-09 2017-11-09 電子部品の製造方法、及び電子部品

Publications (3)

Publication Number Publication Date
JP2019085631A JP2019085631A (ja) 2019-06-06
JP2019085631A5 JP2019085631A5 (enExample) 2020-11-26
JP6967252B2 true JP6967252B2 (ja) 2021-11-17

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JP2017216616A Active JP6967252B2 (ja) 2017-11-09 2017-11-09 電子部品の製造方法、及び電子部品

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JP (1) JP6967252B2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7306712B2 (ja) * 2019-07-26 2023-07-11 株式会社クオルテック ヒータチップ及び接合層評価装置
CN112259383B (zh) * 2020-10-19 2022-02-22 南京工程学院 一种包覆钼酸镍铜复合膜的电极原位制备方法
JP2023079124A (ja) 2021-11-26 2023-06-07 国立大学法人東北大学 パワー半導体素子及びパワー半導体モジュール

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3910363B2 (ja) * 2000-12-28 2007-04-25 富士通株式会社 外部接続端子
CN102738107B (zh) * 2006-05-29 2014-08-27 瑞萨电子株式会社 电子部件、半导体封装件和电子器件
JP5450192B2 (ja) * 2010-03-24 2014-03-26 日立オートモティブシステムズ株式会社 パワーモジュールとその製造方法
JP6569511B2 (ja) * 2015-12-17 2019-09-04 三菱マテリアル株式会社 接合体、冷却器付きパワーモジュール用基板、冷却器付きパワーモジュール用基板の製造方法

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