JP6958259B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6958259B2 JP6958259B2 JP2017215728A JP2017215728A JP6958259B2 JP 6958259 B2 JP6958259 B2 JP 6958259B2 JP 2017215728 A JP2017215728 A JP 2017215728A JP 2017215728 A JP2017215728 A JP 2017215728A JP 6958259 B2 JP6958259 B2 JP 6958259B2
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- Prior art keywords
- conductor plate
- conductive block
- surface side
- side conductor
- groove
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 71
- 239000004020 conductor Substances 0.000 claims description 128
- 229910000679 solder Inorganic materials 0.000 claims description 85
- 229920005989 resin Polymers 0.000 description 31
- 239000011347 resin Substances 0.000 description 31
- 239000007788 liquid Substances 0.000 description 16
- 238000000034 method Methods 0.000 description 12
- 230000001771 impaired effect Effects 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 8
- 238000005476 soldering Methods 0.000 description 8
- 238000005304 joining Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000011265 semifinished product Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
本実施例では、導電ブロック26からみて溝22aの中心よりも遠位側の少なくとも一部に酸化層23が形成されている。酸化層23は液状はんだに濡れにくいために、導電ブロック26に上面側導体板22をはんだ接合する工程で導電ブロック26と上面側導体板22との間から漏れ出たはんだは、酸化層23によってせき止められ、遠位側に膨出する凸形状を形成し、その形状下で硬化する。この場合、溝22a内に流入したはんだの表面形状の再現性が高く、導電ブロック26を一巡する溝22aの長さに沿って観察したときに、液状はんだの断面の一様化が高い。そのために、溝22a内に漏れ出たはんだが硬化する際に導電ブロック26と上面側導体板22の間で硬化するはんだ層24の厚みに与える影響の大きさも一様化される。はんだ接合することで導電ブロック26と上面側導体板22の間の平行度が損なわれることを抑制することができる。
続いて、図6を参照して、参考例を説明する。図6は、図3(c)に対応する。参考例では、溝22aに代えて、溝22cが上面側導体板22に設けられている点が、上記の実施例とは異なる。以下では、上記の実施例と異なる点のみを説明し、上記の実施例と同様の点の説明は省略する。図6は、上面側導体板22に設けられている溝22cの拡大図を示す。溝22cでは、実施例の溝22aにおいて酸化層23が形成されていた部分において、溝が形成されていない。換言すれば、溝22cには、導電ブロック26からみて溝22cの中心よりも遠位側に壁が形成されている。参考例の構成によっても、導電ブロック26に上面側導体板22を接合する工程において、導電ブロック26と上面側導体板22との間から漏れ出たはんだが、壁によってせき止められるので、溝22c内のはんだが遠位側に膨出する凸形状を有する。従って、溝内に流入したはんだの表面形状の再現性が高く、溝22cの長さに沿って観察したときに、液状はんだの断面の一様化が高い。また、溝22c内に漏れ出たはんだが硬化する際に導電ブロック26と上面側導体板22の間で硬化するはんだ層24の厚みに与える影響の大きさも一様化される。はんだ接合することで導電ブロック26と上面側導体板22の間の平行度が損なわれることを抑制することができる。
20:第1積層体
40:第2積層体
22,42:上面側導体板
22a,22c,42a:溝
23,43:酸化層
22b,54a:接合部
24,28,32,44,48,52:はんだ層
26,46:導電ブロック
30,50:半導体素子
34,54:下面側導体板
36:モールド樹脂
Claims (1)
- 平面状に延びている電極が形成されている半導体素子と、
前記半導体素子の前記電極に接合されている導電ブロックと、
前記導電ブロックの前記半導体素子が接合されている側と反対側の面に、はんだ層を介して接合されている導体板を備えており、
前記導体板には、前記導電ブロックが接合されている面において、前記導電ブロックを一巡する溝が設けられており、
前記溝には、前記導電ブロックからみて前記溝の中心よりも遠位側の少なくとも一部に酸化層が形成されており、
前記溝内のはんだが、前記遠位側に膨出する凸形状を有する、半導体装置。
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JP2017215728A JP6958259B2 (ja) | 2017-11-08 | 2017-11-08 | 半導体装置 |
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JP2017215728A JP6958259B2 (ja) | 2017-11-08 | 2017-11-08 | 半導体装置 |
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JP2019087669A JP2019087669A (ja) | 2019-06-06 |
JP6958259B2 true JP6958259B2 (ja) | 2021-11-02 |
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Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4609172B2 (ja) * | 2005-04-21 | 2011-01-12 | 株式会社デンソー | 樹脂封止型半導体装置 |
JP2012142521A (ja) * | 2011-01-06 | 2012-07-26 | Mitsubishi Electric Corp | 電力用半導体装置 |
JP5325917B2 (ja) * | 2011-03-17 | 2013-10-23 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP5921322B2 (ja) * | 2012-05-11 | 2016-05-24 | 三菱電機株式会社 | 半導体モジュールの製造方法 |
JP6114149B2 (ja) * | 2013-09-05 | 2017-04-12 | トヨタ自動車株式会社 | 半導体装置 |
WO2016092791A1 (ja) * | 2014-12-10 | 2016-06-16 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2016178261A (ja) * | 2015-03-23 | 2016-10-06 | カルソニックカンセイ株式会社 | ハンダ付け構造 |
JP6468085B2 (ja) * | 2015-06-11 | 2019-02-13 | 株式会社デンソー | 基板、および、その製造方法 |
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