JP6938118B2 - 表面実装形薄膜抵抗ネットワーク - Google Patents
表面実装形薄膜抵抗ネットワーク Download PDFInfo
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- JP6938118B2 JP6938118B2 JP2016126651A JP2016126651A JP6938118B2 JP 6938118 B2 JP6938118 B2 JP 6938118B2 JP 2016126651 A JP2016126651 A JP 2016126651A JP 2016126651 A JP2016126651 A JP 2016126651A JP 6938118 B2 JP6938118 B2 JP 6938118B2
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- 239000010409 thin film Substances 0.000 title claims description 16
- 239000011347 resin Substances 0.000 claims description 28
- 229920005989 resin Polymers 0.000 claims description 28
- 239000000725 suspension Substances 0.000 claims description 10
- 239000010408 film Substances 0.000 claims description 9
- 238000010292 electrical insulation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H01C1/00—Details
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- H01C1/00—Details
- H01C1/02—Housing; Enclosing; Embedding; Filling the housing or enclosure
- H01C1/034—Housing; Enclosing; Embedding; Filling the housing or enclosure the housing or enclosure being formed as coating or mould without outer sheath
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Non-Adjustable Resistors (AREA)
Description
Claims (4)
- 薄膜抵抗集積アレイを形成したチップと、
該チップを固定したアイランドと、
該アイランド周辺を囲み外方に伸びる複数のリード端子と、
前記チップに形成した抵抗の電極と前記リード端子を接続したワイヤと、
該ワイヤを含む部分を封止したモールド樹脂と、を備え、
前記アイランドから延伸する吊りリードは二股に分かれており、前記モールド樹脂で封止したパッケージ端面において、前記二股に分かれている部分が切断されていて、前記パッケージ端面から露出した前記吊りリードの切断部に電気的絶縁が施されており、
前記切断部は、前記パッケージ端面の中央よりも外側に位置していることを特徴とする表面実装形薄膜抵抗ネットワーク。 - 前記切断部は、絶縁性の樹脂によって覆われていることを特徴とする請求項1に記載の表面実装形薄膜抵抗ネットワーク。
- 前記切断部は、無機質の膜によって覆われていることを特徴とする請求項1に記載の表面実装形薄膜抵抗ネットワーク。
- アイランドと、該アイランド周辺を囲み外方に伸びる複数のリード端子と、該リード端子を連結する外枠部と、前記アイランドを外枠部に連結し、二股に分かれている吊りリードと、前記リード端子に交差して複数の該リード端子を連結するタイバーとを含むリードフレームを準備し、
薄膜抵抗集積アレイを形成したチップを前記アイランドに固定し、
前記チップの抵抗の電極と前記リード端子をワイヤにより接続し、
該ワイヤにより接続した部分を含めてモールド樹脂で封止し、
前記外枠部と前記タイバーの連結部とを含む前記リード端子に連結した不要部を切断し、前記吊りリードの前記二股に分かれている部分を前記モールド樹脂で封止した端面において切断し、
前記モールド樹脂で封止した前記端面から露出し、前記端面の中央よりも外側に位置する前記吊りリードの切断部に電気的絶縁を施すことを特徴とする表面実装形薄膜抵抗ネットワークの製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016126651A JP6938118B2 (ja) | 2016-06-27 | 2016-06-27 | 表面実装形薄膜抵抗ネットワーク |
CN201780037034.XA CN109314091B (zh) | 2016-06-27 | 2017-06-02 | 表面安装型薄膜电阻网络 |
US16/311,858 US20190198203A1 (en) | 2016-06-27 | 2017-06-02 | Surface-mountable thin film resistor network |
PCT/JP2017/020591 WO2018003402A1 (ja) | 2016-06-27 | 2017-06-02 | 表面実装形薄膜抵抗ネットワーク |
DE112017003204.0T DE112017003204T5 (de) | 2016-06-27 | 2017-06-02 | Oberflächen-anbringbares dünnfilmwiderstandsnetzwerk |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016126651A JP6938118B2 (ja) | 2016-06-27 | 2016-06-27 | 表面実装形薄膜抵抗ネットワーク |
Publications (2)
Publication Number | Publication Date |
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JP2018006376A JP2018006376A (ja) | 2018-01-11 |
JP6938118B2 true JP6938118B2 (ja) | 2021-09-22 |
Family
ID=60787073
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2016126651A Active JP6938118B2 (ja) | 2016-06-27 | 2016-06-27 | 表面実装形薄膜抵抗ネットワーク |
Country Status (5)
Country | Link |
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US (1) | US20190198203A1 (ja) |
JP (1) | JP6938118B2 (ja) |
CN (1) | CN109314091B (ja) |
DE (1) | DE112017003204T5 (ja) |
WO (1) | WO2018003402A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102023126249A1 (de) | 2022-09-28 | 2024-03-28 | Koa Corporation | Elektronisches Bauteil |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP7397783B2 (ja) * | 2019-11-21 | 2023-12-13 | 順▲徳▼工業股▲分▼有限公司 | リードフレームストリップ |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4484213A (en) * | 1982-02-19 | 1984-11-20 | Solitron Devices, Inc. | Binary weighted resistor and package |
JPS5963736A (ja) * | 1982-10-04 | 1984-04-11 | Matsushita Electronics Corp | 樹脂封止型半導体装置の製造方法 |
JPS6164143A (ja) * | 1984-09-05 | 1986-04-02 | Nec Corp | 樹脂封止半導体装置 |
JPS61208257A (ja) * | 1985-03-12 | 1986-09-16 | Matsushita Electric Ind Co Ltd | 集積回路装置 |
JP2013153129A (ja) * | 2011-09-29 | 2013-08-08 | Rohm Co Ltd | チップ抵抗器および抵抗回路網を有する電子機器 |
JP6284397B2 (ja) * | 2014-03-10 | 2018-02-28 | エイブリック株式会社 | 半導体装置及びその製造方法 |
US20170323708A1 (en) * | 2016-05-03 | 2017-11-09 | Texas Instruments Incorporated | Component sheet and method of singulating |
-
2016
- 2016-06-27 JP JP2016126651A patent/JP6938118B2/ja active Active
-
2017
- 2017-06-02 CN CN201780037034.XA patent/CN109314091B/zh active Active
- 2017-06-02 US US16/311,858 patent/US20190198203A1/en not_active Abandoned
- 2017-06-02 DE DE112017003204.0T patent/DE112017003204T5/de active Pending
- 2017-06-02 WO PCT/JP2017/020591 patent/WO2018003402A1/ja active Application Filing
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102023126249A1 (de) | 2022-09-28 | 2024-03-28 | Koa Corporation | Elektronisches Bauteil |
Also Published As
Publication number | Publication date |
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CN109314091A (zh) | 2019-02-05 |
JP2018006376A (ja) | 2018-01-11 |
DE112017003204T5 (de) | 2019-03-07 |
CN109314091B (zh) | 2022-07-05 |
US20190198203A1 (en) | 2019-06-27 |
WO2018003402A1 (ja) | 2018-01-04 |
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