JP6937296B2 - インターポーザなし積層ダイ相互接続 - Google Patents
インターポーザなし積層ダイ相互接続 Download PDFInfo
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- JP6937296B2 JP6937296B2 JP2018519378A JP2018519378A JP6937296B2 JP 6937296 B2 JP6937296 B2 JP 6937296B2 JP 2018519378 A JP2018519378 A JP 2018519378A JP 2018519378 A JP2018519378 A JP 2018519378A JP 6937296 B2 JP6937296 B2 JP 6937296B2
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Description
集積回路(IC)アーキテクチャは、単一のパッケージ中に複数の異種機能を組入れるように進化した。その場合、各々の機能は、別個のICダイまたはチップスケールパッケージ(CSP)によって果たされる。そのようなアーキテクチャは、システムインパッケージ(SiP)と称されることがある。ある種類のSiPアーキテクチャは、複数のICダイをインターポーザに搭載することに係り、その上でインターポーザがパッケージ基板に搭載される。インターポーザは、シリコン貫通ビア(TSV)とも称されるダイ貫通ビア(TDV)を含み、その上面および下面の両方でメタライゼーション層を接続する。メタライゼーション層を用いて、複数のICダイの相互の間のおよび複数のICダイの各々の間の電気信号をパッケージ基板に搬送する。この種類のSiPアーキテクチャは、2.5次元(2.5D)パッケージと称されることがある。しかしながら、SiPパッケージのために2.5Dアーキテクチャを用いるとコストが大幅に増大する。というのも、別個のインターポーザを設計し、製造し、かつ試験しなければならないからである。
ダイからダイへの相互接続のための相互接続ダイを有する半導体アセンブリ、ICパッケージ、製造のための方法、およびICパッケージ中で信号をルーティングするための方法を提供するための技術が記載される。1つの実現例では、対向する側に第1の表面および第2の表面が規定される本体を含む相互接続ダイが設けられる。本体の第1の表面上に第1の複数の導電パッドと第2の複数の導電パッドとが形成される。第2の複数の導電パッドは、グループ化され、別個の集積回路(IC)ダイと相互接続ダイとの間で信号を渡すために電気的ダイ間接続部を介してICダイが相互接続ダイに物理的かつ電気的に接続するのを可能にするように構成される向きに第1の複数の導電パッドから物理的に離間される。本体は、第2の複数の導電パッドのうちの選択されるものとの接続のために第1の複数の導電パッドのうち1つを選択するように動作可能な固体回路構成を備える相互接続回路を含む。
任意に、相互接続ダイは、ICダイのうち少なくとも1つよりも小さな計画面積(plan area)を有してもよい。
任意に、半導体アセンブリは、ダイ間接続部によってICダイのうち少なくとも1つに結合される第2の相互接続ダイをさらに含んでもよい。
任意に、第1の相互接続ダイは、ICダイのうち少なくとも1つよりも小さな計画面積を有してもよい。
別の実現例では、集積回路(IC)パッケージが設けられる。ICパッケージは、パッケージ基板と、第1の相互接続ダイと、第1の集積回路(IC)ダイおよび第2のICダイとを含む。第1の相互接続ダイは、ダイ間接続部によってICダイに結合される。パッケージ基板は、複数の電気的相互接続部によってICダイおよび第1の相互接続ダイに結合される。
以上記載した特徴を詳細に理解することができる態様のために、例示的な実現例を参照することによって、以上で簡単に要約した説明のより特定的な説明を有し得、その一部を添付の図面で示す。しかしながら、添付の図面は典型的な例示的な実現例を示すにすぎず、したがってその範囲を限定するものと考えるべきではないことに留意すべきである。
理解を容易にするため、可能な場合は、図同士で共通の同一要素を指定するのに同一の参照番号を用いた。有益な場合は1つの例の中の要素を他の例に組入れることがあることが企図される。
Claims (14)
- 相互接続ダイであって、
対向側に第1の表面および第2の表面が規定されるダイ本体と、
前記ダイ本体の前記第1の表面上に形成される第1の複数の導電パッドと、
前記ダイ本体の前記第1の表面上に形成される第2の複数の導電パッドとを備え、前記第2の複数の導電パッドは、グループ化されて、別個の集積回路(IC)ダイと前記相互接続ダイとの間で信号を渡すために電気的ダイ間接続部を介して前記ICダイが前記相互接続ダイに物理的かつ電気的に接続するのを可能にするように構成される向きに前記第1の複数の導電パッドから物理的に離間され、さらに
前記ダイ本体の中に配設され、かつ前記第2の複数の導電パッドのうち選択される1つとの双方向接続のために前記第1の複数の導電パッドのうち1つを選択するように動作可能な固体回路構成を備える相互接続回路を備え、
前記固体回路構成は、前記相互接続ダイを通してデータをパイプライン化することと、前記相互接続ダイ上にプログラマブルポイントツーポイントネットワークを形成することとのうち少なくとも1つを行なうように動作可能な複数のプログラマブル素子を備え、前記複数のプログラマブル素子の各々は、バイパス機能を有する、相互接続ダイ。 - 電気的ダイ間接続部を介して前記第1の複数の導電パッドに結合される第1のICダイと、
電気的ダイ間接続部を介して前記第2の複数の導電パッドに結合される第2のICダイとをさらに備え、前記第1および第2のICダイは同じ種類のダイではない、請求項1に記載の相互接続ダイ。 - 前記ダイ本体は、前記第1の表面と前記第2の表面との間に規定される250ミクロン未満の厚みを備える、請求項1に記載の相互接続ダイ。
- 前記ダイ本体の前記第1の表面上に形成される第3の複数の導電パッドをさらに備え、前記第3の複数の導電パッドは、グループ化されて、1つ以上の別個の集積回路(IC)ダイと前記相互接続ダイとの間で信号を渡すために電気的ダイ間接続部を介して前記ICダイが前記相互接続ダイに物理的かつ電気的に接続するのを可能にするように構成される向きに前記第1および第2の複数の導電パッドから物理的に離間され、前記相互接続回路は、前記第3の複数の導電パッドのうち選択される1つとの接続のために前記第1または第2の複数の導電パッドのうち1つを選択するよう動作可能である、請求項1に記載の相互接続ダイ。
- 前記ダイ本体の前記第1の表面と前記第2の表面との間に延在する複数のビアをさらに備え、前記ビアは、1つ以上の第2の別々の領域とは別のかつ異なる1つ以上の第1の別々の領域に配置され、前記複数の導電パッドは、前記1つ以上の第2の別々の領域の中に閉じ込められる前記固体回路構成に選択的に結合され、前記ダイ本体の前記第1の表面と前記第2の表面との間に延在するビアは前記1つ以上の第2の別々の領域の中には存在しない、請求項1に記載の相互接続ダイ。
- 前記相互接続ダイは、前記ICダイのうち少なくとも1つよりも小さな計画面積を有する、請求項1に記載の相互接続ダイ。
- 半導体アセンブリであって、
第1の集積回路(IC)ダイと、
第2のICダイと、
ダイ間接続によって前記ICダイに結合される第1の相互接続ダイとを備え、前記第1の相互接続ダイは、前記第1の相互接続ダイを通して前記ICダイ同士の間にプログラマブル双方向信号伝送経路を設ける固体回路構成を有し、前記固体回路構成は、前記第1の相互接続ダイ上に形成される第2の複数の導電パッドのうち任意の1つとの接続のために、前記第1の相互接続ダイ上に形成される第1の複数の導電パッドのうち任意の1つとの間の前記双方向信号伝送経路のルーティングを選択するように動作可能であり、
前記第1の相互接続ダイの前記固体回路構成は、前記第1の相互接続ダイを通してデータをパイプライン化することと、前記第1の相互接続ダイ上にプログラマブルポイントツーポイントネットワークを形成することとのうち少なくとも1つを行なうように動作可能な複数のプログラマブル素子を備え、前記複数のプログラマブル素子の各々は、バイパス機能を有する、
半導体アセンブリ。 - 前記第1のICダイから延在する複数の導電性ピラーと、
前記導電性ピラーの遠端と実質的に同一平面上にあるオーバーモールドの表面とをさらに備える、請求項7に記載の半導体アセンブリ。 - ダイ間接続部によって前記ICダイのうち少なくとも1つに結合される第2の相互接続ダイをさらに備える、請求項7に記載の半導体アセンブリ。
- 複数の電気的相互接続部によって前記ICダイに結合されるパッケージ基板をさらに備え、前記パッケージ基板は、複数の電気的相互接続部によって前記第1の相互接続ダイに結合される、請求項7に記載の半導体アセンブリ。
- 前記第1の相互接続ダイは、前記ICダイのうち少なくとも1つよりも小さな計画面積を有する、請求項7に記載の半導体アセンブリ。
- ダイ間接続部によって前記第1の相互接続ダイに結合される少なくとも第3のICダイをさらに備え、前記固体回路構成は、前記第1の相互接続ダイを通して、前記第1、第2、および少なくとも第3のICダイの間にプログラマブルポイントツーポイント信号伝送経路を設けるように構成される、請求項7に記載の半導体アセンブリ。
- 第1の相互接続ダイは80ミクロン未満の厚みをさらに備える、請求項7に記載の半導体アセンブリ。
- 第1の側を有するパッケージ基板をさらに備え、前記ICダイの各々の底面は第1の複数の電気的相互接続部によって前記パッケージ基板の前記第1の側に直接に結合され、前記第1の側は、第2の複数の電気的相互接続部によって前記第1の相互接続ダイの底面に直接に結合され、前記第1の相互接続ダイの頂面は、前記ダイ間接続によって前記ICダイの各々の前記底面に結合される、請求項7に記載の半導体アセンブリ。
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