JP6924232B2 - Imaging device and its manufacturing method and camera - Google Patents

Description

The present invention relates to an image pickup apparatus, a method for manufacturing the same, and a camera.

In the image pickup apparatus, the image quality deteriorates when an afterimage occurs. The cause of the afterimage is the presence of oxygen in silicon. Patent Document 1 relates to a solid-state image sensor, and the document describes that the lower the oxygen concentration in the semiconductor substrate, the smaller the afterimage.

Japanese Unexamined Patent Publication No. 2007-251074

Patent Document 1 is not sufficiently studied for suppressing afterimages. Therefore, in the solid-state image sensor described in Patent Document 1, afterimages may occur in pixels in which the oxygen concentration is not sufficiently reduced.

The present invention has been made in the wake of the above-mentioned problem recognition, and an object of the present invention is to provide an advantageous technique for suppressing the occurrence of afterimages.

One aspect of the present technology is related to the manufacturing method of the image pickup apparatus, and the manufacturing method has an oxygen concentration of 2 × 10. ¹⁶ atoms / cm ³ Above 4x10 ¹⁷ atoms / cm ³ It has a wafer having a first semiconductor region made of single crystal silicon within the following range, and a second semiconductor region made of single crystal silicon arranged on the wafer and having an oxygen concentration lower than that of the first semiconductor region. A step of preparing a substrate containing a silicon layer, a step of forming a trench in the silicon layer of the substrate, and a step of forming a trench in the silicon layer of the substrate, and a step of forming a trench on the substrate in an oxygen-containing atmosphere so that the inner surface of the trench is oxidized. The first heat treatment was performed to reduce the oxygen concentration in the second semiconductor region to 2 × 10. ¹⁶ atoms / cm ³ Above 4x10 ¹⁷ atoms / cm ³ Oxygen is contained after the step of setting the temperature within the following range, the step of forming a conductive type impurity region opposite to the conductive type of the second semiconductor region along the inner surface of the trench, and the formation of the impurity region. The second heat treatment is performed on the substrate in an atmosphere where the substrate is not used to reduce the oxygen concentration on the surface of the substrate, but the oxygen concentration in the second semiconductor region is reduced by 2 × 10. ¹⁶ atoms / cm ³ Above 4x10 ¹⁷ atoms / cm ³ It includes a step of maintaining within the following range and a step of forming a charge storage portion of the photoelectric conversion element in the second semiconductor region after the second heat treatment.

Further, another aspect of the present technology is that the image pickup apparatus has a pixel portion in which a plurality of pixels are arranged on a substrate made of silicon and a periphery arranged around the pixel portion on the substrate. An image pickup apparatus comprising a circuit section including a peripheral circuit section including a circuit for processing a signal from each pixel, and the peripheral circuit section includes a transistor having a VDD region containing at least one of nickel and cobalt. Each pixel is formed in the first conductive type region including a portion formed on the substrate and accumulating the charge generated by photoelectric conversion, and the first region deeper than the first region of the substrate. The second region of the first conductive type arranged at a position away from the region and the second conductive region arranged between the first region and the second region in the depth direction from the surface of the substrate. It has a third region of the mold, and the third region is arranged at a position away from the second region in the depth direction, and the net impurity concentration of the second conductive mold has a first maximum value. A first portion including the indicated position and a second portion arranged between the first portion and the second region in the depth direction, the net impurity concentration of the second conductive type is lower than the first maximum value. A second portion including a position showing a two maximum value is included, and the oxygen concentration of the second portion is 1 × 10 ¹⁷ [atoms / cm ³ ] or less.

According to the present invention, an advantageous technique for suppressing the generation of afterimages is provided.

The figure which shows typically the cross-sectional structure of the image pickup apparatus of one Embodiment of this invention. The figure for exemplifying the manufacturing method of the image pickup apparatus of one Embodiment of this invention. The figure for exemplifying the manufacturing method of the image pickup apparatus of one Embodiment of this invention. The figure for exemplifying the manufacturing method of the image pickup apparatus of one Embodiment of this invention. The figure for exemplifying the manufacturing method of the image pickup apparatus of one Embodiment of this invention. The figure which shows the distribution of the oxygen concentration in the depth direction of the semiconductor substrate about the Embodiment and the comparative example (before the implementation of a heat treatment step). The figure which shows the distribution of the oxygen concentration in the depth direction of the semiconductor substrate about the Embodiment and the comparative example (after the heat treatment step in the atmosphere containing oxygen). The figure which shows the distribution of the oxygen concentration in the depth direction of the semiconductor substrate about the Embodiment and the comparative example (after the heat treatment step in the atmosphere containing oxygen and the heat treatment step in the atmosphere which does not contain oxygen). The figure which shows the distribution of oxygen concentration in the semiconductor substrate of the manufactured image pickup apparatus. The figure for demonstrating the example of the structure of the image pickup apparatus. The figure for demonstrating the impurity concentration distribution and the oxygen concentration distribution in a substrate. The figure for demonstrating the oxygen concentration dependence in a substrate about the afterimage in an image, and the judgment result about an afterimage and a white scratch. The figure for demonstrating the example of the manufacturing method of an image pickup apparatus. The figure for demonstrating the example of the formation method of the element separation part. The figure for demonstrating the configuration example of a camera. The figure for demonstrating the element separation part. The figure for demonstrating the element separation part. The figure for demonstrating the element separation part.

Hereinafter, the present invention will be described with reference to the accompanying drawings through an exemplary first embodiment.

In the image pickup apparatus, the image quality deteriorates when an afterimage occurs. The cause of the afterimage is the presence of oxygen in silicon. Japanese Unexamined Patent Publication No. 2007-251074 relates to an image sensor. Japanese Unexamined Patent Publication No. 2007-251074 describes that the lower the oxygen concentration in the semiconductor substrate, the smaller the afterimage. As a specific example, JP 2007-251074, it is described that the oxygen concentration to form a ^{13.3 × 10 17 ~13.7 × 10 17} / cm 3 range silicon substrate photodiode ing. Japanese Unexamined Patent Publication No. 2010-34195 relates to silicon wafers such as epitaxial wafers. According to Japanese Patent Application Laid-Open No. 2010-34195, a silicon wafer having a concentration distribution having a maximum value and a minimum value of solid solution oxygen at a fixed depth is obtained by subjecting the wafer to rapid elevating and heating heat treatment in an oxygen gas atmosphere. It is stated that.

If the gradient of oxygen concentration in the depth direction of the semiconductor substrate for forming the image pickup apparatus is large, the degree of oxygen diffusion may vary due to a process error in the manufacturing stage. As a result, the oxygen concentration may vary among the plurality of manufactured image pickup devices. Then, an afterimage may occur in an individual whose oxygen concentration is not sufficiently reduced. Alternatively, there may be a distribution of oxygen concentration between the pixels in the imaging device. Then, an afterimage may occur in the pixel where the oxygen concentration is not sufficiently reduced.

The present embodiment was made with the above-mentioned recognition of the problem as an opportunity, and an object of the present embodiment is to provide an advantageous technique for suppressing the occurrence of afterimages.

One aspect of this embodiment is (a) a first semiconductor region made of single crystal silicon having an ^{oxygen concentration in the range of 2 × 10 16} atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ^{3 or less.}
A second semiconductor region arranged on the first semiconductor region and made of single crystal silicon having an oxygen concentration lower than that of the first semiconductor region,
And the process of preparing the semiconductor substrate including
(B) A step of heat-treating the semiconductor substrate in an oxygen-containing atmosphere to bring the oxygen concentration in the second semiconductor region within the range ^{of 2 × 10 16} atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ^{3 or less.} When,
(C) The step of forming a photoelectric conversion element in the second semiconductor region is included.

According to the present embodiment, an advantageous technique for suppressing the generation of afterimages is provided.

In the following description, the first conductive type and the second conductive type are terms used to distinguish the conductive type, and when the first conductive type is n type, the second conductive type is p type. Yes, conversely, when the first conductive type is p type, the second conductive type is n type.

FIG. 1 schematically shows a cross-sectional structure of an image pickup apparatus 100 according to an embodiment of the present invention. The image pickup device 100 is a solid-state image pickup device having a semiconductor substrate SS including a first semiconductor region 101 and a second semiconductor region 102 arranged on the first semiconductor region 101. Of the two surfaces of the second semiconductor region 102, the surface opposite to the first semiconductor region 101 constitutes the surface of the semiconductor substrate SS. The back surface of the semiconductor substrate SS may be composed of the first semiconductor region 101. The second semiconductor region 102 is continuous with the first semiconductor region 101. That is, there is no insulator region between the first semiconductor region 101 and the second semiconductor region 102. In this example, both the first semiconductor region 101 and the second semiconductor region 102 have a first conductive type. That is, in this example, the first semiconductor region 101 and the second semiconductor region 102 have the same conductive type. The first semiconductor region 101 and the second semiconductor region 102 may have different conductive types. As will be described later, a plurality of impurity regions having different conductive types and impurity concentrations are provided in the second semiconductor region 102.

The concentration of the first conductive type impurities in the first semiconductor region 101 is different from the concentration of the first conductive type impurities in the second semiconductor region 102. In one example, the concentration of the first conductive type impurities in the first semiconductor region 101 is larger than the concentration of the first conductive type impurities in the second semiconductor region 102. In another example, the concentration of the first conductive type impurities in the first semiconductor region 101 is smaller than the concentration of the first conductive type impurities in the second semiconductor region 102.

The first semiconductor region 101 is made of single crystal silicon and can be formed by slicing and polishing an ingod of single crystal silicon. The second semiconductor region 102 is made of single crystal silicon, and can be formed by forming a single crystal silicon layer on the first semiconductor region 101 by an epitaxial growth method. The layer formed by the epitaxial growth method is called an epitaxial layer. Since the crystal lattice can be continuous between the first semiconductor region 101 and the second semiconductor region 102, it may not be possible to observe a clear interface.

A photoelectric conversion element PD is arranged on the semiconductor substrate SS of the image pickup apparatus 100. The photoelectric conversion element PD is arranged at least in the first semiconductor region 101. In this example, the photoelectric conversion element PD is arranged in the first semiconductor region 101, but the photoelectric conversion element can be extended to the second semiconductor region 102. The photoelectric conversion element PD has a first conductive type impurity region 104 that can function as a charge storage region. In the first conductive type impurity region 104, a large number of signal charges form carriers. Further, the photoelectric conversion element PD may include an impurity region 103 having a second conductive type different from the first conductive type between the impurity region 104 and the first semiconductor region 101. Further, the photoelectric conversion element PD may include a first conductive type impurity region 102b continuously arranged in the impurity region 104 under the impurity region 104. The portion of the second semiconductor region 102 arranged below the impurity region 103 is the impurity region 102a, and the portion of the second semiconductor region 102 arranged above the impurity region 103 is the impurity region 102b. be.

The impurity concentration of the first conductive type in the impurity region 104 is higher than the impurity concentration in the second semiconductor region 102 (impurity region 102a, impurity region 102b). The impurity region 104, the impurity region 102b, and the impurity region 103 constitute the photoelectric conversion element PD. Of the negative charges (electrons) and positive charges (holes) generated by photoelectric conversion in the photoelectric conversion element PD, charges of the same type as the majority carriers in the first conductive type are accumulated in the impurity region 104. The photoelectric conversion element PD may include an impurity region 105 that is arranged above the impurity region 104, that is, between the impurity region 104 and the surface of the semiconductor substrate SS and has a second conductive type. The impurity region 105 functions to separate the impurity region 104 from the surface of the semiconductor substrate SS, thereby forming a photoelectric conversion element PD having an embedded photodiode structure.

Although not shown, the imaging device 100 has a plurality of impurity regions 104. The plurality of impurity regions 104 can be separated from each other by the second conductive type impurity regions 106 and 107 that function as separation regions due to a potential barrier. The impurity region 103 may be arranged below the sequence of the plurality of impurity regions 104 so as to extend over the entire region of the sequence.

The image pickup apparatus 100 may be configured as a MOS image sensor, a CCD image sensor, or another type of image sensor. Hereinafter, an example in which the image pickup apparatus 100 is configured as a MOS image sensor will be described.

The electric charge accumulated in the impurity region 104 is a first conductive type that functions as a floating diffusion region via a channel formed in the impurity region 102b by applying an active level potential to the gate electrode 114 (transfer gate). Is transferred to the impurity region 112 of. The impurity region 112 is formed between the impurity region 102b and the surface of the semiconductor substrate SS in the second semiconductor region 102. The gate electrode 114 is arranged on the semiconductor substrate SS via the gate insulating film 116. The impurity region 104, the impurity region 112, the gate electrode 114, and the gate insulating film 116 have a MOS transistor structure. On the side of the impurity region 104 of the impurity region 112, an impurity region 111 that functions as an electric field relaxation region may be arranged so as to be adjacent to the impurity region 112. The impurity region 111 may have a first conductive type.

The image pickup apparatus 100 may include a plurality of transistors Tr in order to output a signal corresponding to the electric charge transferred to the impurity region 112 to the column signal line. The plurality of transistors Tr are arranged on the surface side of the semiconductor substrate SS. The transistor Tr may include an impurity region 113 constituting a source and a drain, a gate electrode 115, and a gate insulating film 117. The element to be separated from each other among the elements including the plurality of transistors Tr and the impurity region 104 (photoelectric conversion element) can be separated by the element separation unit 110. The element separation unit 110 may be formed of an insulator having an STI structure or a LOCOS structure formed on the surface side of the semiconductor substrate SS, but may also be formed by PN junction separation. The second conductive type impurity region 109 is formed around the element separating portion 110. The impurity region 109 can function as a channel stop or a shield against a dark current generated at the interface between the element separation unit 110 and the first semiconductor region 102. An impurity region 108 having a second conductive type may be arranged between the impurity region 109 and the impurity region 103.

An insulating layer 118, a plurality of insulating layers 123, wiring layers 120 and 122, a contact plug 119, a via plug 121, and the like may be arranged on the semiconductor substrate SS. The insulating layer 118 can function, for example, as an antireflection film and / or an etching stopper. The plurality of insulating layers 123 can function as an interlayer insulating film. A color filter layer 124, a microlens 125, and the like may be arranged on the plurality of insulating layers 123.

Hereinafter, a method for manufacturing the image pickup apparatus 100 will be exemplified by way of referring to FIGS. 2 to 5. First, in step S200 shown in FIG. 2, a preparatory step for preparing the semiconductor substrate SS is carried out. The semiconductor substrate SS includes a first semiconductor region 101 having a first conductive type and a second semiconductor region 102 arranged on the first semiconductor region 101 and having a first conductive type. The first semiconductor region 101 may be, for example, a single crystal silicon substrate. In a more specific example, the first semiconductor region 101 is obtained by mirror-polishing the main surface of a disk member cut out from a single crystal silicon ingot having a diameter of 300 mm, which has been pulled up by a magnetic field application CZ method (MCZ method). It can be a single crystal silicon wafer.

The preparatory step carried out in step S200 may include a step of preparing the first semiconductor region 101 and a step of forming the second semiconductor region 102 on the first semiconductor region 101. The second semiconductor region 102 can typically be formed on top of the first semiconductor region 101 by an epitaxial growth method. For example, each of the first semiconductor region 101 and the second semiconductor region 102 shows an n-type by containing phosphorus of about ^{1 × 10 14 to} 5 × 10 ¹⁴ atoms / cm ^{3 as an impurity.}

The oxygen concentration in the first semiconductor region 101 can be in the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less, for example, 1 × 10 ¹⁷ atoms / cm ³ . When the oxygen concentration falls within this range, the minimum value C10min of the oxygen concentration in the first semiconductor region 101 is 2 × 10 ¹⁶ atoms / cm ³ or more, and the maximum value C10max of the oxygen concentration in the first semiconductor region 101 is 4. It means that it is × 10 ¹⁷ atoms / cm ^{3 or less.} This oxygen concentration can be determined, for example, from a conversion factor by Old ASTM. There are no restrictions on the dimensions, resistivity, or conductivity of the first semiconductor region 101. The oxygen concentration in the second semiconductor region 102 is lower than the oxygen concentration in the first semiconductor region 101. For example, the minimum value C20min of the oxygen concentration in the second semiconductor region 102 is smaller than the maximum value C10max of the oxygen concentration in the first semiconductor region 101 (C20min <C10max). Further, the minimum value C20min of the oxygen concentration in the second semiconductor region 102 is smaller than the minimum value C10min of the oxygen concentration in the first semiconductor region 101 (C20min <C10min). Further, for example, the maximum oxygen concentration C20max in the second semiconductor region 102 is smaller than the maximum oxygen concentration C10max in the first semiconductor region 101. Further, the maximum oxygen concentration C20max in the second semiconductor region 102 is smaller than the minimum oxygen concentration C10min in the first semiconductor region 101. The second semiconductor region 102 has the same conductive type as the first semiconductor region 101, and may have a thickness in the range of 5 μm or more and 50 μm or less, more preferably 5 μm or more and 25 μm or less.

The second semiconductor region 102 may be formed so that the concentration of the first conductive type impurities in the first semiconductor region 101 is different from the concentration of the first conductive type impurities in the second semiconductor region 102. In one example, the second semiconductor region 102 may be formed so that the concentration of the first conductive type impurities in the first semiconductor region 101 is higher than the concentration of the first conductive type impurities in the second semiconductor region 102. In another example, the second semiconductor region 102 may be formed so that the concentration of the first conductive type impurities in the first semiconductor region 101 is smaller than the concentration of the first conductive type impurities in the second semiconductor region 102.

In FIG. 6, the distribution of oxygen concentration in the depth direction of the semiconductor substrate SS is illustrated by a solid line. The horizontal axis shows the depth from the surface of the semiconductor substrate SS, and the vertical axis shows the oxygen concentration (atmos / cm ³ ). Here, the solid line (embodiment) in FIG. 6 is a semiconductor substrate SS obtained by forming a second semiconductor region 102 on a first semiconductor region 101 ^{having an oxygen concentration of 1 × 10 17} atoms / cm ^3. It shows the distribution of oxygen concentration. A comparative example shown by a dotted line in FIG. 6 is a semiconductor substrate obtained by forming a second semiconductor region 102 on a first semiconductor region 101 ^{having an oxygen concentration of 1.3 × 10 18} atoms / cm ^3. It shows the distribution of oxygen concentration. In both the embodiment and the comparative example of FIG. 6, the thickness of the second semiconductor region 102, which is the single crystal silicon layer formed by epitaxial growth, is 9 μm. Therefore, the position where the depth from the surface of the semiconductor substrate is 9 μm corresponds to the boundary between the first semiconductor region 101 and the second semiconductor region 102. In both the embodiment shown by the solid line and the comparative example shown by the dotted line, in the portion (depth 0 to 4.5 μm) of the second semiconductor region 102 from the surface side to half the depth of the semiconductor substrate. The oxygen concentration is 1 × 10 ¹⁶ atoms / cm ³ or less. ^{In the embodiment, the oxygen concentration is 1 × 10 16} atoms / cm ³ or less even in the remaining portion (depth 4.5 to 9 μm) of the second semiconductor region 102. In the comparative example, in the remaining portion (depth 4.5 to 9 μm) of the second semiconductor region 102, the oxygen concentration is 1 × 10 ¹⁶ atoms / cm ^{3 due to the diffusion of oxygen from the first semiconductor region 101.} Over.

Next, in steps S210 and S220 shown in FIG. 2 and S230 shown in FIG. 3, a trench forming step of forming a trench TR on the semiconductor substrate SS is performed. First, in step S210, a step of forming the film 150 on the semiconductor substrate SS is performed. The film 150 may include, for example, a silicon oxide layer 151, a polysilicon layer 152 arranged on the silicon oxide layer 151, and a silicon nitride layer 153 arranged on the polysilicon layer 152. Following step S210, in step S220, a step of patterning the film 150 by a photolithography step to form the opening OP1 is performed. Following step S220, in step S230, a step of etching the semiconductor substrate SS (second semiconductor region 102) through the opening OP1 using the patterned film 150 as an etching mask is performed. By this step, a trench TR is formed in the semiconductor substrate SS (second semiconductor region 102).

Then, in step S240 shown in FIG. 3, it is possible to heat treatment of the semiconductor substrate SS in an atmosphere containing oxygen, oxygen is supplied to the inner surface of the trench TR to the deep portion of the second semiconductor region 102. This heat treatment involves oxidation of the inner surface of the trench TR, and as a result, a silicon oxide film 170 may be formed on the inner surface of the trench TR. The heat treatment in step S240 can be carried out, for example, at a temperature of 800 ° C. or higher and 1150 ° C. or lower. Further, the heat treatment in step S240 can be carried out, for example, so that the oxygen concentration in the second semiconductor region 102 is in the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ^{3 or less.} Further, the heat treatment in step S240 can be carried out, for example, so that the oxygen concentration in the second semiconductor region 102 is ^{within the range of 1 × 10 16} atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ^{3 or less.}

Here, the solid solution limit concentration of oxygen in silicon at a temperature of 800 ° C. or higher and 1150 ° C. or lower is in the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less. Therefore, it is preferable that the oxygen concentration of the first semiconductor region 101 for obtaining the semiconductor substrate SS is set within the range of the solid solution limit concentration, and the heat treatment in step S240 is performed in an atmosphere containing oxygen. According to such a method, it is easy to obtain a semiconductor substrate SS having a substantially constant oxygen concentration distribution in the depth direction.

By performing the heat treatment in step S240 in the entire depth direction of the second semiconductor region 102, the oxygen concentration of the second semiconductor region 102 is in the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less. Can be inside. Further, the oxygen concentration of the second semiconductor region 102 in the entire depth direction of the second semiconductor region 102 can be within the range of ^{1 × 10 16} atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ^{3 or less.} .. Further, for example, when the maximum value and the minimum value of the oxygen concentration in the second semiconductor region 102 after step S240 are C21max and C21min, respectively, it is preferable that C21max / C21min is 10 or less. More preferably, C21max / C21min is 5 or less.

In FIG. 7, the distribution of the oxygen concentration in the depth direction of the semiconductor substrate SS after the heat treatment is performed in the oxygen-containing atmosphere in step S240 is illustrated by a solid line. Here, the result shown in FIG. 7 is the result of setting the temperature of the heat treatment step in step S240 to 1050 ° C.

In the heat treatment in step S240, the semiconductor substrate SS can be rapidly cooled by forcibly cooling the semiconductor substrate SS after heating the semiconductor substrate SS. In this cooling, the temperature of the semiconductor substrate SS is, for example, a temperature drop rate of 0.1 ° C./sec or more, preferably a temperature drop rate of 1 ° C./sec or more, and more preferably a temperature drop rate of 10 ° C./sec or more. Can be descended. The temperature drop rate can be 100 ° C./sec or less. By cooling rapidly in this way, the diffusion of unnecessary oxygen can be suppressed.

Next, in step S250 shown in FIG. 3, an injection step for forming the second conductive type impurity region 109 is carried out. By forming the impurity region 109 along the inner surface of the trench TR, the dark current generated in the vicinity of the inner surface of the trench TR can be reduced. The heat treatment in step S240 can be performed after the formation of the impurity region 109, but by performing the formation of the impurity region 109 after the heat treatment heat in step S240, unnecessary diffusion of the impurity region 109 can be suppressed. Next, in step S260 shown in FIG. 4, a filling step of filling the trench TR with the insulator 160 (silicon oxide) is performed. At this time, the insulator 160 may also be deposited on the film 150. In FIG. 4, the silicon oxide film 170 is shown integrally with the insulator 160. Next, in step S270 shown in FIG. 4, a removing step of removing the insulator 160 on the film 150 by CMP or the like is performed. As a result, the element separation portion 110 is formed in the trench TR. After that, the film 150 is removed. The heat treatment in the oxygen atmosphere of step S240 can also be performed after the embedding of the insulator 160 in step S260. However, by performing the heat treatment in an oxygen atmosphere before embedding the insulator 160, oxygen can be supplied from the inner surface of the trench TR to the deep part of the second semiconductor region 102.

Next, in step S280 shown in FIG. 4, the second conductive type impurity regions 103 and the second conductive type impurity regions 106 and 107 are formed. The resist pattern for forming the second conductive type impurity region 103 and the second conductive type impurity region 106, 107 is omitted. Then, in order to diffuse or activate the formed second conductive type impurity regions 103, 106, 107, a heat treatment step is performed in an oxygen-free atmosphere. Then, in step 280, the gate insulating films 116, 117 and the gate electrodes 114, 115 are formed on the semiconductor substrate SS.

In FIG. 8, the distribution of oxygen concentration in the depth direction of the semiconductor substrate SS after step S280 is illustrated by a solid line. In the state of FIG. 8, the above-mentioned heat treatment step in an oxygen-free atmosphere and the heat treatment step in an oxygen-containing atmosphere for forming the gate insulating films 116 and 117 are performed. When the heat treatment step is performed in an oxygen-free atmosphere, oxygen in the region near the surface of the semiconductor substrate SS is desorbed by outward diffusion. Therefore, the oxygen concentration in the region near the surface of the semiconductor substrate SS is lower than that immediately after the heat treatment step of step S240 (FIG. 7). From the results shown in FIG. 8, it is understood that the gradient of oxygen concentration can be suppressed within the permissible value even by the heat treatment (heat treatment for activating the injected impurities, film formation treatment) that can be performed after step S240. be able to. In the entire depth direction of the second semiconductor region 102, even after step S280, the oxygen concentration of the second semiconductor region 102 is within the range ^{of 2 × 10 16} atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ^{3 or less.} Can be maintained. Further, the oxygen concentration of the second semiconductor region 102 can be maintained within the range of ^{1 × 10 16} atoms / cm ³ or more and 1 × 10 ¹⁷ atoms / cm ^{3 or less in the entire depth direction of the second semiconductor region 102.} can. Further, for example, even after step S280, when the maximum value and the minimum value of the oxygen concentration in the second semiconductor region 102 are C22max and C22min, respectively, it is preferable that C22max / C22min is 10 or less. More preferably, C22max / C22min is 5 or less.

Next, in step S290, the resist pattern RP2 is formed on the semiconductor substrate SS, and the first conductive type impurities are injected into the semiconductor substrate SS (second semiconductor region 102) through the opening OP2 of the resist pattern RP2, whereby the impurity region is formed. 104 is formed. After that, the resist pattern RP2 is removed.

Next, in step S300, the resist pattern RP3 is formed on the semiconductor substrate SS, and the second conductive type impurities are injected into the semiconductor substrate SS through the opening OP3 of the resist pattern RP3. As a result, the second conductive type impurity region 105 is formed on the impurity region 104. In this way, the photoelectric conversion element PD is formed in steps S200 to S300.

Next, in step S310, the insulating layer 118 is formed so as to cover the surface of the semiconductor substrate SS and the gate electrodes 114 and 115. After that, a plurality of insulating layers 123, wiring layers 120 and 122, a contact plug 119, a via plug 121 and the like are formed, and further, a color filter layer 124 and a microlens 125 and the like are formed. As a result, the image pickup apparatus 100 is completed as illustrated in FIG.

In FIG. 9, the distribution of oxygen concentration in the semiconductor substrate SS of the image pickup apparatus 100 manufactured according to this embodiment is illustrated by a solid line. A comparative example is also shown in FIG. In the comparative example, the oxygen concentration at a depth of about 10 μm from the surface of the semiconductor substrate SS is 7 × 10 ¹⁷ atoms / cm ^3, which is about 10 times the oxygen concentration near the surface of 7 × 10 ¹⁶ atoms / cm ^3. Yes, the concentration gradient is extremely large. On the other hand, in this embodiment, the oxygen concentration is 8 × 10 ¹⁶ atoms / cm ³ even at a depth of about 10 μm from the surface of the semiconductor substrate SS, and the oxygen concentration near the surface is 5 × 10 ¹⁶ atoms / cm. The concentration is about 1.6 times that of ^3. That is, in this embodiment, a state in which the gradient of oxygen concentration is low is achieved. When the gradient of the concentration of oxygen is low, it is possible to suppress the generation of afterimages due to the variation in the manufacturing process. As the variation in the manufacturing process, for example, the ingot for cutting out the first semiconductor region 101 or the variation in the oxygen concentration in the first semiconductor region 101 can be mentioned. Other variations in the manufacturing process include, for example, heat treatment for injecting impurities into the semiconductor substrate SS and then activating the impurities, or temperature variations in the film forming process.

In the image pickup apparatus 100, when the maximum value and the minimum value of the oxygen concentration in the depth portion having a large influence on the afterimage on the semiconductor substrate SS are Cmax and Cmin, respectively, Cmax / Cmin is preferably 10 or less. For example, in the image pickup apparatus 100, Cmax / Cmin is 10 or less when the maximum and minimum values of the oxygen concentration in the semiconductor region in the portion where the distance from the surface of the semiconductor substrate SS is within 20 μm are Cmax and Cmin, respectively. Is preferable. Alternatively, in the image pickup apparatus 100, Cmax / Cmin is 10 or less when the maximum and minimum values of the oxygen concentration in the semiconductor region in the portion where the distance from the surface of the semiconductor substrate SS is within 30 μm are Cmax and Cmin, respectively. Is preferable. Alternatively, in the image pickup apparatus 100, Cmax / Cmin is 10 or less when the maximum and minimum values of the oxygen concentration in the semiconductor region in the portion where the distance from the surface of the semiconductor substrate SS is within 40 μm are Cmax and Cmin, respectively. Is preferable. Alternatively, in the image pickup apparatus 100, Cmax / Cmin is 10 or less when the maximum and minimum values of the oxygen concentration in the semiconductor region in the portion where the distance from the surface of the semiconductor substrate SS is within 50 μm are Cmax and Cmin, respectively. Is preferable. Cmax / Cmin is preferably 5 or less in each depth portion.

When the maximum and minimum values of oxygen concentration in the portion where the depth from the surface of the semiconductor substrate SS is within 10 μm are Cmax and Cmin, respectively, the values of Cmax / Cmin are the embodiments shown in FIG. Is 1.6, and in the comparative example shown in FIG. 9, it is about 10. That is, it is estimated that the value of Cmax / Cmin of the comparative example shown in FIG. 9 is considerably larger than the value of Cmax / Cmin of the embodiment shown in FIG. 9, and the occurrence of afterimages is large.

Hereinafter, as an application example of the image pickup apparatus according to each of the above embodiments, a camera in which the image pickup apparatus is incorporated will be exemplified. The concept of a camera includes not only a device whose main purpose is shooting but also a device having an auxiliary shooting function (for example, a personal computer or a mobile terminal). The camera includes an imaging device according to the present invention exemplified as the above embodiment, and a processing unit that processes a signal output from the imaging device. The processing unit may include, for example, an A / D converter and a processor that processes digital data output from the A / D converter.

Although the surface-illuminated CMOS image sensor is exemplified as the image pickup apparatus in the above-described embodiment, it can be applied to the back-illuminated type and also to the CCD image sensor. In the back-illuminated image pickup apparatus, the thickness of the semiconductor region made of single crystal silicon having a photoelectric conversion unit is about 1 to 10 μm. The maximum value of the oxygen concentration in the semiconductor region may be 10 times or less the minimum value in the entire depth direction from the front surface to the back surface of the semiconductor region. The oxygen concentration in the semiconductor region may be within the range of ^{2 × 10 16} atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less in the entire depth direction from the front surface to the back surface of the semiconductor region. In the range from the front surface of the semiconductor region to 20 μm, in the portion farther from the front surface than the back surface of the semiconductor region, there is no semiconductor region that causes afterimages due to oxygen, and microlenses and color filters are present. sell.

Hereinafter, other aspects of the present invention will be described with reference to the accompanying drawings through a second embodiment, which is an exemplary embodiment thereof.

The image pickup apparatus is arranged on a substrate made of a semiconductor such as silicon, and each has a plurality of pixels including a photoelectric conversion unit, and an image is formed in each pixel based on the electric charge generated by the photoelectric conversion. Will be done.

The imaging device is required to suppress or reduce afterimages and white scratches that may occur in the image. Afterimages are generated, for example, because the electric charge generated by photoelectric conversion is trapped by a defect in the substrate when reading a certain image, and the electric charge is released when reading another image thereafter. sell. White scratches can occur during the manufacture of the imaging apparatus, for example, due to metal impurities mixed in the substrate during the step of silicidizing the electrodes of the transistor with nickel or cobalt.

Japanese Unexamined Patent Publication No. 2007-251074 discloses that the afterimage in an image is suppressed by lowering the oxygen concentration in the substrate. On the other hand, Japanese Patent Application Laid-Open No. 2003-92301 discloses that white scratches in an image are suppressed by increasing the oxygen concentration in the substrate. That is, according to Japanese Patent Application Laid-Open No. 2007-251074 and Japanese Patent Application Laid-Open No. 2003-92301, in order to achieve both suppression of afterimages and suppression of white scratches, the substrate is required to have mutually contradictory configurations. Therefore, it can be said that it is difficult to achieve both of these by simply adjusting the oxygen concentration in the substrate.

An object of the present embodiment is to provide a novel technique for suppressing both afterimages and white scratches in an image.

One side surface of the present embodiment is attached to an image pickup device, and the image pickup device is arranged around a pixel portion in which a plurality of pixels are arranged on a substrate made of silicon and the pixel portion on the substrate. It has a peripheral circuit unit, which is a peripheral circuit unit and includes a circuit that processes a signal from each pixel.
Here, the peripheral circuit portion has a transistor having a silicide region containing at least one of nickel and cobalt.
Further, each pixel is formed on the substrate and is formed on the substrate.
The first region of the first conductive type including the portion that accumulates the electric charge generated by the photoelectric conversion, and
A second region of the first conductive type arranged at a position deeper than the first region of the substrate and away from the first region, and
It has a second conductive type third region arranged between the first region and the second region in the depth direction from the surface of the substrate.
In addition, the third region is
A first portion, which is arranged at a position away from the second region in the depth direction and includes a position where the net impurity concentration of the second conductive type shows a first maximum value, and
A second position that is arranged between the first portion and the second region in the depth direction and has a second maximum value at which the net impurity concentration of the second conductive type is lower than the first maximum value. Includes two parts.
The oxygen concentration of the second portion is 1 × 10 ¹⁷ [atoms / cm ³ ] or less.

According to this embodiment, both afterimages and white scratches in the image can be suppressed.
(1-1. Structure of imaging device)
FIG. 10 is a schematic diagram for explaining an example of the structure of the image pickup apparatus 100 according to the second embodiment. The image pickup apparatus 100 includes regions R1 to R4 and the like formed on a substrate SUB made of silicon, respectively. The region R1 (first region) is, for example, N type (first conductive type), and is hereinafter referred to as “N type region R1” in the present specification. The region R2 (second region) is, for example, N-type, and is hereinafter referred to as “N-type region R2”. The region R3 (third region) is, for example, P-type (second conductive type), and is hereinafter referred to as “P-type region R3”. Further, the region R4 is, for example, N-type, and is hereinafter referred to as “N-type region R4”.

Each of the above regions R1 to R4 may be formed by using a known semiconductor manufacturing technique such as epitaxial growth or impurity injection. Specifically, first, a silicon substrate corresponding to the N-type region R4 is prepared, and an N-type semiconductor member is formed on the silicon substrate by, for example, epitaxial growth. Next, the N-type region R1 is formed by injecting impurities into the formed semiconductor member, and the P-type region R3 is formed at a position deeper than the N-type region R1 before or after the formation of the N-type region R1. The N-type region R2 is a region between the P-type region R3 and the N-type region R4, and is therefore arranged at a position deeper than the N-type region R1 and away from the N-type region R1.

The N-type region R1 is a charge storage portion (not shown) in which charges (electrons in this example) generated by photoelectric conversion are accumulated, and has a higher impurity concentration (for example, 1 × 10 ^{17) than other portions.} It includes a charge storage unit having [cm ^{-3] or more).} The N-type region R1 may be formed at a position away from the surface of the substrate SUB (so as to be embedded) by forming the P-type region R0 near the surface of the substrate SUB.

The P-type region R3 is a region formed between the N-type region R1 and the N-type region R2 so as to come into contact with the bottom surface and the side surface of the N-type region R1. That is, a PN junction is formed between the N-type region R1 and the P-type region R3, and a photodiode is formed. In other words, the P-type region R3 is formed so as to be adjacent to the N-type region R1 from a position deeper than the N-type region R1 or shallower than the N-type region R1 to a position deeper than the N-type region R1 and shallower than the N-type region R2. ..

In each of the above-mentioned regions, for example, boron (B) or the like is used as the impurity for forming the P type (P type impurity), and the impurity for forming the N type (N type impurity) is used as the impurity (N type impurity). For example, phosphorus (P), arsenic (As) and the like may be used. Further, in the figure, the maximum value Q_R1 of the N-type impurity concentration in the N-type region R1 and the maximum value Q1 to Q5 of the P-type impurity concentration in the P-type region R3 are shown. It will be described later.

The image pickup apparatus 100 further includes a floating diffusion FD and a gate electrode GTX. The floating diffusion FD is an N-type region formed on the surface of the substrate SUB, in the vicinity thereof, and at a position away from the N-type region R1. The gate electrode GTX is a gate electrode of a MOS transistor (transfer transistor) that connects the N-type region R1 and the floating diffusion FD, and is formed on the substrate SUB via an insulating film F. The electric charge generated by the photoelectric conversion and accumulated in the N-type region R1 is transferred to the floating diffusion FD via the channel formed by supplying the activation voltage to the gate electrode GTX. The transferred charge or the corresponding signal is read out as a pixel signal by a reading circuit (not shown).

Further, the image pickup apparatus 100 further includes an element separation portion STI having an STI (Shallow Training Isolation) structure formed near the surface of the substrate SUB, and a P-type impurity region CS for channel stop formed around the element separation portion STI. .. The element separation unit STI electrically separates the elements or units formed on the substrate SUB from each other.

Although description is omitted here, conductive members (wiring patterns) arranged in one or more wiring layers, plugs connecting them, and optical elements (for example, color filters, microlenses, etc.) are placed on the substrate SUB. The including structure can be arranged.

FIG. 11 shows the actual concentration distribution of impurities (boron and arsenic) at the cut lines A1-A2 (in the depth direction from the surface of the substrate SUB) in FIG. Here, only the impurity concentration of the portion necessary for the explanation of this example is shown, and the impurity concentration distribution of the other portion (for example, region R0 etc.) is not shown.

Here, the "actual" impurity concentration in a certain region is the impurity concentration actually present in the region regardless of the conductive type of the region, and is also called a gross impurity concentration. On the other hand, the "net" impurity concentration in a region is an effective impurity concentration that determines the conductive type in that region, and is also called a net impurity concentration. That is, the net impurity concentration corresponds to the actual impurity concentration of one conductive type minus the actual impurity concentration of the other conductive type different from the conductive type. For example, when the actual boron (P-type impurity) concentration in a certain region is 4 × 10 ¹⁶ [cm ^-3 ] and the actual arsenic (N-type impurity) concentration is 1 × 10 ¹⁶ [cm ^-3 ], the region The conductive type is P-type, and the net P-type impurity concentration in the region is 3 × 10 ¹⁶ [cm ^-3 ].

Although the actual impurity concentration is shown in FIG. 11, the P-type impurity concentration in the N-type region R1 is sufficiently lower than the N-type impurity concentration in the N-type region R1 and is in the P-type region R2. The N-type impurity concentration is sufficiently lower than the P-type impurity concentration in the P-type region R2. Therefore, the net impurity concentration distribution corresponding to FIG. 11 is substantially the same as the impurity distribution of FIG.

In FIG. 11, the concentration of N-type impurities (arsenic) in the N-type region R1 is shown by a alternate long and short dash line, and the concentration of P-type impurities (boron) in the P-type region R3 is shown by a solid line (note that in the substrate SUB). The oxygen concentration of is shown by a broken line, but the details of this will be described later.) The position where the N-type impurity concentration shows the maximum value C_R1 in the N-type region R1 is defined as the peak position Q_R1. The electric charge generated by the above-mentioned photoelectric conversion is mainly the peak position Q_R1 in the N-type region R1 and the portion in the vicinity thereof (for example, 1 × 10 ¹⁶ [cm ^-3 ] or more, particularly 1 × 10 ¹⁷ [cm ^-3 ]]. It can be accumulated in the above part). The peak position Q_R1 has a depth (depth from the surface of the substrate SUB) of about 0.3 [μm], and its net N-type impurity concentration is about 1.23 × 10 ¹⁷ [cm ^-3 ]. For the portion of the N-type region R1 other than the charge storage portion, the net N-type impurity concentration may be ^{less than 1 × 10 17} [cm ^-3 ], for example, 1 × 10 ¹⁴ to 1 × 10 ¹⁶ [cm ^-3 ]. It may be about.

The P-type region R3 has a plurality of portions P0 to P5, for example, in the depth direction from the surface of the substrate SUB. In this example, the portion P0 is a portion surrounding the region R1. The portions P1 to P5 each include positions Q1 to Q5 in which the P-type impurity concentration indicates a maximum value C1 to C5, respectively. In the figure, the peak positions Q1, Q2, Q3, Q4, and Q5 showing the maximum P-type impurity concentrations C1, C2, C3, C4, and C5 are shown for the portions P1, P2, P3, P4, and P5, respectively (P1). ~ P5 and Q1 to Q5 are also shown in FIG. 10). The boundary between the portions P0 to P5 is a position where the impurity concentration in the distribution of the net P-type impurity concentration shows a minimum value. This structure is obtained, for example, by injecting a plurality of impurities with different injection energies, and according to this method, the P-type region R3 is adjusted so that the impurity concentration distribution becomes a desired concentration. It can be formed to the desired depth.

In the P-type region R3, the net P-type impurity concentration for the deepest portion P5 of the portions P1 to P5 may be higher than the net P-type impurity concentration for the portions P1 to P4 other than the portion P5. For example, the maximum value C5 of the net P-type impurity concentration for the portion P5 may be three times or more higher than the maximum value C1 to C4 of the net P-type impurity concentration for the parts P1 to P4, and further five times or more. good. According to this structure, it is possible to prevent the electric charge generated in the P-type region R3 by photoelectric conversion (specifically, the electric charge leaks in a direction deeper than the P-type region R3), and the electric charge can be efficiently distributed. Can lead to the N-type region R1.

For example, the peak position Q1 in the partial P1 is about 0.7 [μm] in depth, and the maximum value C1 of the net P-type impurity concentration is about 2.0 × 10 ¹⁷ [cm ^-3 ]. The peak position Q2 in the portion P2 has a depth of about 1.2 [μm], and the maximum value C2 of the net P-type impurity concentration is about 1.7 × 10 ¹⁷ [cm ^-3 ]. The peak position Q3 in the portion P3 has a depth of about 1.6 [μm], and the maximum value C3 of the net P-type impurity concentration is about 1.0 × 10 ¹⁷ [cm ^-3 ]. The peak position Q4 in the portion P4 has a depth of about 2.0 [μm], and the maximum value C4 of the net P-type impurity concentration is about 0.9 × 10 ¹⁷ [cm ^-3 ]. The peak position Q5 in the partial P5 is about 3.2 [μm] in depth, and the maximum value C5 of the net P-type impurity concentration is about 4.0 × 10 ¹⁷ [cm ^-3 ]. The maximum value C1 to C4 of the net P-type impurity concentration in the portions P1 to P4 becomes smaller as it is arranged at a deeper position (C1>C2>C3> C4). These depths may be determined based on the penetration depth of incident light (for example, red light) from the surface of the substrate SUB.

(1-2. White scratches that may occur on the image)
In the manufacturing process of the image pickup apparatus 100, metal impurities (nickel, cobalt, etc.) may be mixed in the substrate SUB by, for example, silicide treatment, and these metal impurities may cause white scratches in the image. .. Focusing on this, the inventor of the present invention conducted an experiment using a plurality of substrate SUBs having different configurations, and studied diligently. Among them, the inventor conducted an experiment using a plurality of substrate SUBs having different P-type impurity concentration distributions in the P-type region R3, and found that the degree of white scratches was depletion between the N-type region R1-P-type region R3. We found that it depends on the width (volume) of the layer. Specifically, the inventor has found that as the number of metal impurities in the depletion layer between the N-type region R1-P-type region R3 increases, white scratches in the image tend to increase. It is considered that this is because the metal impurities in the depletion layer have some influence on the accumulated charge of the N-type region R1 by the depletion layer electric field or through the electric field.

Therefore, in this structure, white scratches were suppressed by reducing the depletion layer width between the N-type region R1-P-type region R3. Specifically, the maximum values C1 and C2 of the net P-type impurity concentration of the parts P1 and P2 on the N-type region R1 side of the P-type region R3 are set to the parts P3 and P4 on the N-type region R2 side of the P-type region R3. The net P-type impurity concentration was higher than the maximum values C3 and C4. Thereby, the depletion layer can be prevented from reaching the deep position of the P-type region R3. Further, the net P-type impurity concentration in the portion of the P-type region R3 on the N-type region R1 side may be higher than the net N-type impurity concentration in the charge storage portion of the N-type region R1. Specifically, as illustrated in FIG. 11, the net P-type impurity concentration at the peak position Q1 in the portion P1 of the P-type region R3 is calculated from the net N-type impurity concentration at the peak position Q_R1 in the N-type region R1. Should also be high. According to this structure, for example, while the image pickup apparatus 100 is in the charge storage mode (operation mode for accumulating charges in the N-type region R1), the depletion layer between the N-type region R1-P-type region R3 is more than the partial P1. It is possible to prevent the deep portions P2 to P5 from being reached.

In summary, the P-type region R3 may be configured so that the depletion layer width between the N-type region R1-P-type region R3 becomes small. In this example, the P-type region R3 is configured such that the net P-type impurity concentration of a part thereof is higher than the net P-type impurity concentration of a part of the other part deeper than the part. , The depletion layer is prevented from reaching the other part. Further, the net P-type impurity concentration of a part of the P-type region R3 may be higher than the net N-type impurity concentration at the peak position Q_R1 of the N-type region R1. Preferably, the net P-type impurity concentration of the portion P1 of the portions P1 to P5 of the P-type region R3 closest to the N-type region R1 is set to be higher than the net N-type impurity concentration at the peak position Q_R1 of the N-type region R1. You can make it higher.

Further, in this example, the maximum value C2 to C4 of the net P-type impurity concentration of the portions P2 to P4 between the parts P1 and P5 is lower than the maximum value C1 of the net P-type impurity concentration of the part P1. It is preferable to do so. Further, it is preferable that the maximum value C2 to C4 of the net P-type impurity concentration of the portions P2 to P4 is lower than the maximum value C5 of the net P-type impurity concentration of the portion P5. Furthermore, it is preferable that the net P-type impurity concentration of any one of the portions P2 to P4 is lower than the net N-type impurity concentration in the N-type region R1. In this example, the maximum value C3 and C4 of the net P-type impurity concentration of the portions P3 and P4 is smaller than the maximum value C_R1 of the net N-type impurity concentration at the peak position Q_R1 of the N-type region R1.

(1-3. Afterimages that can occur in images)
When the oxygen concentration in the substrate SUB becomes high, an oxygen complex (thermal donor) is likely to be formed in the substrate SUB. The thermal donor may trap the charge generated by the photoelectric conversion due to its energy level, which can cause an afterimage in the image. For example, the charge generated by photoelectric conversion when reading the first image can be trapped by the energy level of the thermal donor. If the trapped charge is then released when reading a second image that is different from the first image, the second image may have an afterimage due to this charge.

According to Japanese Patent Application Laid-Open No. 2007-251074, afterimages in the image are suppressed by lowering the oxygen concentration in the substrate. On the other hand, according to Japanese Patent Application Laid-Open No. 2003-92301, white scratches in the image are suppressed by increasing the oxygen concentration in the substrate.

Here, as described with reference to FIG. 11, by configuring the P-type region R3 so that the depletion layer width between the N-type region R1-P-type region R3 becomes small, white scratches can be suppressed. .. In this structure, what kind of range should the oxygen concentration in the substrate SUB be set in order to sufficiently suppress the afterimage, the inventor has determined that a plurality of substrate SUBs (0.7 × 10 ¹⁷ to 0.7) having different oxygen concentrations from each other. Experiments were carried out using 14 × 10 ¹⁷ [atoms / cm ³ ]), and diligent studies were conducted.

With reference to FIG. 11 again, FIG. 11 further shows the oxygen concentration distribution in the substrate SUB at the cut lines A1-A2 in FIG. As shown in FIG. 11, in this structure, the oxygen concentration in the substrate SUB was set to 1 × 10 ¹⁷ [atoms / cm ³ ] or less to suppress the afterimage.

Here, when the electric charge generated by the photoelectric conversion reaches the depletion layer between the N-type region R1 and the P-type region R3, it drifts toward the N-type region R1 due to the depletion layer electric field having a large electric field. In the P-type region R3, which is not particularly depleted, the electric field is smaller than the depletion layer electric field, so that the charge is easily trapped in the energy level of the thermal donor (as described above, this causes an afterimage in the image. Causes.). Therefore, it is preferable to prevent the formation of thermal donors in the non-depleted portion, and at least the oxygen concentration in the non-depleted portion should be 1 × 10 ¹⁷ [atoms / cm ³ ] or less. That is, the net P-type impurity concentration in the P-type region R3 is higher than the net N-type impurity concentration in the peak position Q_R1 of the N-type region R1 or deeper than the portion containing the N-type impurity concentration (part P1 in this example). The oxygen concentration up to the portion should be 1 × 10 ¹⁷ [atoms / cm ³ ] or less. Preferably, in the region including the entire P-type region R3 (the region from the N-type region R1 or a shallower position to the P-type region R3 or a deeper position), the oxygen concentration in the substrate SUB is 1 × 10 ¹⁷ [. Atoms / cm ³ ] or less. In the N-type region R2 located deeper than the P-type region R3, the oxygen concentration may be higher than the oxygen concentration in the P-type region R3, and may be, for example, 1 × 10 ¹⁷ [atoms / cm ³ ] or more. ..

For example, the oxygen concentration in the substrate SUB in a region from the surface of the substrate SUB to a depth of 15 [μm] from the surface (this region has a sufficient depth to include the P-type region R3). It should be 1 × 10 ¹⁷ [atoms / cm ³ ] or less. ^{In another example, the oxygen concentration in the substrate SUB may be 1 × 10 17} [atoms / cm ³ ] or less in a region from the surface of the substrate SUB to a depth of 10 [μm] from the surface. ^{Then, the oxygen concentration in the substrate SUB may be set to 2 × 10 17} [atoms / cm ³ ] or less in the region from the depth of 10 [μm] from the surface to the depth of 20 [μm] from the surface. .. In yet another example, in a portion of the region from a depth of 10 [μm] from the surface of the substrate to a depth of 20 [μm] from the surface, the oxygen concentration in the substrate SUB is 1 × 10 ¹⁷ [atoms]. / Cm ³ ] may be larger.

Further, it should be noted that the oxygen concentration in the portions P1 to P5 of the third region R3 may be 1 × 10 ¹⁶ [atoms / cm ³ ] or more, as shown in FIG. The presence of oxygen of 1 × 10 ¹⁶ [atoms / cm ³ ] or more is effective for improving the strength of the substrate, gettering of impurity metals, and the like. In this example, the oxygen concentration in the region between peak positions C4 and C5 was higher than the net P-type impurity concentration in that region.

FIG. 12A is a plot diagram showing the measurement results of the oxygen concentration dependence in the substrate SUB for the afterimage in the image. The horizontal axis in the figure indicates the oxygen concentration [atoms / cm ³ ] in the substrate SUB, and the vertical axis indicates the degree of afterimage (afterimage amount) [LSB] in the image. According to FIG. 12A, the amount of afterimage decreases when the oxygen concentration in the substrate SUB is lowered. Further, when the oxygen concentration in the substrate SUB is in the ^{range of 1 × 10 17} [atoms / cm ³ ] or less, the amount of afterimage is 8 [LSB] or less, and the afterimage in the image can be sufficiently and effectively reduced.

FIG. 12B shows the afterimage amount and the white scratches for each of the cases where the oxygen concentration in the substrate SUB is high and low, and the net P-type impurity concentration in the P-type region R3 is high and low, respectively. This is a summary of the judgment results of whether or not it is within the permissible range. “High” in the substrate SUB in FIG. 12 (b) indicates that the oxygen concentration is ^{higher than 1 × 10 17} [atoms / cm ³ ], and “low” means that the oxygen concentration is 1 ×. It is shown that it is 10 ¹⁷ [atoms / cm ^{3] or less.} A "low" net P-type impurity concentration in the P-type region R3 indicates that at least a portion of the P-type impurity concentration in the P-type region R3 is lower than the net N-type impurity concentration in the N-type region R1. The case of is indicated as "high".

In each of the above cases, for afterimages / white scratches, the results within the permissible range are indicated by "○", and those that are not are indicated by "x". For example, in the figure, if the afterimage is within the permissible range and the white scratch is not within the permissible range, it is indicated by “◯ / ×”. According to FIG. 12B, when the oxygen concentration in the substrate SUB is “low” and the net P-type impurity concentration in the N-type region R2 is “high”, both the afterimage and the white scratches are within the permissible range. You can see that.

(1-4. Summary)
According to this structure, the P-type region R3 is configured such that the net P-type impurity concentration of a part thereof is higher than the net P-type impurity concentration of a part of the other part deeper than the part. This prevents the depletion layer from reaching the other part. As a result, the width of the depletion layer between the N-type region R1-P-type region R3 can be reduced, and white scratches in the image can be suppressed. Then, the oxygen concentration in the substrate SUB was set to 1 × 10 ¹⁷ [atoms / cm ³ ] or less so that the thermal donor was not formed in the deep part of the P-type region R3. Thereby, the afterimage in the image can be suppressed.

As described above, according to the present embodiment, it is advantageous to suppress both afterimages and white scratches in the image.

In particular, when the image pickup apparatus 100 includes a digital circuit, the manufacturing method of the image pickup apparatus 100 may include, for example, a step of siliculating each electrode of a transistor in the digital circuit, so that metal impurities are mixed in the substrate SUB. There is a possibility that it will be done. For example, the image pickup apparatus 100 includes a pixel unit in which a plurality of pixels are arranged, and a peripheral circuit unit arranged around the pixel unit that processes signals from each pixel. As the transistor, those having a VDD region in the source and the drain can be used. The peripheral circuit unit includes, for example, an analog-to-digital conversion circuit, and a transistor having the silicide region can also be used as a part of this analog-to-digital conversion circuit. Nickel, cobalt, or the like is typically used as the metal in the silicide region, and a part of the metal is used as an impurity in the pixel portion as an impurity by the step of silicidizing the transistor (step of forming the silicide region) and the subsequent heat treatment step. Can spread to. As mentioned above, this can cause white scratches on the image. Therefore, according to the present embodiment, it is advantageous to suppress both afterimages and white scratches in the image, particularly in the image pickup apparatus 100 including the silicidal region.

13 (a) to 13 (e) are schematic views for explaining the state of each step in the manufacturing method of the image pickup apparatus 100.

In the step of FIG. 13 (a), in ^{the substrate SUB having an oxygen concentration of 2 × 10 17} [atoms / cm ³ ] or less, a region RA (pixel region) in which a pixel portion should be formed and a peripheral circuit portion are formed. A substrate SUB having a region RB (peripheral region) to be formed is prepared. The peripheral region RB includes, for example, a region RB1 in which an NMOS transistor should be formed and a region RB2 in which a MIMO transistor should be formed.

For example, on a silicon wafer oxygen concentration is ^{1 × 10 16 [atoms / cm} 3] or more and ^{3 × 10 17 [atoms / cm} 3] or less, the oxygen concentration by epitaxial growth ^{1 × 10 16 [atoms / cm} 3 ] The following single crystal silicon layer is formed. It is desirable that a silicon wafer having an oxygen concentration ^{not exceeding 3 × 10 17} [atoms / cm ^{3] be used.} When a silicon wafer having a high oxygen concentration (for example, 1 × 10 ¹⁸ [atoms / cm ³ ] or more) is used, even if a single crystal silicon layer having a low oxygen concentration is formed on the silicon wafer, other steps (heat treatment step, etc.) thereafter are performed. ), Oxygen moves (diffuses) from the wafer to the single crystal silicon layer. Therefore, it is preferable to use a silicon wafer having an oxygen concentration of at least 5 × 10 ¹⁷ [atoms / cm ³ ] or less.

The single crystal silicon layer formed by epitaxial growth is preferably formed so that its thickness is within the range of 5 to 25 [μm]. As a result, even when a silicon wafer having a relatively high oxygen concentration is used, oxygen in the silicon wafer can be diffused to the vicinity of the surface of the single crystal silicon layer, and it is possible to prevent the oxygen concentration of the single crystal silicon layer from becoming high. can.

In the prepared substrate SUB, for example, an element separation portion STI having an STI structure can be formed between the regions RA, RB1 and RB2. The element separation unit STI may be composed of an insulating member such as silicon oxide. The depth of the element separation unit STI is about 0.1 to 0.5 [μm].

After that, the P-type region R3 is formed by injecting a P-type impurity into the pixel region RA. The P-type region R3 includes the above-mentioned portions P0 to P5 (parts P0 to P5 are not shown here). The portions P0 to P5 can be formed, for example, by performing a plurality of impurity injections with different injection energies.

For example, P-type or N-type partial PAs, PBs, and PCs may be formed in the vicinity of the surface of the substrate SUB in order to adjust the threshold voltage of the transistor to be formed later. Further, in the portion of the substrate SUB that contacts the element separation portion STI, the element is separated in order to reduce the dark current component that may be mixed in the pixel signal due to the crystal defect at the boundary between the element separation portion STI and the substrate SUB. A P-shaped region CS may be formed so as to surround the portion STI.

In the step of FIG. 13B, for example, a P-type well PWL is formed in the region RB1 by injecting impurities using a predetermined resist pattern (not shown) formed on the substrate SUB. Then, in the same procedure, an N-type well NWL is formed in the region RB2. Any of these wells may be formed first.

In the step of FIG. 13C, an insulating film F (transistor gate insulating film) is formed on the surface of the substrate SUB. The insulating film F is made of, for example, silicon oxide, and its film thickness may be about 3 to 20 [nm]. After that, the gate electrode GTX of the transfer transistor and the gate electrode G of another MOS transistor are formed on the insulating film F. Further, an N-type region R1 is formed by injecting an N-type impurity into the surface of the substrate SUB and its vicinity. The N-type region R1 is preferably formed so that the above-mentioned peak position Q_R1 is deeper than half the depth of the element separation portion STI, and is preferably formed so as to be deeper than the bottom surface of the element separation portion STI. May be done.

After that, a floating diffusion FD can be formed using the gate electrode GTX as a mask. Further, a source / drain region RDS of the corresponding MOS transistor may be formed in each of the regions RB1 and RB2.

The formation order of each element constituting the pixel may be changed as needed. For example, for the gate electrode GTX and the N-type region R1, any of them may be formed first.

In the step of FIG. 13D, a region R0 for making the N-type region R1 an embedded type is formed. The region R0 can be formed at a position away from the end of the gate electrode GTX so that the charge transfer efficiency of the transfer transistor is maintained. The region R0 may be formed by injecting a P-type impurity into the substrate SUB (specifically, a part of the N-type region R1) using, for example, the gate electrode GTX and the resist pattern PR as masks. The injection angle of the impurities (the angle formed by the normal of the upper surface of the substrate SUB and the injection direction of the impurities) may be set in the range of, for example, 7 to 45 degrees. As a result, the region R0 is formed at a position away from the end of the gate electrode GTX. For example, when the height of the gate electrode GTX is 250 [nm], the injection may be performed with an injection energy of 12 [keV] and an injection angle within the range of 10 to 20 degrees.

In the step of FIG. 13E, an insulating film covering the regions RA, RB1 and RB2 is formed, and a part of the insulating film is etched to form a sidewall spacer SWS on the side surface of the gate electrode G. At this time, the other part of the insulating film can be left in the region RA as the protective film PDP. Then, by injecting an N-type impurity, the NMOS transistor in the region RB1 is made into an LDD structure, and similarly, by injecting a P-type impurity, the epitaxial transistor in the region RB2 is made into an LDD structure. After that, these MOS transistors are subjected to silicide treatment using a salicide process. At this time, the protective film PDP of the region RA can also be used as the silicide protection. Part Psili in the figure shows a silicidized silicide region in the electrodes of each MOS transistor.

After that, a structure including a wiring pattern, an optical element, and the like may be formed on the structure obtained in the step of FIG. 13 (e) by using a known semiconductor manufacturing technique. In this way, the image pickup apparatus 100 Can be manufactured.

As described with reference to FIG. 13A, the image pickup apparatus 100 may include element separation portions P1 and P2 having an STI structure. The element separation portions P1 and P2 can be formed by forming a trench from the surface of the substrate SUB to a predetermined depth by etching or the like, and filling the trench with an insulating member. According to this step, metal impurities may be mixed in the substrate SUB, and the stress applied to the substrate SUB due to the heat treatment during that period, the stress applied to the substrate SUB by the formed element separation portions P1 and P2, etc. White scratches may occur in the image. Therefore, applying the present invention to the image pickup apparatus 100 including the element separation portion of the STI structure is also advantageous in suppressing both afterimages and white scratches in the image.

14 (a) to 14 (d) are diagrams for explaining a process of forming an element separation portion (referred to as an element separation portion P) of the STI structure in the manufacturing method of the image pickup apparatus 100. In the step of FIG. 14A, for example, a structure in which a silicon oxide film F1, a polysilicon film F2, and a silicon nitride film F3 are formed in this order on a substrate SUB made of silicon is prepared.

In the step of FIG. 14B, the trench T is formed by, for example, etching using a predetermined resist pattern (not shown). The trench T may be formed from the upper surface of the silicon nitride film F3 to a predetermined depth from the surface of the substrate SUB.

In the step of FIG. 14C, for example, an oxidation treatment is performed to form an oxide film F4 (silicon oxide film) on the exposed surface of the substrate SUB exposed by the trench T. The oxidation treatment may be performed by, for example, dry oxidation at a temperature of about 1100 ° C. The film thickness of the oxide film F4 may be about 20 to 50 [nm].

In this step, the exposed surface of the substrate SUB is oxidized, and the exposed surface (side surface) of the polysilicon film F2 exposed by the trench T is also oxidized. As a result, a silicon oxide film is also formed on the exposed surface of the polysilicon film F2, and the silicon oxide film has an effect of maintaining the shape of the trench T.

In the step of FIG. 14D, the trench T is filled with an insulating member IM such as silicon oxide. This step may be performed by a deposition method such as CVD (Chemical Vapor Deposition). After that, the upper surface of the insulating member IM may be flattened by, for example, CMP treatment, and the element separating portion P is formed in this way.

Although some preferred embodiments have been illustrated above, the present invention is not limited to these examples, and some of them may be modified without departing from the spirit of the present invention. For example, the conductive type of each semiconductor region may be reversed, or the same conductive type and different elements may be used as the impurities forming the same.

Further, it goes without saying that the individual terms described in the present specification are used only for the purpose of explaining the present invention, and the present invention is not limited to the strict meaning of the terms. The equivalent may also be included. For example, the "imaging device" may include a solid-state imaging device such as a CCD image sensor or a CMOS image sensor, the "pixel" may be referred to as a sensor, and the "pixel signal" may be a sensor signal accordingly. May be called.

FIG. 15 is a diagram for explaining a configuration example of a camera to which the image pickup apparatus 100 shown in the above example is applied. In addition to the image pickup apparatus 100, the camera includes, for example, a processing unit 200, a CPU 300 (or a processor), an operation unit 400, and an optical system 500. Further, the camera may further include a display unit 600 for displaying a still image or a moving image to the user, and a memory 700 for storing the data. The image pickup apparatus 100 generates image data composed of digital signals based on the light that has passed through the optical system 500. The image data is subjected to predetermined image processing by the processing unit 200 and output to the display unit 600 and the memory 700. Further, the CPU 300 may change the setting information of each unit or the control method of each unit according to the shooting conditions input by the user via the operation unit 400. The concept of a camera includes not only a device whose main purpose is shooting but also a device having an auxiliary shooting function (for example, a personal computer or a mobile terminal).

Hereinafter, still another aspect of the present invention will be described through a third embodiment, which is an exemplary embodiment thereof.

This embodiment is an embodiment having both the features of the first embodiment and the features of the second embodiment. That is, in the present embodiment, the photoelectric conversion element PD in the first embodiment has a structure similar to that of a photodiode in which a PN junction is formed between the N-type region R1 and the P-type region R3 in the second embodiment. It is a form. Further, in the present embodiment, the first semiconductor region 101 in the first embodiment corresponds to the N-type region R4 in the second embodiment. The impurity region 102a in the first embodiment corresponds to the N-type region R2 in the second embodiment. The impurity region 103 having the second conductive type in the first embodiment corresponds to the P-type region R3 in the second embodiment. As described in the second embodiment, since the P-type region R3 has a plurality of portions P0 to P5, the impurity region 103 has a plurality of portions corresponding to the plurality of portions P0 to P5. The first conductive type impurity region 104 in the first embodiment corresponds to the N type region R1 in the second embodiment. The first conductive type impurity region 102b in the first embodiment corresponds to the partial PA or partial PB in the second embodiment. In the present embodiment, the semiconductor substrate SS in the first embodiment and the substrate SUB in the second embodiment will be collectively referred to as "substrate S".

FIG. 11 only shows the oxygen concentration up to a depth of 6 μm on the substrate SUB, but in the present embodiment, it is deeper than 6 μm from the surface of the substrate S and more than 20 μm such that the N-type region R4 exists. Even in the shallow part, it has the same oxygen concentration distribution as in FIG. That is, when the maximum and minimum values of the oxygen concentration in the semiconductor region in the portion where the distance from the surface of the substrate S is within 20 μm are Cmax and Cmin, respectively, Cmax / Cmin is 10 or less, preferably 5 or less. be. Further, the oxygen concentration in the semiconductor region in the portion where the distance from the surface is within 20 μm is within the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less. Other points are the same as those of the first embodiment and the second embodiment.

^{In the present embodiment, as described above, the presence of oxygen of 1 × 10 16} [atoms / cm ³ ] or more in the shallow portion of the substrate S (semiconductor substrate SS or substrate SUB) is effective for gettering of impurity metals and the like. .. However, in the present embodiment, the oxygen concentration in the deep part (semiconductor region 101, region R4) of the semiconductor substrate SS or the substrate SUB is as low as ^{5 × 10 15} [atoms / cm ^{3] or less.} Therefore, the gettering action of the impurity metal in the deep part of the substrate S cannot be expected to be large. It is known that the metal in the silicide region provided in the transistor of the peripheral circuit portion diffuses to the pixel portion via the deep portion of the substrate S. Therefore, as in the present embodiment, the net P-type impurity concentration of a part of the P-type region of the photodiode is higher than that of the other part of the net P-type impurity concentration at a position deeper than the part. By configuring it to be high, the influence of impurity metals existing in the deep part is reduced. Therefore, both afterimages and white scratches can be suppressed to an appropriate level.

Hereinafter, yet another aspect of the present invention will be described through a fourth embodiment, which is an exemplary embodiment thereof.

This embodiment is characterized by the element separation part described in the first to third embodiments. The element separation unit 110 of the first embodiment corresponds to the element separation unit STI of the pixel region RA of the second embodiment. The insulator 160 and the silicon oxide film 170 of the element separating portion 110 in the first embodiment correspond to the insulating member IM and the oxide film F4 of the element separating portion STI in the second embodiment, respectively. The impurity region 109 in the first embodiment corresponds to the impurity region CS in the second embodiment. Hereinafter, the element separation unit 110 of the first embodiment and the element separation unit STI of the pixel region RA of the second embodiment will be collectively referred to as “element separation unit ISO”. Further, the insulator 160 and the silicon oxide film 170 of the element separating portion 110, the insulating member IM and the oxide film F4 of the element separating portion STI will be collectively referred to as “insulator INS”. The device separator ISO has an STI structure, and a typical insulator INS is made of silicon oxide. The peripheral region RB of the second embodiment will be described as the element separation unit STI and the insulating member IM according to the second embodiment. Also in this embodiment, the semiconductor substrate SS in the first embodiment and the substrate SUB in the second embodiment will be collectively referred to as "substrate S".

In the present embodiment, the hydrogen concentration CA [atoms / cm ³ ] of the insulator INS of the element separation unit ISO is set to 5 × 10 ¹⁸ [atoms / cm ³ ] or more. The hydrogen concentration CA of the insulator INS ^{is preferably 1 × 10 19} [atoms / cm ³ ] or more, and more preferably 3 × 10 ¹⁹ [atoms / cm ³ ] or more. As described above, the ^{presence of oxygen of 1 × 10 16} [atoms / cm ³ ] or more on the substrate S is effective for gettering of impurity metals and the like. However, in that case, the gettering action of the impurity metal is reduced as compared with the case where oxygen of ^{1 × 10 18} [atoms / cm ^{3] or more is present on the substrate S.} By setting the hydrogen concentration CA to 5 × 10 ¹⁸ [atoms / cm ³ ] or more, and further to 1 × 10 ¹⁹ [atoms / cm ³ ] or more, noise such as white scratches caused by impurity metals can be alleviated. It is presumed that this is because the impurity metal is inactivated by hydrogen. Further, trench etching of the substrate S is required to form the element separation portion ISO having the STI structure. The deterioration of image quality due to damage caused to the substrate S by this trench etching can be reduced by hydrogen terminating the dangling bond on the surface of the substrate S. In this study, the hydrogen concentration in the element separation part having the STI structure of the image pickup device was 2 × 10 ¹⁸ [atoms / cm ³ ] in the whole insulator of the element separation part. The hydrogen concentration CA of the insulator INS may be 3 × 10 ²¹ [atoms / cm ³ ] or less, or 1 × 10 ²¹ [atoms / cm ³ ] or less. It suffices if there is a portion in the insulator INS that satisfies the above-mentioned conditions for the hydrogen concentration CA, and there may be a portion in the insulator INS that does not satisfy the above-mentioned conditions. It is preferable that the total hydrogen concentration CA of the insulator INS satisfies the above-mentioned conditions. The hydrogen concentration CA can be adjusted by adopting a film forming method (for example, HDP-CVD method) capable of increasing the hydrogen content in the insulator IM or a raw material gas for film forming (for example, a silane gas). It can also be adjusted by introducing hydrogen from the outside such as an insulating film containing hydrogen on the substrate S.

16 (a) and 16 (b) show the first example and the second example of the distribution of the hydrogen concentration CA in this embodiment. In FIGS. 16A and 16B, the position TL indicates the position of the surface of the substrate S, and the position BL indicates the position of the bottom surface of the element separation portion ISO. The difference between the position TL and the position BL corresponds to the depth of the element separation portion ISO. The depth of the element separation unit ISO is, for example, 0.1 to 0.5 μm, typically 0.2 to 0.4 μm. In the examples of FIGS. 16A and 16B, the depth of the element separation portion ISO is 0.26 μm. In the first example shown in FIG. 16A, the hydrogen concentration CA is distributed in the range of ^{1 × 10 19} to 2 × 10 ²⁰ [atoms / cm ^3]. In the second example shown in FIG. 16B, the hydrogen concentration CA is distributed in the range of ^{2 × 10 19} to 1 × 10 ²¹ [atoms / cm ^3]. In both the first example and the second example, the hydrogen concentration is remarkably increased near the bottom surface (near the position BL) of the device separation portion ISO. As described above, it is preferable that the hydrogen concentration in the lower half of the position BL side is higher than that of the upper half of the position TL side with reference to the position of half the depth of the element separation portion ISO. By doing so, hydrogen can be effectively supplied into the substrate S.

As described above, the hydrogen concentration CA [atoms / cm ³ ] of the insulator INS of the element separation unit ISO shows a distribution. An index that quantitatively indicates the amount of hydrogen in the insulator INS is the hydrogen density DA [atoms / cm ² ] of the insulator INS. The hydrogen density DA is an integral value of the hydrogen concentration CA in the depth direction. If the hydrogen concentration CA is constant in the depth direction and the depth of the element separation unit ISO is DP [cm], the hydrogen density DA is the product of the hydrogen concentration CA and the depth DP (DA = CA × DP). be. When the hydrogen concentration CA shows a distribution, the sum of the products of the resolution DR [cm] (DR = DP / n) in the depth direction and the hydrogen concentration CAn at each depth (DA = Σ (DR × CAn)). be.

By setting the hydrogen density DA to 1 × 10 ¹⁴ [atoms / cm ² ] or more, a practical effect of reducing white scratches can be obtained. A hydrogen density DA of 1 × 10 ¹⁴ [atoms / cm ² ] means that the hydrogen concentration CA is uniformly 5 × 10 ¹⁸ [atoms / cm ² ] in the device separation unit ISO having a depth of 0.2 μm. Corresponds to the case. The hydrogen density DA may be 3 × 10 ¹⁵ [atoms / cm ² ] or less. The hydrogen density DA of 1 × 10 ¹⁴ [atoms / cm ² ] means that the hydrogen concentration CA is uniformly 1 × 10 ²⁰ [atoms / cm ² ] in the element separation unit ISO having a depth of 0.3 μm. Corresponds to the case of. As described above, the hydrogen concentration CA can be higher in the lower half than the upper half of the device separation part ISO, so that the hydrogen density DA is dominated by the hydrogen concentration CA in the lower half of the device separation part ISO. Therefore, it is preferable that the portion located in the lower half of the element separation portion ISO satisfies the above-mentioned hydrogen concentration CA condition.

FIG. 17 shows the relationship between the hydrogen density and the number of white scratches. One of the two points in the graph of FIG. 17 corresponds to FIG. 16A, and the hydrogen density DA calculated from the distribution of the hydrogen concentration CA is 5.5 × 10 ¹⁴ [atoms / cm ² ]. The other of the two points in the graph of FIG. 17 corresponds to FIG. 16 (b), and the hydrogen density DA calculated from the distribution of the hydrogen density CA is 2.5 × 10 ¹⁵ [atoms / cm ² ]. It can be read that the white scratches can be reduced as the hydrogen density DA increases. If the hydrogen density DA is 2 × 10 ¹⁴ [atoms / cm ² ], the number of white scratches is expected to be about 5,000, and 1.4 × 10 ¹⁵ [atoms] to further halve the white scratches from the level of 5,000. / Cm ² ]. By setting the hydrogen density DA to 1.4 × 10 ¹⁵ [atoms / cm ² ] or more, white scratches can be sufficiently reduced.

Next, the relationship between the element separation unit ISO in the pixel region RA and the element separation unit STI in the peripheral region RB described in the second embodiment will be described. Here, the hydrogen concentration of the insulating member of the element separating portion STI in the peripheral region RB shown in FIG. 13 is defined as CB [atoms / cm ³ ]. The hydrogen concentration CB of the insulating member of the element separating portion STI in the peripheral region RB is preferably lower than the hydrogen concentration CA of the insulator INS (insulating member IM) of the element separating portion ISO in the pixel region RA. In the manufacturing process of the image pickup apparatus 100, various defects occur in the substrate S. Examples of this defect include a point defect in the semiconductor substrate S and an interface state existing at the interface between the substrate S and the element separation portion ISO. Further, for example, the interface state existing at the interface between the substrate S and the gate insulating film and defects in the gate insulating film can be mentioned. These defects lead to deterioration of transistor performance and increase of noise generated in the pixel circuit area. The noise generated in the pixel region RA is directly related to the image quality. Therefore, in the pixel region RA, it is desirable to promote the hydrogen termination of defects by increasing the hydrogen supply amount. On the other hand, in the peripheral region RB, it is desirable to limit the hydrogen supply amount when the main point is to ensure the reliability of the MIS transistor. This is due to the following reasons. In the image pickup apparatus 100, the miniaturization of the MIS transistor constituting the peripheral region RB is progressing due to the demand for high speed signal processing speed and low power consumption. With the progress of miniaturization, a decrease in hot carrier resistance and a decrease in reliability of MIS transistors such as NBTI (Negative Bias Temperature Institute) become apparent. In the presence of excess hydrogen, the deterioration of their properties is promoted. Therefore, by satisfying CB <CA, it is possible to improve the characteristics of the pixel region RA and the peripheral region RB at the same time.

Regarding the difference in hydrogen concentration between the pixel region RA and the peripheral region RB, for example, the protective film PDP in the pixel region RA suppresses the outward diffusion of hydrogen in the insulating member of the element separation portion STI, and the protective film PDP in the peripheral region RB is used. It can be realized by removing it. Further, by making the wiring structure as the hydrogen inhibitory member different between the pixel region RA and the peripheral region RB, it can be realized by making the hydrogen supply amount from the hydrogen supply source such as the passivation film provided above the wiring structure different. ..

As the hydrogen concentration in the insulator INS of the element separation unit ISO, a value calculated by SIMS analysis can be adopted. The SIM analysis of the element separation unit ISO can be performed from the surface (back surface) opposite to the surface (front surface) on which the element separation unit ISO and the transistor are provided on the substrate S. SIMS analysis can also be performed from the surface side of the substrate S with all layers other than the substrate S and the element separation portion ISO removed. Hereinafter, a method for calculating the hydrogen concentration CA will be described.

FIG. 18 shows an outline of the arrangement pattern of the element unit ACT and the element separation unit ISO of the pixel region RA and the analysis region AA by SIMS. The analysis area AA is a rectangular area having a side of about several tens of μm or a circular area having a diameter of about several tens of μm, and the area thereof is SC (cm ² ). In the pixel region RA, a pattern of a pixel circuit of about several μm is repeatedly arranged. Therefore, the analysis area AA includes several to several tens of pixel circuit patterns. SIMS analysis is performed on this analysis area AA to calculate the ^{hydrogen concentration MA (atoms / cm 3) in the analysis area AA.} Since the pixel circuit RA is a repeating pattern of the pixel circuit, the hydrogen concentration MA in the analysis region AA is almost the same regardless of which region in the pixel region RA the SIMS analysis is performed. The device part ACT is made of silicon having a low solid solution limit of hydrogen, while the element separation part ISO is made of an insulator such as silicon oxide having a high solid solution limit of hydrogen. Therefore, the hydrogen concentration of the element unit ACT is negligibly lower than the hydrogen concentration of the element separation unit ISO. Focusing on the fact that the element unit ACT and the element separation unit ISO are included in the analysis region AA of the hydrogen concentration MA, the hydrogen concentration MA obtained by the SIMS analysis is a SIMS including the element unit ACT and the element separation unit ISO. It can be said that it is the average hydrogen concentration in the analysis area of. Then, the hydrogen concentration of the element unit ACT becomes negligibly low as compared with the hydrogen concentration of the element separation unit ISO. Therefore, the hydrogen concentration MA obtained by SIMS analysis is not equivalent to the hydrogen concentration CA of the device separation unit ISO. This is because the element separation unit ISO does not exist in the entire analysis area, but the element unit ACT and the element separation unit ISO coexist in the analysis area. Therefore, the hydrogen concentration CA of the actual device separation unit ISO is calculated as follows. First, the area occupancy rate OA of the element separation unit ISO in the analysis area AA is calculated. The area occupancy rate can be calculated from the CAD data or the like used in the layout design of the element separation unit ISO. ^{The area occupancy rate OA of the element separation unit ISO is a value obtained by dividing the total area SA (cm 2} ) of the area of the element separation unit ISO when the analysis area AA is viewed in a plan view by the area SC of the analysis area AA (OA = SA). / SC). The hydrogen concentration CA in the insulator of the device separation section ISO is a value obtained by dividing the hydrogen concentration MA in the analysis region AA by the area occupancy rate OA of the device separation section ISO (CA = MA / OA). The area occupancy rate OA is a value larger than 0 and smaller than 1, and is about 0.2 to 0.6. In the image pickup apparatus 100, in order to increase the light receiving area of the photoelectric conversion unit PD, the element unit ACT of the pixel region RA is set to be larger than the element separation unit ISO, and the OA may be 0.5 or less.

The hydrogen concentration CB in the peripheral region RB can be calculated in the same manner. That is, the hydrogen concentration CB in the insulator IM of the device separation unit STI in the peripheral region RB is a value obtained by dividing the hydrogen concentration MB in the analysis region with respect to the peripheral region RB by the area occupancy rate OB of the device separation unit STI (CB =). MB / OB). ^{The area occupancy rate OA of the element separation unit STI is a value obtained by dividing the total area SB (cm 2} ) of the area of the element separation unit STI when the analysis area with respect to the peripheral area RB is viewed in a plan view by the area SC of the analysis area (OB). = SB / SC).

In the image pickup apparatus 100, in order to increase the light receiving area of the photoelectric conversion unit PD, the element unit of the pixel region RA is set to be larger than the element separation unit ISO. Therefore, the area occupancy rate OA of the element separation unit ISO in the pixel region RA is lower than the area occupancy rate OB of the element separation unit STI in the peripheral region RB (OA <OB). On the other hand, the amount of hydrogen supplied from the element separation units ISO and STI per unit volume is preferably larger in the pixel region RA than in the peripheral region RB. The amount of hydrogen QA that can be supplied from the element separation unit ISO per unit volume in the pixel region RA is proportional to the value obtained by multiplying the hydrogen concentration CA by the area occupancy rate OA (QA∝CA × OA). Similarly, the amount of hydrogen QB that can be supplied from the element separation unit STI per unit volume in the peripheral region RB is proportional to the value obtained by multiplying the hydrogen concentration CB by the area occupancy rate OB (QB∝CB × OB). Therefore, satisfying QB <QA means satisfying CB × OB <CA × OA. In order to satisfy both OA <OB and CB × OB <CA × OA, it is more preferable to satisfy 10 × CB ≦ CA. Since CA × OA = MA and CB × OB = MB, whether or not QB <QA is satisfied is detected in the analysis area having the same shape with respect to the pixel area RA and the peripheral area RB in the SIMS analysis. It can be judged by comparing the amount of hydrogen produced.

The oxygen concentration in the first to fourth embodiments described above can also be analyzed by SIMS. In that case, the SIMS analysis region includes not only the semiconductor region but also the element separation unit ISO. Therefore, in the substrate S in the SIMS data, the presence of oxygen in the silicon oxide constituting the element separation part ISO is present in the oxygen concentration at the depth (for example, 0.1 to 0.5 μm) where the element separation part ISO exists. It is reflected extremely strongly. Oxygen derived from silicon oxide in this device separator ISO should be distinguished from oxygen in the semiconductor region. In reality, the oxygen concentration at the depth at which the element separation portion ISO exists in the SIMS analysis data of the substrate S can be considered by excluding it from the oxygen concentration distribution in the semiconductor region. It is also possible to evaluate the oxygen concentration in the semiconductor region of the portion shallower than the bottom surface of the element separation portion ISO by removing the element separation portion ISO from the substrate S by wet etching or the like and then performing the measurement by SIMS. Is.

The first embodiment aims to supply oxygen from the inner surface of the trench TR to the deep part of the second semiconductor region 102, and it is the first embodiment that the oxygen concentration at the depth where the element separating portion 110 exists is not taken into consideration. It does not deviate from the purpose of. Therefore, the oxygen concentration range, the maximum value, and the minimum value of the semiconductor substrate SUB may be evaluated in a portion deeper than the element separation unit 110. In other words, the range, maximum value, and minimum value of the oxygen concentration of the semiconductor substrate SUB may be evaluated at a portion deeper than the portion of the surface of the semiconductor substrate SUB that constitutes the bottom surface of the element separation portion 110. In the graph shown in FIG. 9, the oxygen concentration at the depth at which the element separating portion 110 exists is omitted.

In the second embodiment, the net P-type impurity concentration of a part of the P-type region R3 is higher than the net P-type impurity concentration of another part at a position deeper than the part. The depletion layer is prevented from reaching the part deeper than the certain part and the other part. One portion may be, for example, a portion P1, and the other portion may be, for example, an N-type charge accumulator, or, for example, portions P2-4 deeper than P1. As a result, the width of the depletion layer between the N-type region R1-P-type region R3 can be reduced, and white scratches in the image can be suppressed. In the second embodiment, the peak position Q_R1 of the N-type region R1 is preferably arranged so as to be deeper than half the depth of the element separation portion STI, preferably at a position deeper than the bottom surface of the element separation portion STI. It may be arranged.

The second embodiment is also applied to a so-called back-illuminated image pickup device in which optical elements such as a color filter and a microlens are arranged on the opposite side (back surface side) of the substrate provided with transistors and wiring layers. It is possible. In that case, the P-type region R3 may be exposed and arranged on the back surface without the N region R2 and the N-type region R4 existing. In a back-illuminated image pickup device, a single crystal silicon layer is formed on an N-type region R4 as a silicon wafer by epitaxial growth, and an ion implantation into the single crystal silicon layer causes an N-type region R1 or a P-type region R3 or the like. Can be formed. After that, a part of the silicon wafer and the single crystal silicon layer (corresponding to the N-type region R2) is removed by polishing, but if oxygen diffuses into the single crystal silicon layer before polishing, the P-type region as described above is used. In the presence of oxygen in the silicon, the effects of afterimages can occur as well. Furthermore, the problem of afterimages due to light that is easily absorbed by silicon, such as blue light, is likely to occur. Therefore, it is useful to apply the present invention to a back-illuminated imaging device. For example, if at least a part of the P-type region R3 located on the back surface side where the light is incident has a low oxygen concentration, the influence of the afterimage can be reduced. Further, if the structure can suppress the spread of the depletion layer to the P-shaped region R3, the influence of white scratches due to polishing of the substrate can be reduced.

The embodiments described above can be appropriately combined as long as they do not deviate from the idea of the present invention, and the combinations form a part of the present disclosure. In addition, matters that can be clearly grasped from the drawings, particularly specific numerical values in various graphs, form a part of the present disclosure even if they are not clearly described in the present specification.

100: Imaging device, 101: 1st semiconductor region, 102: 2nd semiconductor region, R1: N-type region, R2: N-type region, R3: P-type region.

Claims (9)

A wafer having a first semiconductor region made of single crystal silicon having an oxygen concentration in the range of 2 × 10 ¹⁶ atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ³ or less, and a wafer arranged on the wafer and having an oxygen concentration. A step of preparing a substrate including a silicon layer having a second semiconductor region made of single crystal silicon lower than that of the first semiconductor region.
A step of forming a trench in the silicon layer of the substrate and
The substrate was subjected to the first heat treatment in an oxygen-containing atmosphere so that the inner surface of the trench was oxidized, and the oxygen concentration in the second semiconductor region was ^{adjusted to 2 × 10 16} atoms / cm ³ or more 4 ×. 10 ¹⁷ atoms / cm ³ or less step and
A step of forming a conductive type impurity region opposite to the conductive type of the second semiconductor region along the inner surface of the trench, and
After the formation of the impurity region, the substrate is subjected to a second heat treatment in an oxygen-free atmosphere to reduce the oxygen concentration on the surface of the substrate, but the oxygen concentration in the second semiconductor region is reduced by 2 ×. The process of maintaining within the range of ^{10 16} atoms / cm ³ or more and 4 × 10 ¹⁷ atoms / cm ^{3 or less, and}
After the second heat treatment, a step of forming a charge storage portion of the photoelectric conversion element in the second semiconductor region, and
A method for manufacturing an imaging device, which comprises. A step of filling the trench with an insulator is further included after the formation of the impurity region and before the second heat treatment.
The method for manufacturing an imaging device according to claim 1, wherein the image pickup apparatus is manufactured. The first heat treatment is carried out at a temperature of 800 ° C. or higher and 1150 ° C. or lower.
The method for manufacturing an imaging device according to claim 1 or 2, wherein the image pickup apparatus is manufactured. In the step of performing the first heat treatment, after heating the substrate, the substrate is cooled at a temperature drop rate of 1 ° C./sec or more.
The method for manufacturing an imaging device according to any one of claims 1 to 3, wherein the image pickup apparatus is manufactured. The silicon layer is an epitaxial layer having a thickness of 5 μm or more and 25 μm or less.
The method for manufacturing an imaging device according to any one of claims 1 to 4, wherein the image pickup apparatus is manufactured. It has a step of forming a gate electrode on the surface of the substrate, and has a step of forming a gate electrode.
After forming the gate electrode, C22max / C22min is 10 or less when the maximum and minimum values of the oxygen concentration in the second semiconductor region are C22max and C22min, respectively.
The method for manufacturing an imaging device according to any one of claims 1 to 5, wherein the image pickup apparatus is manufactured. After the first heat treatment and before the second heat treatment, in the second semiconductor region, as a part of the photoelectric conversion element, a conductive type impurity region opposite to the conductive type of the second semiconductor region. Including the step of forming
The method for manufacturing an imaging device according to any one of claims 1 to 6, wherein the image pickup apparatus is manufactured. A peripheral circuit unit including a pixel unit in which a plurality of pixels are arranged on a substrate made of silicon and a peripheral circuit unit arranged around the pixel unit on the substrate and processing a signal from each pixel. An image pickup device having a circuit unit and
The peripheral circuit portion has a transistor having a silicide region containing at least one of nickel and cobalt.
Each pixel is
A first conductive type region including a portion formed on the substrate and accumulating charges generated by photoelectric conversion, and a first region of the first conductive type.
A second region of the first conductive type arranged at a position deeper than the first region of the substrate and away from the first region, and
A second conductive type third region arranged between the first region and the second region in the depth direction from the surface of the substrate,
Have,
The distribution of the net impurity concentration of the second conductive type in the third region in the depth direction has a plurality of maximum values, and the plurality of maximum values are the first region among the plurality of maximum values. The first maximum value at the first position closest to the above and the second maximum value at the second position between the first position and the second region are included, and the first maximum value is the first maximum value. Greater than 2 maxima ,
An imaging device characterized in that the oxygen concentration at the second position ^{is 1 × 10 17} atoms / cm ^{3 or less.} A peripheral circuit unit including a pixel unit in which a plurality of pixels are arranged on a substrate made of silicon and a peripheral circuit unit arranged around the pixel unit on the substrate and processing a signal from each pixel. An image pickup device having a circuit unit and
The peripheral circuit portion has a transistor having a silicide region containing at least one of nickel and cobalt.
Each pixel is
A first conductive type region including a portion formed on the substrate and accumulating charges generated by photoelectric conversion, and a first region of the first conductive type.
A second region of the first conductive type arranged at a position deeper than the first region of the substrate and away from the first region, and
A second conductive type third region arranged between the first region and the second region in the depth direction from the surface of the substrate,
Have,
The distribution of the net impurity concentration of the second conductive type in the third region in the depth direction has a plurality of maximum values, and the plurality of maximum values are the first region among the plurality of maximum values. The first maximum value at the first position closest to the above and the second maximum value at the second position between the first position and the second region are included, and the first maximum value is the first maximum value . Higher than the maximum value of the net impurity concentration of the first conductive type in one region,
An imaging device characterized in that the oxygen concentration at the second position is 1 × 10 ¹⁷ atoms / cm ^{3 or less.}

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