JP2007141937A - Solid-state imaging device, semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device wherein the formation of an element isolation area results in no reduction of sensitivity of a photo diode, leak current can be suppressed, and saturation is hard to occur even during large signal, and which has a trench element isolation structure. <P>SOLUTION: The solid-state imaging device is provided with a photo diode 8 and a transistor 7 on a semiconductor substrate. An element isolation area 3 which isolates the photo diode 8 from the transistor 7 is provided with a trench enclosing the photo diode (second semiconductor layer 6), and an insulator embedded in the trench. The section of a side wall on the side of the photo diode area of the trench is tapered as shallower toward the photo diode area. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a solid-state imaging device in which photoelectric conversion elements are formed in each light receiving region, and a method for manufacturing the same.

  As a photoelectric conversion element using a semiconductor, a photodiode using a pn junction in a semiconductor is known. A solid-state imaging device in which such photoelectric conversion elements are arranged one-dimensionally or two-dimensionally on a single semiconductor substrate is widely installed in digital cameras, video cameras, copying machines, facsimiles, and the like. The solid-state imaging device is also known as an image sensor or a semiconductor image sensor. In such a solid-state imaging device, a photodiode is provided for each pixel. Furthermore, in a solid-state imaging device, an amplifier circuit for amplifying signal charges generated in the photodiode, a switch circuit used to select a specific one from photodiodes arranged in a matrix, etc. Each pixel is formed on a semiconductor substrate. Since the amplifier circuit and the switch circuit are usually formed by MOS transistors or the like, an element isolation region for isolating the photodiode portion from the amplifier circuit or the switch circuit or the like is required on the semiconductor substrate. In the following description, an amplifier circuit for selecting signal charges from a photodiode and a switch circuit provided for each photodiode are collectively referred to as a peripheral circuit.

  Among such solid-state imaging devices, CMOS image sensors manufactured by a CMOS process including peripheral circuits not only have the advantage of low power consumption, but also include an image signal processing circuit and a memory circuit in the same chip. It has an excellent feature of being possible. In a CMOS image sensor incorporating an image signal processing circuit, a photodiode array section is provided in which photodiodes for each pixel are combined with peripheral circuits corresponding thereto and arranged in a matrix. In addition, in such a CMOS image sensor, an image signal processing circuit and a horizontal selection circuit and a vertical selection circuit used for pixel selection are provided around the photodiode portion.

  When a solid-state imaging device having a photodiode array cell and an image signal processing circuit is formed using the latest semiconductor device process supported by the advancement of miniaturization technology, noise generated in the photodiode portion can be reduced. It is cited as an important issue. The photodiode is isolated from the peripheral circuit, but when a selective oxide film made of a LOCOS film or the like formed on a silicon semiconductor substrate is used for element isolation, the ratio of the area of the element isolation region to the total area This causes the problem that becomes too large. Therefore, STI (Shallow Trench Isolation) in which a buried oxide film is formed in a trench (groove) provided in a semiconductor substrate has been used as an element isolation region. When STI is used for element isolation of a photodiode, a large factor of noise generation, that is, leakage current generation, is leakage due to a silicon semiconductor layer-silicon oxide film interface near the trench and a recombination center existing in the vicinity thereof. .

  FIG. 5 is a cross-sectional view of a main part of a conventional solid-state imaging device using STI for element isolation of a photodiode. FIG. 5 mainly shows the photodiode and the surrounding element isolation region.

  An element isolation region 2 by STI is provided on the surface of the first semiconductor layer 1 which is a first conductivity type semiconductor region which is a silicon semiconductor substrate. As the trench, a shallow (narrow) trench having a box-shaped cross-sectional shape is used, and the depth of the trench is, for example, about 200 nm. A buried oxide film is buried in the trench of the element isolation region 2. The element isolation region 2 isolates at least the photodiode portion 8 from the transistor portion 7 of the peripheral circuit.

  In the photodiode portion 8, the conductivity type opposite to the first conductivity type (that is, the second conductivity type) (ie, the second conductivity type) from the surface of the semiconductor substrate (first semiconductor layer 1) to the lower position from the lower end position of the element isolation region 2. A second semiconductor layer 6 which is a semiconductor region of conductivity type is formed. The first semiconductor layer 1 and the second semiconductor layer 6 form a pn junction, thereby forming a photodiode serving as a photoelectric conversion unit. The second semiconductor layer 6 is also called a photodiode region.

  A surface diffusion layer 5 that is a semiconductor region of the first conductivity type is provided at the silicon-oxide film interface on the outermost surface of the photodiode in order to reduce dark current in the photodiode. Further, a channel stop region 9 which is a first conductivity type semiconductor region is provided so that the element isolation region 2 and the second semiconductor layer 6 do not directly contact each other. The surface diffusion layer 5 and the channel stop region 9 are for reducing dark current in the photodiode. In particular, the channel stop region 9 is formed so that the depletion region of the photodiode is separated from the trench element isolation region. . Since the channel stop region 9 is also a diffusion layer, it is also called an element isolation diffusion layer.

In order to form the first conductivity type diffusion layer (channel stop region 9) at a concentration sufficient to suppress the expansion of the depletion region at the element isolation interface, the first conductivity type is formed by ion implantation (ion implantation). The impurity is implanted into a position in contact with the element isolation region 2. Thereafter, a method of expanding the diffusion layer by thermal diffusion is effective. For example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2003-142675) proposes a technique for introducing an element isolation diffusion layer so as to surround the trench element isolation region with respect to the trench element isolation region provided around the photodiode. .
JP 2003-142673 A

  Incidentally, miniaturization of device sizes is progressing in semiconductor devices in general, and accordingly, shallow junctions are formed based on a scaling law. In such a miniaturization process, if the thermal load is too large, the diffusion of impurities proceeds excessively, making it difficult to form a shallow junction. Therefore, in the miniaturization process, it is necessary to reduce the thermal load, suppress impurity diffusion, and form a sharp impurity junction.

  On the other hand, considering the photodiode, in order to improve the sensitivity, it is necessary to detect all of the electron-hole pairs generated by incident light as signal charges. The thickness of 6 cannot be made too thin. When the element isolation diffusion layer (channel stop region) is formed by a single ion implantation in a miniaturization process in which the thermal load is restricted, the impurity concentration profile is a concentration profile having a peak in the implantation ion depth. Become. Therefore, a non-uniform concentration diffusion layer region is formed. In the example shown in FIG. 5, in order to form the element isolation region 9 at a position below the bottom surface of the element isolation region 2, slightly below the midpoint of the element isolation region 2 in the depth direction in the semiconductor substrate. Is the range of the implanted ions. The element isolation diffusion layer 9 is formed so as to narrow the second semiconductor layer 6 at this range of depth, and as a result, the volume of the second semiconductor layer 6 that is the photodiode region is reduced. As a result, the light receiving sensitivity is lowered and the saturation charge is lowered.

  In order to form the element isolation diffusion layer 9 having a uniform thickness along the element isolation region 2, it is conceivable to perform ion implantation a plurality of times under the condition that the acceleration voltage is changed. This increases the number of processes and also increases the cost.

  As described above, the problem in the case where the STI structure is used in the solid-state imaging device including the photodiode has been described. However, the same problem may occur with the progress of miniaturization even in the semiconductor device not including the photodiode. Consider a case where a semiconductor device has an element portion that is relatively susceptible to leakage current and an element portion that is less susceptible to influence, and these element portions are separated from each other. If trench isolation is employed in a miniaturized process, it is necessary to provide an element isolation diffusion layer on the element portion side that is relatively susceptible to leakage current. However, by providing the element isolation diffusion layer, miniaturization of the element part that is relatively susceptible to the leakage current is hindered for the same reason as described above.

  Therefore, an object of the present invention is to prevent the leakage current in the photodiode without increasing the element isolation region because the formation of the element isolation structure that separates the photodiode and the peripheral circuit does not lead to a decrease in sensitivity of the photodiode. An object of the present invention is to provide a solid-state imaging device having a trench element isolation structure that is less likely to cause saturation even at a large signal.

  Another object of the present invention is a semiconductor device having a first element portion that is relatively susceptible to leakage current and a second element portion that is less likely to be affected, without increasing the element isolation region. An object of the present invention is to provide a semiconductor device having a trench element isolation structure that can suppress a leakage current in a first portion.

  Still another method of the present invention is to provide a method for manufacturing the solid-state imaging device and the semiconductor device of the present invention.

  The solid-state imaging device according to the present invention includes a first conductive type first semiconductor region on a semiconductor substrate, and a second conductive type second semiconductor that forms a PN junction with the first semiconductor region and can store signal charges. In a solid-state imaging device having a photoelectric conversion unit including a region and a semiconductor element different from the photoelectric conversion unit, the solid-state imaging device includes an element isolation region that isolates the photoelectric conversion unit from the semiconductor element. A cross-sectional shape of the side wall on the photoelectric conversion unit side of the trench has a tapered shape that becomes shallower toward the photoelectric conversion unit side. .

  In the present invention, the photoelectric conversion unit is, for example, a photodiode having a pn junction. The semiconductor element different from the photoelectric conversion unit is, for example, a MOS transistor.

  In the solid-state imaging device of the present invention, it is preferable that the third semiconductor region of the first conductivity type is formed from the side wall to the semiconductor substrate side along the tapered side wall. The third semiconductor region is preferably formed with a uniform impurity concentration and a uniform thickness.

  The side wall of the trench on the semiconductor element side is preferably perpendicular to the surface of the semiconductor substrate or has a taper angle smaller than the taper angle of the side wall on the photoelectric conversion unit side. Here, the taper angle is an angle formed between a normal to the surface of the semiconductor substrate and a side wall.

  In the solid-state imaging device of the present invention, when a plurality of semiconductor elements are provided, it is preferable that element isolation between the semiconductor elements is performed by a second element isolation region having a box-shaped cross-sectional trench. .

  The semiconductor device of the present invention is a semiconductor device having a first element portion that is relatively susceptible to leakage current and a second element portion that is relatively less susceptible to leakage current on a semiconductor substrate. And an element isolation region that isolates the first element portion from the second element portion, and the element isolation region includes a trench that surrounds the first element portion and an insulator embedded in the trench. The cross-sectional shape of the side wall on the first element portion side of the trench has a tapered shape that becomes shallower toward the first element portion side.

  The method of manufacturing a semiconductor device according to the present invention has a tapered shape on the surface of a semiconductor substrate that surrounds the first element portion and the cross-sectional shape of the side wall on the first element portion side becomes shallower toward the first element portion side. In a method of manufacturing a semiconductor device in which a first trench and a second trench having a box-shaped cross-sectional shape are simultaneously formed, a first resist layer is formed at a position corresponding to the first element portion on the surface of the semiconductor substrate. And performing a reflow heat treatment to deform the sidewall of the first resist layer into a tapered shape, curing the first resist layer, and curing the first resist layer, Forming a second resist layer on the surface of the semiconductor substrate so that a portion excluding the formation positions of the trench and the second trench is covered with the resist, and forming the first resist layer and the second resist layer It characterized by having a the steps of etching the semiconductor substrate as a disk.

  In the method of manufacturing a semiconductor device according to the present invention, after the step of etching the semiconductor device, ion implantation is performed in a self-aligned manner with respect to the first trench, and the semiconductor is formed from the sidewall along the tapered sidewall. A step of forming a diffusion region on the substrate side may be provided.

  According to the present invention, it is possible to expand the photodiode region as compared with the conventional method by making the trench isolation tapered. Furthermore, since the trench isolation diffusion layer has only a minimum thickness necessary for suppressing the depletion layer spreading from the photodiode, the photoelectric conversion region is not unnecessarily narrowed. In addition, a uniform electric field generated at the PN junction of the photodiode can be obtained, the leakage current can be reduced, and an element with good noise characteristics can be realized.

  Next, a preferred embodiment of the present invention will be described with reference to the drawings.

  A solid-state imaging device according to an embodiment of the present invention is a photodiode array in which a circuit for one pixel is used as a unit cell and such unit cells are arranged in a matrix in a two-dimensional direction. Around the photodiode array, a horizontal selection circuit and a vertical selection circuit used for pixel selection are provided, and an image signal processing circuit that performs image processing based on a light reception signal from each pixel, if necessary, A memory for storing image signals is provided. Each unit cell, horizontal selection circuit, vertical selection circuit, image signal processing circuit, memory, and the like are provided on a single semiconductor substrate by a semiconductor device manufacturing process, as will be described later. The unit cell includes a photodiode that is a photoelectric conversion element, and a peripheral circuit that includes an amplifier circuit for amplifying signal charges generated by the photodiode and a switch circuit used to select a specific photodiode. ing.

  FIG. 1 is a cross-sectional view showing a configuration of a main part of a solid-state image sensor according to the present embodiment, showing an element isolation structure of a photodiode and a peripheral circuit in a unit cell of the solid-state image sensor, that is, a region for one pixel. Yes.

  The first semiconductor layer 1 formed of a first conductivity type (for example, p-type) semiconductor substrate is divided into a photodiode portion 8 and a transistor portion 7 of a peripheral circuit. The photodiode portion 8 is isolated from the transistor portion 7 by an element isolation region 3 formed so as to surround the photodiode. In the transistor portion 7, an element isolation region 2 made of a shallow trench having a box-shaped cross-sectional shape is provided in order to isolate individual transistors. Although not specifically shown in FIG. 1, each transistor constituting the peripheral circuit is formed in the transistor portion 7. Each of these element isolation regions 2 and 3 includes a trench (groove) formed in a semiconductor substrate and an insulator (for example, a buried oxide film) filling the trench.

  The photodiode portion 8 is a semiconductor region opposite to the first conductivity type from the surface of the first semiconductor layer 1 to a position slightly deeper than the bottom surface of the element isolation region 3, and is a second photodiode region that is a photodiode region. The semiconductor layer 6 is provided. Similar to that shown in FIG. 5, the first semiconductor layer 1 and the second semiconductor layer 6 form a pn junction for the photodiode.

  In the solid-state imaging device of this embodiment, in the trench of the element isolation region 3 that isolates the photodiode portion 8 and the transistor portion 7 of the peripheral circuit, the side wall on the transistor portion 7 side has a box shape, that is, substantially vertical. Alternatively, it is formed to have a steep gradient. On the other hand, the side wall of the trench on the photodiode portion 8 side is formed in a tapered shape that becomes shallower as it approaches the photodiode side. That is, the horizontal width of the trench increases from the bottom to the top of the trench, and the trench is formed so as to protrude toward the photodiode portion 8. The depth of the trench in the element isolation region 3 is, for example, 250 nm or less.

  Here, the inclination of the sidewall of the trench will be described. Considering the normal to the surface of the semiconductor substrate, the angle (taper angle) formed between the side wall on the transistor portion 7 side and the normal line is smaller than the taper angle on the side wall on the photodiode portion side. When the side wall on the transistor portion 7 side is perpendicular to the surface of the semiconductor substrate, the taper angle is 0 °. The side wall (tapered side wall) on the photodiode portion side has a taper angle of, for example, 30 ° to 60 °.

  A diffusion region 4 that is a semiconductor region of the first conductivity type is provided immediately below the element isolation region 3 surrounding the photodiode. The diffusion region 4 separates the second semiconductor layer 6, which is a photodiode region, from the element isolation region 3, and prevents the depletion layer formed in the photodiode region from expanding until it contacts the element isolation region 3. Is for. In this embodiment, the diffusion region 4 has a constant thickness from the interface to the silicon semiconductor region side along the tapered sidewall of the device isolation region 3, that is, the interface between the device isolation region 3 and the silicon semiconductor region. It is formed with a uniform impurity concentration. Furthermore, a surface diffusion layer 5 that is a semiconductor region of the first conductivity type is provided on the outermost surface of the photodiode region (second semiconductor layer 6) in order to reduce dark current in the photodiode.

  In general, when forming an element isolation region having a trench having a box-shaped cross-sectional shape, the trench is formed from the surface of the semiconductor substrate to a predetermined depth (for example, 200 nm) by anisotropic etching. The lateral width of the groove cannot be made too small. In addition, since the oxide film is buried in the groove after the trench is formed, the width of the groove cannot be reduced. That is, in a trench groove having a box-shaped cross-sectional shape, the width of the groove cannot be reduced to a certain extent. On the other hand, in the case of an element isolation region having a groove whose one side wall is tapered, the lateral width of the groove on the outermost surface of the semiconductor substrate is larger than the lateral width of the trench having a box-shaped cross-sectional shape. However, since the side wall is tapered, restrictions on anisotropic etching and embedding of the insulating film are eased. Therefore, the width at the lowermost position of the groove is larger than the width in the trench having a box-shaped cross-sectional shape. Can also be reduced. Therefore, when isolating a certain semiconductor region, even if an element isolation region having a trench having a box-shaped cross section is used, or an element isolation region having a tapered side wall on the semiconductor region side is used. However, the effective volume surrounded by the element isolation region is not so different.

  In the case of the present embodiment, as shown in FIG. 1 and as will become clear from the description of the manufacturing process described later, the thickness of the element isolation region 3 is increased along the tapered slope using simple steps. Is relatively thin and uniform diffusion region 4 can be formed. Since the diffusion region 4 can be formed with a uniform thickness, the solid-state imaging device of this embodiment has a photodiode region (the second region) as compared with a conventional solid-state imaging device in which the thickness of the element isolation diffusion layer is not uniform. The semiconductor layer 6) can be expanded. Furthermore, since the diffusion region 4 can be formed so as to have a minimum thickness necessary for suppressing the spread of the depletion layer from the photodiode, according to the present embodiment, the photoelectric conversion region is not unnecessarily narrowed. In addition, a uniform electric field generated at the pn junction can be obtained. Therefore, according to the present embodiment, it is possible to realize a solid-state imaging device with reduced leakage current and good noise characteristics.

  Although not shown in FIG. 1, in such a solid-state imaging device, an electrode wiring made of, for example, a polysilicon wiring is formed on the surface of the semiconductor substrate. Here, no electrode wiring is formed in the region immediately above the photodiode region (second semiconductor layer 6). This is because if a polysilicon wiring layer is formed on the photodiode region, this wiring layer absorbs incident light, resulting in a decrease in sensitivity as a photodiode.

  In a general semiconductor device in which an element isolation region is formed, electrode wiring is often laid out on the element isolation region. However, in the case of the element isolation structure having the tapered inner wall as described above, if the electrode wiring is disposed on the shallower trench isolation portion, a breakdown voltage defect may occur with the underlying silicon semiconductor layer. is there. Therefore, it is preferable to provide the element isolation region whose inner wall has a tapered shape only at a position where the electrode wiring does not cross. In a solid-state imaging device, an electrode wiring does not normally traverse an element isolation region for isolating a photodiode portion. Therefore, an element isolation region whose inner wall has a tapered shape is preferably used for element isolation of the photodiode portion. be able to. Even if it is not a photodiode part, it is an element part in a semiconductor device that does not require a separate electrode wiring and is relatively susceptible to leakage current, and the inner wall is tapered. It is possible to effectively use an element isolation region having

  Note that an element isolation region using a trench having a box-shaped cross-sectional shape is also used for element isolation between transistors in an image signal processing circuit and a memory arranged around the photodiode array in a solid-state imaging device. In image signal processing circuits and memories, electrode wiring and polysilicon wiring are often used. Therefore, an element isolation region having a box-shaped cross-sectional shape is preferable for separating the electrode wiring from the silicon semiconductor substrate. is there.

  FIG. 2 shows a circuit configuration of a unit cell configured in a circuit for one pixel in the solid-state imaging device. A ground potential is applied to the anode of the photodiode 101 for photoelectric conversion. The cathode of the photodiode 101 is connected to one end of the transfer MOS transistor 103 for reading the signal charge of the photodiode 101. Of course, the photodiode 101 is constituted by a pn junction formed by the first semiconductor layer 1 and the second semiconductor layer 6 in FIG. The other end of the transfer MOS transistor 103 is connected to one end of a reset MOS transistor 102 for resetting the photodiode 101 and to the gate of a MOS transistor 104 for converting the read charge into a voltage. The MOS transistor 104 operates as a source follower to perform voltage conversion, and one end of the MOS transistor 104 and the other end of the reset MOS transistor 102 are both connected to a power supply line 110 that supplies, for example, a voltage Vdd. . A row selection MOS transistor 105 for selectively outputting the output of the MOS transistor 104, that is, the source follower amplifier, is inserted between the other end of the MOS transistor 104 and the signal line 111. As described above, the unit cell includes one photodiode 101 and four MOS transistors 102 to 105, and it is necessary to isolate the photodiode 101 from the MOS transistors 102 to 105 on the semiconductor substrate. For this element isolation, as described above, the element isolation region 3 whose side wall on the photodiode 101 side is tapered is used. An element isolation region 2 having a box-shaped cross-sectional shape is used for element isolation between the MOS transistors 102 to 105.

  A reset signal φres is given to the gate of the reset MOS transistor 102 as a control signal. A transfer signal φtx is given as a control signal to the gate of the transfer MOS transistor 103. A row selection signal φsel is supplied to the gate of the row selection MOS transistor 105 as a control signal.

  In this unit cell, the signal charge generated in the photodiode 101 by photoelectric conversion is input to the gate of the MOS transistor 104 via the transfer MOS transistor 103. The MOS transistor 104 as a source follower amplifier amplifies the signal charge and converts it into a voltage signal. The voltage-converted signal is output on the signal line 111 via the row selection MOS transistor 105.

  Next, a manufacturing process of the solid-state image sensor of this embodiment will be described. As described above, the solid-state imaging device of the present embodiment is characterized in that the element isolation region surrounding the photodiode has a side wall formed in a tapered shape so as to become shallow toward the photodiode region. Further, in the manufacturing process of the present embodiment, an element isolation region having a box-shaped cross section and an element isolation region having a tapered side wall are formed simultaneously. Therefore, in the following, an example of the manufacturing process of the present embodiment will be described focusing on these points. In the following description, it is assumed that the first conductivity type in the above description is p-type, and the second conductivity type is n-type.

  A silicon oxide film 11 is formed with a thickness of about 15 nm on the surface of the p-type silicon semiconductor substrate 10, and a polysilicon film 12 is provided with a thickness of about 50 nm thereon by CVD (chemical vapor deposition). Thus, a silicon nitride film (SiN film) 13 is formed to a thickness of 200 nm. Thereafter, as shown in FIG. 3A, a first photoresist layer 14 is formed by coating and developing so as to cover a position to be a photodiode region. At this time, the side wall of the first photoresist layer 14 is substantially perpendicular to the silicon semiconductor substrate 10, and the top surface and the side wall of the first photoresist layer 14 are substantially perpendicular.

Thereafter, by processing in a nitrogen (N ₂ ) atmosphere at a temperature of 200 ° C. for 30 minutes, the sidewall of the first photoresist layer 14 is tapered as shown in FIG. To. In other words, the ridge portion formed by the top surface and the side wall of the first photoresist layer 14 is shaped by heat so that the first photoresist layer is formed in a certain range along the outer periphery of the first photoresist layer 14. The thickness of the first photoresist layer 14 is reduced in the direction leading to the outer periphery of the layer 14. Thus, after making the cross-sectional shape of the 1st photoresist layer 14 into a taper shape, UV curing is implemented by irradiating this with ultraviolet-ray (UV) in nitrogen atmosphere, and the 1st photoresist layer 14 is made Harden.

  Next, using a double coating method, as shown in FIG. 3C, the second photoresist layer 15 is formed on the substrate so that the element isolation region is formed at the opening. The side wall of the second photoresist layer 15 is substantially perpendicular to the substrate. Note that the reflow heat treatment is performed on the first photoresist layer 14 and then the UV curing is performed because the first photoresist layer 14 is dissolved in the development step of the second photoresist layer 15. This is to prevent it.

  Thereafter, the silicon nitride film 13, the polysilicon film 12, and the silicon oxide film 11 are etched using the first and second photoresist layers 14 and 15 as an etching barrier, and the silicon semiconductor substrate 10 is further etched. Since the side wall of the first photoresist layer 14 is tapered, as shown in FIG. 4A, the first photoresist layer 14 side along the first photoresist layer 14 side. A trench 21 having a tapered side wall is formed. The side wall of the trench 21 on the side in contact with the second photoresist layer 15 is substantially vertical. Further, a trench 22 having a box-shaped cross-sectional shape is formed in a portion surrounded only by the second photoresist layer 15. Thus, trenches 21 and 22 having a desired shape are formed. As for the trench 21 whose side wall is tapered, it is preferable to leave a flat portion with a width of at least about 200 nm in the deepest portion. This is because, in the subsequent gate oxide film forming step, if there is a portion where an acute angle is formed at the corner of the trench, stress concentrates on that portion and becomes a source of leakage current.

Next, the photoresist layers 14 and 15 are removed and washed, and an inner wall oxide film 16 is formed to a thickness of about 50 nm in a pyro atmosphere using a mixed gas of hydrogen (H ₂ ) and oxygen (O ₂ ) at 1100 ° C. To do. The state where the inner wall oxide film 16 is formed is shown in FIG.

Thereafter, as shown in FIG. 4C, a resist layer 17 is formed on the entire surface of the substrate except for the position of the trench 21 whose side wall is tapered. Using resist layer 17 as a mask, boron (B), which is a p-type impurity, is ion-implanted at an acceleration voltage of 20 to 30 keV and a dose of about ² to 10 × 10 ¹² / cm ² to form diffusion region 4 in a self-aligned manner. . The diffusion region 4 is uniformly provided under the deepest bottom surface of the trench 21 and the tapered side wall. Accordingly, ion implantation for forming the diffusion region 4 is performed in a self-aligned manner. Thereafter, the resist layer 17 is removed, and an oxide film is buried in the trenches 21 and 22 by using a general semiconductor device manufacturing process, thereby completing the element isolation regions 3 and 2 as shown in FIG.

  Further, the solid-state imaging device of the present embodiment is completed through ion implantation for forming the photodiode region and a process for forming a transistor in the transistor unit 7.

  As described above, the present invention has been described by taking the solid-state imaging device having the photodiode as an example, but the present invention is not limited to the solid-state imaging device. The present invention includes, for example, a first element portion that is relatively susceptible to the leakage current and a second element portion that is relatively less susceptible to the leakage current. The present invention can be applied to a semiconductor device in which elements are separated from the two element portions. In that case, as the element isolation region surrounding the first element portion, an element isolation region having a tapered side wall on the first element portion side is used, and a uniform diffusion region is further provided under the tapered side wall. What is necessary is just to provide. By separating the first element portion by the element isolation region in this way, the leakage current flowing through the first element portion can be reduced without reducing the effective area and volume of the first element portion. Can do.

It is sectional drawing which shows the structure of the principal part of the solid-state image sensor of one Embodiment of this invention. It is an equivalent circuit diagram of a unit cell. (A)-(C) are the figures explaining the manufacturing process of a solid-state image sensor. (A)-(C) are the figures explaining the manufacturing process of a solid-state image sensor. It is sectional drawing which shows the structure of the principal part of the conventional solid-state image sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st semiconductor layer 2, 3 Element isolation region 4 Diffusion region 5 Surface diffusion layer 6 2nd semiconductor layer (photodiode region)
7 Transistor portion 8 Photodiode portion 9 Channel stop region (element isolation diffusion layer)
DESCRIPTION OF SYMBOLS 10 Silicon semiconductor substrate 11 Silicon oxide film 12 Polysilicon film 13 Silicon nitride film 14 1st photoresist layer 15 2nd photoresist layer 16 Inner wall oxide film 17 Resist layer

Claims (8)

A photoelectric conversion unit including a first conductivity type first semiconductor region on a semiconductor substrate, and a second conductivity type second semiconductor region which forms a PN junction with the first semiconductor region and can store signal charges; In a solid-state imaging device having a semiconductor element different from the photoelectric conversion unit,
An element isolation region for isolating the photoelectric conversion unit from the semiconductor element;
The element isolation region includes a trench surrounding the photoelectric conversion unit, and an insulator embedded in the trench,
A solid-state imaging device, wherein a cross-sectional shape of a side wall of the trench on a side of the photoelectric conversion unit becomes tapered toward the photoelectric conversion unit side.   2. The solid-state imaging device according to claim 1, wherein a third semiconductor region of a first conductivity type is formed from the side wall to the semiconductor substrate side along the side wall having the tapered shape.   The solid-state imaging device according to claim 2, wherein the third semiconductor region is formed with a uniform impurity concentration and a uniform thickness.   3. The solid-state imaging device according to claim 1, comprising a plurality of the semiconductor elements, wherein element isolation between the semiconductor elements is performed by a second element isolation region having a box-shaped cross-sectional trench.   2. The solid-state imaging device according to claim 1, wherein a side wall of the trench on the semiconductor element side is perpendicular to a surface of the semiconductor substrate or has a taper angle smaller than a taper angle of the side wall on the photoelectric conversion unit side. . In a semiconductor device having, on a semiconductor substrate, a first element portion that is relatively susceptible to leakage current and a second element portion that is relatively less susceptible to leakage current.
An element isolation region for isolating the first element portion from the second element portion;
The element isolation region includes a trench surrounding the first element portion, and an insulator embedded in the trench,
The semiconductor device, wherein a cross-sectional shape of a side wall of the trench on the first element portion side has a tapered shape that becomes shallower toward the first element portion side. A first trench having a taper shape surrounding a first element portion on a surface of a semiconductor substrate and having a cross-sectional shape of a side wall on the first element portion side becoming shallower toward the first element portion; In the method for manufacturing a semiconductor device, the second trench having the cross-sectional shape of
Forming a first resist layer at a position corresponding to the first element portion on the surface of the semiconductor substrate, and performing a reflow heat treatment to deform the sidewall of the first resist layer into a tapered shape;
Curing the first resist layer;
After the step of curing the first resist layer, a second resist layer is formed on the surface of the semiconductor substrate so that a portion excluding the formation positions of the first trench and the second trench is covered with the resist. Forming, and
Etching the semiconductor substrate using the first resist layer and the second resist layer as a mask;
A method for manufacturing a semiconductor device, comprising:   After the step of etching the semiconductor device, ion implantation is performed in a self-aligned manner with respect to the first trench, and at least along the side wall having the tapered shape, a diffusion region from the side wall to the semiconductor substrate side The method of manufacturing a semiconductor device according to claim 7, further comprising:

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