JP2007311648A - Solid-state imaging device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a picture element cell in a solid-state imaging device with trench isolation without decreasing saturation and sensitivity characteristics of an imaging element while avoiding leakage current. <P>SOLUTION: The solid-state imaging device has a primary conductive semiconductor substrate 201, a secondary conductive well prepared in the semiconductor substrate 201, two or more primary conductive charge storage regions 208 prepared in the well, a trench structure 203 prepared in the well on whose inner wall a silicon oxide film 204 is formed, a secondary conductive failure inhibition layer 205 prepared close to the vicinity of the trench structure 203 or very close to it, and a primary conductive inversion layer 209 prepared between the failure inhibition layer 205 and the charge storage regions 208. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to a technique for miniaturizing a pixel cell constituting the solid-state imaging device.

  In recent years, the demand for higher pixels in solid-state imaging devices has been increasing. As a result of miniaturization of the pixel cells constituting the solid-state imaging device to meet this demand, it becomes difficult to separate the pixel cells by LOCOS (Local Oxidation of Silicon) separation, and instead, it is difficult to form a semiconductor substrate. A trench isolation (STI: Shallow Trench Isolation) in which a trench structure is formed and a silicon oxide film or a dielectric is embedded therein has come to be used. Trench isolation is a technique commonly used for fine pattern formation of 0.25 μm technology or less, and it is miniaturized because the dielectric can be embedded deeply inside the substrate compared to LOCOS isolation, so that the isolation distance can be increased. It is expected to be suitable for separating pixel cells.

However, when trench isolation is used, crystal defects are generated due to process damage during processing, stress of an oxide film formed on the inner surface of the trench structure, and embedded silicon insulator. This crystal defect becomes an electron generation recombination center, and when electrons generated by thermal excitation from the defect to the conduction band of the semiconductor enter the photodiode, image defects such as dark current and white scratches are caused. Therefore, a method of forming an impurity region of the opposite type to the photodiode (hereinafter simply referred to as “impurity region”) so as to cover a region where many defects near the side wall of the trench structure are generated is considered. (Patent Document 1). In this way, during the operation of the solid-state imaging device, the depletion layer extending from the photodiode can be prevented from spreading to the trench side wall having many defects, so that leakage current can be avoided, so that unnecessary charges do not enter the photodiode. Can be.
JP 2002-57319 A

  However, the present inventors have found through experiments that when the impurity region is formed in the vicinity of the side wall of the trench structure with isolation as described above, the saturation characteristics and sensitivity characteristics deteriorate. This problem is particularly noticeable when the pixel cell size is 2.2 μm square or less, which makes it difficult to realize a solid-state imaging device having a pixel cell size smaller than 2.2 μm square. .

  The present invention has been made in view of the above-described problems. In a solid-state imaging device having trench isolation, a pixel cell is formed without degrading the saturation characteristics and sensitivity characteristics of an imaging pixel while avoiding a leakage current. It is an object to provide a miniaturized solid-state imaging device and a method for manufacturing the same.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a first conductive type semiconductor substrate, a second conductive type well provided in the semiconductor substrate, and a first conductive type provided in the well. A plurality of conductivity type charge storage regions; a trench structure provided in the well and having a silicon oxide film formed on the inner wall thereof; and a second structure provided in the vicinity of or very close to the periphery of the trench structure. It is characterized by comprising a conductivity type defect suppression layer and a first conductivity type inversion layer provided between the defect suppression layer and the charge storage region.

  As described above, the inversion is performed by providing an inversion layer having a conductivity type different from that of the defect suppression layer between the charge accumulation region that is a photodiode and the defect suppression layer that is an impurity region provided around the trench structure. It is possible to avoid the reduction of the charge accumulation region that occurs when the layer is not provided. For this reason, the pixel cell of the solid-state imaging device can be miniaturized without being accompanied by a decrease in the saturation characteristic or sensitivity characteristic of the photodiode due to the reduction of the charge accumulation region.

  In this case, the impurity concentration of the second conductivity type forming the defect suppression layer is higher than the impurity concentration of the well of the second conductivity type, and the impurity concentration of the first conductivity type forming the inversion layer is It is more preferable to make the concentration higher than the impurity concentration of the charge storage region.

  In addition, it is preferable that the defect suppression layer and the inversion layer are not provided around the trench structure that is not adjacent to the charge accumulation region. By doing so, the narrow channel characteristics of the transistor can be prevented from being deteriorated.

  Furthermore, it is preferable that a channel stopper region of a second conductivity type is formed at a boundary portion between the element isolation channel stopper layer formed below the trench structure and the charge storage region and the bottom of the inversion layer. By doing so, it is possible to more reliably separate adjacent charge storage regions.

  The method for manufacturing a solid-state imaging device according to the present invention includes a first step of forming a second conductivity type well on a first conductivity type silicon substrate, a second step of forming a trench structure in the well, A third step of forming a silicon oxide film on the inner wall of the trench structure; a fourth step of forming a second conductivity type defect suppression layer around the trench structure; and a first conductivity type around the defect suppression layer. And a sixth step of forming a charge accumulation region of the first conductivity type in a region between the trench structures.

  More specifically, in the second step, after forming a silicon oxide film and a silicon nitride film on the silicon substrate, the trench structure is formed by etching using a patterned resist layer. In the third step, a silicon oxide film is formed on the inner wall of the trench structure by thermal oxidation. In the fourth step, the defect suppression layer is formed by ion implantation of a second conductivity type impurity. In the fifth step, the inversion layer is formed by ion implantation of impurities of the first conductivity type, and the sixth step uses a resist patterned for each pixel. Preferably, the charge accumulation region is formed by ion implantation of a first conductivity type impurity.

  By doing in this way, the solid-state imaging device concerning the present invention can be formed easily.

  Further, the ion implantation in the fourth step and the fifth step is performed in a self-aligned manner using the trench structure, and the formation of the inversion layer in the fifth step is performed as described above. It is preferable that the impurity is formed by ion implantation of an impurity having a concentration twice or more that of the impurity implanted at the time of forming the charge storage region in the sixth step.

  Further, in the fourth and fifth steps, the periphery of the trench structure that is not adjacent to the charge storage region is covered with a resist, and the defect suppression layer and the inversion are formed around the trench structure that is not adjacent to the charge storage region. It is preferred not to provide a layer.

  Further, after the sixth step, an element isolation channel stopper layer is formed below the trench structure and the electric charge storage region, and a boundary portion between the element isolation channel stopper layer and the bottom of the inversion layer is It is desirable to have a seventh step of forming a two-conductivity type channel stopper region.

  In addition, the seventh step is to deeply implant a second conductivity type impurity in the vertical direction at the bottom of the trench structure to form the channel stopper region, and the ion implantation in the seventh step includes: More preferably, the trench structure is used in a self-aligned manner.

  According to the solid-state imaging device and the manufacturing method thereof according to the present invention, in the solid-state imaging device having trench isolation, the solid-state imaging in which the pixel cell is miniaturized without reducing the saturation characteristic and the sensitivity characteristic of the imaging pixel while avoiding the leakage current. An apparatus and a manufacturing method thereof can be provided.

  Embodiments of a solid-state imaging device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

(Embodiment 1)
First, the overall configuration of the solid-state imaging device according to the present invention will be described.

  FIG. 1 is a circuit diagram illustrating an outline of a configuration of a solid-state imaging device.

  As shown in FIG. 1, the solid-state imaging device 1 includes a plurality of pixel cells 101, a vertical scanning circuit 102, a horizontal scanning circuit 103, a horizontal switch element 104, and an amplifier 105, which are read pulse lines 106 and vertical selection lines 107. The vertical signal line 108 and the horizontal signal line 109 are connected. Each pixel cell 101 includes a vertical selection switch element 110, a readout switch element 111, and a photoelectric conversion element 112, and the cell size is 2.2 μm square. The pixel cells 101 are arranged in a matrix to form an imaging area.

  The pixel cells 101 arranged in a matrix share a vertical selection line 107 for each row, and a control electrode of the vertical selection switch element 110 is connected to the vertical selection line 107. The vertical scanning circuit 102 inputs a vertical scanning pulse to the control electrode of the vertical selection switch element 110 via the vertical selection line 107.

  The pixel cell 101 shares a vertical signal line 108 for each column of the matrix, and one main electrode of the readout switch element 111 is connected to the vertical signal line 108. The other main electrode of the read switch element 111 is connected to the photoelectric conversion element 112 which is a photodiode.

  Further, the pixel cell 101 shares a read pulse line 106 for each column of the matrix, and the main electrode of the vertical selection switch element 110 is connected to the read pulse line 106. The other main electrode of the vertical selection switch element 110 is connected to the control electrode of the read switch element 111.

  One main electrode of the horizontal switch element 104 is connected to the vertical signal line 108, and the other main electrode is connected to the horizontal signal line 109. A horizontal scanning pulse is input from the horizontal scanning circuit 103 to the control electrode of the horizontal switch element 104. The amplifier 105 amplifies the signal charge of the horizontal signal line 109 and outputs it.

  When a vertical scanning pulse is input from the vertical scanning circuit 102 and a reading pulse is input from the horizontal scanning circuit 103, the vertical selection switch element 110 inputs the product pulse to the control electrode of the reading switch element 111. The signal charge obtained by photoelectric conversion by the photoelectric conversion element 112 is output to the vertical signal line 108. When the horizontal scanning circuit 103 inputs a horizontal scanning pulse to the horizontal switch element 104 and a horizontal reading pulse to the reading pulse line 106, the signal charge output to the vertical signal line 108 is transmitted to the horizontal signal line 109, and the amplifier Amplified at 105 and output.

  Although the solid-state imaging device having a general configuration has been described here, it is needless to say that the configuration of the solid-state imaging device of the present invention is not limited to the above, and other configurations may be used.

  Next, a detailed configuration of the pixel cell 101 of the solid-state imaging device 1 of the present embodiment will be described.

  FIG. 2 is a schematic cross-sectional view illustrating the configuration of the imaging region of the solid-state imaging device 1 according to the first embodiment, that is, the vicinity of the photodiode 208 in the pixel cell 101. As shown in FIG. 2, a trench structure (trench groove) 203 is formed on a silicon substrate 201, which is a semiconductor substrate, for isolating an element adjacent to the photodiode 208. In the silicon substrate 201, a P-type well of the second conductivity type is formed on an N-type semiconductor substrate of the first conductivity type here. In FIG. 2, only the P-type well portion is shown, and the N-type substrate portion is not shown.

  The photodiode 208 is made of an N-type semiconductor layer of a first conductivity type, and a shield layer 214 is provided on the surface of the photodiode 208 on the silicon substrate 201 side. The photodiode 208 is a so-called embedded photodiode and constitutes the photoelectric conversion element 112 in the pixel cell 101. By using the embedded photodiode in this manner, the photodiode 208 is shielded from defects on the surface of the silicon substrate 201, so that leakage current due to defects on the surface of the silicon substrate 201 can be prevented. The size of the photodiode 208 is 1.7 μm × 1.1 μm in plan view.

  The trench structure 203 has a liner oxide film 204 formed on the inner wall surface thereof, and is further filled with a buried layer formed by depositing silicon oxide. The trench structure 203 separates adjacent pixel cells or circuit elements formed on the silicon substrate surface. The trench structure 203 has a width of 0.35 μm and a depth of 0.3 μm.

  Around the trench structure 203, a defect suppression layer 205 made of a P-type semiconductor layer of the second conductivity type is formed. Thus, by forming the defect suppression layer 205 made of a P-type semiconductor around the trench structure 203, the following effects are produced.

  As will be described later, since the trench structure 203 is formed by dry etching, the silicon substrate 201 is damaged by etching plasma. Further, since the liner oxide film 204 on the inner wall surface of the trench structure 203 is formed by thermal oxidation, a stress is generated between the liner oxide film 204 and the silicon substrate 201. As a result, when a lattice defect occurs in the silicon substrate 201 around the trench structure 203, electric charges are generated from the lattice defect due to thermal excitation and enter the photodiode 208, generating a false signal and degrading the image quality. There is. Here, by forming the defect suppression layer 205 of the P-type semiconductor layer around the trench structure 203, it is possible to prevent the above-described electrons from being combined with holes and entering the photodiode 208. In order to sufficiently exhibit this effect, the defect suppression layer 205 is formed so as to cover a defect existing region in a range of about 50 nm from the trench structure.

The impurity concentration of the defect suppression layer 205 is preferably higher than the impurity concentration of the P-type semiconductor well that forms the silicon substrate. Specifically, the impurity concentration of the defect suppression layer 205 is about 5E17 [/ m ³ ], and the impurity concentration of the P-type semiconductor well is about 1E17 [/ m ³ ]. By setting the impurity concentration higher than that, the depletion layer hardly extends to the trench structure 203 side in the defect suppression layer 205, so that defects on the surface of the trench structure can be electrically inactivated.

  An inversion layer 209 made of an N-type semiconductor that is the first conductivity type is formed around the defect suppression layer 205. By forming the inversion layer 209 of the first conductivity type in this way, it is possible to prevent the effective area of the photodiode 208 from being reduced.

  As described above, the defect suppression layer 205 is preferably formed of a dense P-type semiconductor layer in consideration of its effect, but is included in the defect suppression layer 205 by various heat treatment steps in the manufacturing process of the solid-state imaging device 1. It is conceivable that P-type impurities diffuse into the photodiode 208 by thermal diffusion. As a result, a phenomenon occurs in which the effective area of the photodiode 208 that is an N-type semiconductor layer is reduced, and the number of charges that can be accumulated in the photodiode 208 is reduced, resulting in a problem that image quality is deteriorated.

  This problem becomes prominent when the distance between the trench structure 203 and the photodiode 208 is narrowed, particularly when the pixel cell size is 2.2 μm square as in this embodiment or smaller. However, by providing the inversion layer 209 as in the present embodiment, a solid-state imaging device with smaller pixel cells can be realized.

From such an effect, it is desirable that the impurity concentration of the inversion layer 209 is higher than the impurity concentration of the N-type semiconductor forming the photodiode 208. Specifically, the inversion layer 209 has an impurity concentration of about 1 to 5E12 [/ m ³ ] and the photodiode 208 has an impurity concentration of about 1 to 5E11 [/ m ³ ]. By setting the impurity concentration higher than the impurity concentration, the potential of the photodiode 208 can be increased in the horizontal direction, so that the number of electrons that can be accumulated in the photodiode 208 can be increased.

  FIG. 9 shows an impurity profile when the inversion layer 209 is a thick N-type semiconductor layer as described above. From the profile of FIG. 9, it can be seen that the N-type region constituting the photodiode 208 is formed to extend toward the trench structure 203 compared to the profile when the inversion layer 209 shown in FIG. 10 is not formed. . As is apparent from the result of the impurity profile, it can be seen that the provision of the inversion layer 209 can prevent the effective area of the photodiode 208 from being reduced as compared with the original area due to miniaturization.

  Since the configuration other than the above is the same as that of a normal solid-state imaging device, it will be briefly described.

  The first to third read control layers 207, 210, and 211 in the P-type region are in the vicinity of the photodiode 208 as a read control layer that determines the threshold value of the transfer gate that transfers carriers of the photodiode 208 to the drain layer 215. Formed. These together with the gate oxide film 212, the gate electrode 213, and the drain layer 215 constitute the read switch element 111.

  A wiring 217 is a wiring for reading out charges accumulated in the photodiode 208. The interlayer insulating film 216 is an insulating member having high translucency with respect to visible light. The light shielding film 218 shields the incident light from entering the photodiodes 208 other than the photodiode 208 that should be incident. The channel stopper layer 220 is a channel stopper for trench element isolation, and separates adjacent elements. The protective film 218 protects the surface of the solid-state image sensor 1.

  As described above, the structure of the solid-state imaging device of the present embodiment has been described for the pixel portion that forms the photodiode 208 that is the charge storage region. However, the pixel portion is formed in the peripheral circuit portion that does not form the photodiode 208 around the pixel portion. For the trench structure 203 that is not adjacent to the charge storage region, it is desirable to make the surrounding structure different from that of the pixel portion. In the peripheral circuit portion, since there is no problem that unnecessary charges generated by providing the trench structure 203 like the pixel portion enter the photodiode and the image quality deteriorates, the defect suppression layer 205 and the inversion layer 209 are unnecessary. Because it becomes. Rather, by not forming the defect suppression layer 205 and the inversion layer 209 around the trench structure 203 in the peripheral circuit portion, the peripheral circuit operates normally without degrading the narrow channel characteristics of the transistor formed as the peripheral circuit. be able to.

  Next, the manufacturing process of the solid-state imaging device 1 described above will be described.

  3 to 8 are schematic cross-sectional views illustrating manufacturing steps of the solid-state imaging device 1 according to the present embodiment.

  First, a P-type well, which is a second conductivity type, is formed on an N-type semiconductor substrate, which is a first conductivity type, to form a silicon substrate 201 (first step, not shown).

  Next, as shown in FIG. 3A, an oxide film 202, which is a base silicon oxide film, is formed on the silicon substrate 201 by thermal oxidation, and low pressure chemical vapor deposition (LPCVD) is performed on the oxide film 202. A nitride film 301 that is a silicon nitride film is formed by low pressure chemical vapor deposition. The film thickness of the oxide film 202 is 10 nm, and the film thickness of the nitride film 301 is 150 nm. In the low-pressure chemical vapor deposition method, one to several kinds of compound gas containing a constituent element of a thin film to be formed or a simple substance gas is supplied onto a heated wafer under a reduced pressure of about 0.1 to 10 Torr. This is a method of growing a thin film by reaction.

  Thereafter, as shown in FIG. 3B, a resist agent is applied onto the nitride film 301, heat-treated (pre-baked), exposed using an exposure apparatus such as a stepper, developed with a resist with an organic solvent, and the like again. A patterned resist 302 is formed by heat treatment (post-bake). Then, a portion of the nitride film 301, the oxide film 202, and the silicon substrate 201 that is not covered with the resist 302 is excavated by an etching process to form a trench structure 203 (second step). In this case, the etching process may be dry etching or wet etching.

  Next, as shown in FIG. 3C, after removing the resist 302, the inner wall of the trench structure 203 is thermally oxidized by heat treatment to form a thin liner oxide film 204 (third step). The film thickness of the liner oxide film 204 is 15 nm.

Next, as shown in FIG. 4 (a), boron (B) is implanted at an acceleration energy of 30 keV and at an inclination angle of 25 degrees with respect to the normal of the surface of the silicon substrate 201 in four directions by 8.0 × 10 ¹² ions / cm ^2. Are sequentially implanted to form the defect suppression layer 205 (fourth step). Here, sequentially implanting from four directions means that ions are implanted while being rotated by 90 degrees with respect to the main surface of the silicon substrate 201 while maintaining the tilt angle of the implanted ions. In this way, since there is no “dark” part where ions are not implanted into the surface of the silicon substrate 201, the defect suppression layer 205 can be formed around the entire wall surface of the trench structure 203.

Thereafter, as shown in FIG. 4 (b), arsenic (As) is ion-implanted sequentially from four directions at an implantation energy of 5.0 × 10 ¹¹ ions / cm ² at an acceleration energy of 600 KeV and an inclination angle of 25 degrees to obtain a high concentration. The inversion layer 209 which is the N-type region is formed (fifth step).

  Here, the concentration of the impurity to be implanted is set higher than the impurity concentration to be implanted when the photodiode 208 which is a charge storage region to be formed later as a region of the same conductivity type is formed. In particular, the impurity concentration at the time of implantation is preferably doubled or more. In this manner, by setting the impurity concentration when forming the inversion layer 209 to be higher than the impurity concentration when forming the photodiode 208, in particular, by setting the impurity concentration to be twice or more, the potential of the photodiode is laterally increased. Since the number of electrons that can be stored in the photodiode 208 can be increased, the effect can be increased.

  In addition, after the trench structure 203 is formed, both the defect suppression layer 205 and the inversion layer 209 are self-aligned with the trench structure 203 by adopting a method of sequentially implanting impurities from four directions at a predetermined inclination angle. Can be formed. In particular, the inversion layer 209 has a great advantage in that it is not necessary to consider the overlay variation due to mask alignment compared to the method of performing ion implantation by resist patterning, and the process variation can be reduced.

  Up to this point, the method for forming the defect suppression layer 205 and the inversion layer 209 in the vicinity of the trench structure 203 of the pixel portion where the photodiode 208 serving as the charge storage region is formed has been described. However, it is not necessary to form the defect suppression layer 205 and the inversion layer 209 around the trench structure 203 that is not adjacent to the charge storage region in the peripheral circuit portion formed around the pixel portion. Therefore, in the fourth and fifth steps of forming the defect suppression layer 205 and the inversion layer 209 around the trench structure 203 of the pixel portion, a resist film is applied to the entire peripheral circuit region including the nitride film 301 and the periphery thereof. The trench structure 203 of the circuit part is covered. By doing so, the defect suppression layer 205 and the inversion layer 209 are not formed around the trench structure 203 located in the peripheral circuit portion and not adjacent to the charge accumulation region, so that the narrow channel characteristics of the transistor are deteriorated. Therefore, the peripheral circuit can be operated normally.

  As described above, after forming two types of trench structures 203 having different peripheral structures in the pixel portion and the peripheral circuit portion, silicon oxide is deposited on the entire surface of the silicon substrate 201 to form the buried layer 206. Then, the silicon oxide other than the buried layer 206 is removed by using a chemical mechanical polishing (CMP) to planarize the surface as shown in FIG.

Further, as shown in FIG. 4D, the nitride film 301 is removed, and as shown in FIG. 5A, boron is implanted at an acceleration energy of 10 keV by an ion implantation amount of 1.0 × 10 ¹² ions / cm ^2. Thus, the first read control layer 207 is formed.

Thereafter, as shown in FIG. 5B, a resist film is applied on the oxide film 202 and the buried layer 206 to form a resist 501 patterned by a normal exposure and development operation, and then arsenic (As) is accelerated. Ions are implanted at an energy of 600 keV and an implantation amount of 1.0 × 10 ¹² ions / cm ² to form a photodiode 208 which is a charge storage region (sixth step).

After removing the resist 501, a patterned resist 601 is formed as shown in FIG. 6A. First, boron is ion-implanted with an acceleration energy of 300 keV and an implantation amount of 4.0 × 10 ¹¹ ions / cm ^2. Thus, the second read control layer 210 is formed. Next, boron is similarly ion-implanted at an acceleration energy of 100 keV and an implantation amount of 8.0 × 10 ¹¹ ions / cm ² to form the third read control layer 211.

After the resist 601 is removed, boron is ion-implanted with an acceleration energy of 120 KeV and an implantation amount of 6.0 × 10 ¹² ions / cm ² to form an element isolation channel stopper layer 220 as shown in FIG. 6B.

  The oxide film 202 is removed by an etching process to expose the first read control layer 207. Then, a gate oxide film 212 and a gate electrode 213 are sequentially formed on the exposed portion of the first read control layer 207 as shown in FIG. 7A.

Next, as shown in FIG. 7B, after a patterned resist 603 is formed, boron is ion-implanted with an acceleration energy of 6 keV and an implantation amount of 1.0 × 10 ¹⁴ ions / cm ² , thereby forming a shield layer 214. Form.

After removing the resist 603, a patterned resist 702 is formed as shown in FIG. 8A, and phosphorus (P) ions are implanted at an acceleration energy of 50 keV and an implantation amount of 4.0 × 10 ¹³ ions / cm ^2. Then, boron is further ion-implanted at an acceleration energy of 30 keV and an implantation amount of 2.0 × 10 ¹² ions / cm ² to form the drain layer 215.

  Then, after removing the resist 702, as shown in FIG. 8B, an interlayer insulating film 216, a wiring 217, a light shielding film 218, and a protective film 219 are formed in a wiring process.

In this way, the solid-state imaging device 1 according to the present embodiment is manufactured.
(Second Embodiment)
Another embodiment of the solid-state imaging device 1 according to the present invention will be described.

  FIG. 11 is a schematic cross-sectional view illustrating a configuration of an imaging region of the solid-state imaging device according to the second embodiment.

  The basic configuration of the solid-state imaging device according to the second embodiment is the same as that of the solid-state imaging device according to the first embodiment described above. To simplify.

  That is, a photodiode 208 which is a charge storage region and a trench structure 203 are formed on a silicon substrate 201, a P-type well is formed on an N-type semiconductor substrate, and the trench structure 203 The liner oxide film 204 is formed on the inner wall, the defect suppression layer 205 and the inversion layer 209 are formed around the trench structure 203, and their conductivity types are the same as those in the first embodiment. Further, the photodiode is 1.7 μm × 1.1 μm in plan view, and the trench structure 203 has a width of 0.35 μm and a depth of 0.3 μm.

  The first to third read control layers 207, 210 and 211, the gate oxide film 212, the gate electrode 213, the drain layer 215 and the like are formed in the vicinity of the photodiode 208 to constitute the read switch element 111. The same applies to the other wiring 217, the interlayer insulating film 216, and the light shielding film 218.

  In the present embodiment, the device isolation channel stopper layer 220 formed in the lower silicon substrate 201 in which the regions constituting the photodiode 208 and the trench structure 203 and the readout switch element 111 as charge storage regions are formed. And a P-type channel stopper region 221 of the second conductivity type is formed in the vicinity of a boundary portion between the trench structure 203 and the inversion layer 209 formed around the trench structure 203. .

  In the present invention, since the defect suppression layer 205 formed around the trench structure 203 in order to prevent the occurrence of unnecessary leakage current has a conductivity type different from that of the photodiode, the photodiode is subjected to the heat treatment process of the substrate. The inversion layer 209 having the same conductivity type as that of the photodiode is provided between the defect suppression layer 205 and the photodiode 208 in order to reduce the effective region and prevent the charge storage effect from being reduced. And However, in this case, only the element isolation channel stopper layer 220 for isolation of the trench element that is normally formed may cause element isolation leak or decrease the breakdown voltage. In such a case, the channel stopper region 221 of the second conductivity type, which is different from the conductivity type of the photodiode 208 shown in the second embodiment, is a boundary portion between the inversion layer 209 and the element isolation channel stopper layer 220. By forming it in the vicinity, it is possible to prevent a decrease in element isolation performance.

  Next, a manufacturing method of the solid-state imaging device shown as the second embodiment will be described.

  As described above, the solid-state imaging device according to the second embodiment has the second conductivity type P in the vicinity of the boundary between the element isolation channel stopper layer 220 and the inversion layer 209 formed around the trench structure 203. The difference from the first embodiment is that a channel stopper region 221 of a mold is formed. For this reason, here, the formation of the channel stopper region 221 will be mainly described.

  FIG. 12 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the second embodiment. FIG. 12A shows a stage in which the defect suppression layer 205 and the inversion layer 209 are formed in the trench structure 203 adjacent to the photodiode 208 which is a charge storage region so as to be self-aligned therewith. It is the same as that of FIG.4 (b) explaining the manufacturing method of the solid-state image sensor which concerns on Embodiment 1. FIG.

In the method of manufacturing the solid-state imaging device according to the second embodiment, boron (B) is implanted into the inner surface of the trench 203 in four directions at an acceleration energy of 30 keV and an implantation amount of 8.0 × 10 ¹² ions / cm ² at an inclination angle of 25 degrees. Then, after forming the defect suppression layer 205, arsenic (As) is ion-implanted sequentially from four directions at an acceleration energy of 600 Kev and an inclination angle of 25 degrees in increments of 5.0 × 10 ¹¹ ons / cm ^2. Thus, the inversion layer 209 is formed as shown in FIG.

After the defect suppression layer 205 and the inversion layer 209 are formed in a self-aligned manner with respect to the trench structure 203 in this way, boron (B) is accelerated at an energy of 120 to 150 KeV and an inclination angle as shown in FIG. An ion implantation amount of 6.0 × 10 ¹² ions / cm ² is ion-implanted at 0 degree to form a channel stopper region 221 (seventh step).

  At this time, in order to prevent boron (B) ions from being implanted into the active region other than the bottom of the trench structure 203 that forms the channel stopper region 221, the nitridation of the silicon substrate 201 is more than the sum of Rp and ΔRp for ion implantation. Note that the film 301 is formed thick. For example, if the acceleration energy of boron (B) described above is 120 to 150 KeV, 200 nm or more may be deposited as the nitride film 203. In this way, by forming the nitride film 301 thick in a region where boron (B) ions are not desired to be implanted, the channel stopper region 221 can be formed in a self-aligned manner by trench isolation. Compared to implantation, it is not necessary to consider overlay variation due to mask alignment, and process variations can be reduced.

  After this, the formation of the buried layer 206 may be performed by the same method as described for the method of manufacturing the solid-state imaging device of the first embodiment, and FIG. 4C and the subsequent drawings are shown as FIGS. The solid-state imaging device according to the second embodiment can be formed through the steps described above.

  As described above, the present invention has been described based on the embodiment. However, the present invention is not limited to the above-described embodiment, and the following modifications can be implemented.

  For example, in the above embodiment, the size of the pixel cell is 2.2 μm square, but it is needless to say that the present invention is not limited to this, and may have a size other than 2.2 μm square. In particular, when the pixel cell size is smaller than a 2.2 μm square, such as a 1.5 μm square, the application of the present invention allows a pixel cell with a very small size that is not accompanied by a decrease in saturation characteristics or sensitivity characteristics. A solid-state imaging device can be obtained. In addition, the size of the photodiode 208 and the trench structure 203 is naturally designed to be different from the above-described embodiment depending on the size of the pixel cell.

  Further, in each of the above-described embodiments, the case where the N type is used as the first conductivity type and the P type is used as the second conductivity type has been described, but the case where the two conductivity types are inverted is used. That is, even when a P-type semiconductor is used as the first conductivity type and an N-type semiconductor is used as the second conductivity type, the above-described effects of the present invention are similarly exhibited.

  In addition, regarding the trench structure 203, in each of the above embodiments, only the pixel portion and the peripheral circuit portion have different peripheral configurations, but the distance between the trench structure and the circuit element in the peripheral circuit portion is somewhat. In the case where the peripheral circuit element is not particularly adversely affected such as when it is large, the defect suppression layer 205 and the inversion layer 209 may be provided for all the trench structures.

  Furthermore, in the description of the above embodiment, only the case where the silicon oxide buried layer 206 is provided in the trench structure 203 has been described. However, the present invention is not limited to this, and the trench structure can be used as long as the element isolation function can be exhibited. The presence or absence of the embedded material and the type thereof are not limited to the above description.

  The solid-state imaging device and the manufacturing method thereof according to the present invention are useful as a technique for miniaturizing a pixel cell without reducing saturation characteristics and sensitivity characteristics in the solid-state imaging device.

It is a circuit diagram which shows the outline of a structure of the solid-state imaging device concerning embodiment of this invention. It is a schematic cross section which shows the structure in the imaging region of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a schematic cross section which shows the manufacturing process of the solid-state imaging device which concerns on the 1st Embodiment of this invention. FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention and subsequent to FIG. 3. FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention and subsequent to FIG. 4. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention and subsequent to FIG. 5. FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention and subsequent to FIG. 6. FIG. 8 is a schematic cross-sectional view illustrating a manufacturing process of the solid-state imaging device according to the first embodiment of the present invention and subsequent to FIG. 7. It is a figure which shows the distribution state of the impurity in the pixel part containing the trench structure of the solid-state imaging device which concerns on the 1st Embodiment of this invention. It is a figure which shows the distribution state of the impurity in the pixel part of the solid-state imaging device which concerns on a prior art. It is a schematic cross section which shows the structure in the imaging region of the solid-state imaging device which concerns on the 2nd Embodiment of this invention. It is a schematic cross section which shows the manufacturing process of the solid-state imaging device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state imaging device 101 Pixel cell 102 Vertical scanning circuit 103 Horizontal scanning circuit 104 Horizontal switch element 105 Amplifier 106 Read pulse line 107 Vertical selection line 108 Vertical signal line 109 Horizontal signal line 110 Vertical selection switch element 111 Read switch element 112 Photoelectric Conversion element 201 Silicon substrate 202 Oxide film 203 Trench structure 204 Liner oxide film 205 Defect suppression layer 207, 210, 211 Read control layer 208 Photodiode 209 Inversion layer 212 Gate oxide film 213 Gate electrode 214 Shield layer 215 Drain layer 216 Interlayer insulating film 217 Wiring 218 Light shielding film 219 Protective film 220 Element isolation channel stopper layer 221 Channel stopper region

Claims (12)

A first conductivity type semiconductor substrate;
A second conductivity type well provided in the semiconductor substrate;
A plurality of charge storage regions of a first conductivity type provided in the well;
A trench structure provided in the well and having a silicon oxide film formed on the inner wall thereof;
A defect-conducting layer of a second conductivity type provided near or in the vicinity of the periphery of the trench structure;
A solid-state imaging device comprising: a first conductivity type inversion layer provided between the charge suppression region around the defect suppression layer.   The impurity concentration of the second conductivity type forming the defect suppression layer is higher than the impurity concentration of the well of the second conductivity type, and the impurity concentration of the first conductivity type forming the inversion layer is the concentration of the charge storage region. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is higher than the impurity concentration.   The solid-state imaging device according to claim 1, wherein the defect suppression layer and the inversion layer are not provided around the trench structure that is not adjacent to the charge storage region.   A channel stopper region of a second conductivity type is formed at a boundary portion between an element isolation channel stopper layer formed below the trench structure and the charge storage region and a bottom portion of the inversion layer. Item 3. The solid-state imaging device according to Items 1 to 3. A first step of forming a second conductivity type well on a first conductivity type silicon substrate;
A second step of forming a trench structure in the well;
A third step of forming a silicon oxide film on the inner wall of the trench structure;
A fourth step of forming a second conductivity type defect suppression layer around the trench structure;
A fifth step of forming a first conductivity type inversion layer around the defect suppression layer;
And a sixth step of forming a first conductivity type charge storage region in a region between the trench structures. In the second step, after forming a silicon oxide film and a silicon nitride film on the silicon substrate, the trench structure is formed by etching using a patterned resist layer,
In the third step, a silicon oxide film is formed on the inner wall of the trench structure by thermal oxidation.
In the fourth step, the defect suppression layer is formed by ion implantation of a second conductivity type impurity.
In the fifth step, the inversion layer is formed by ion implantation of a first conductivity type impurity.
6. The solid-state imaging device according to claim 5, wherein in the sixth step, the charge accumulation region is formed by ion-implanting a first conductivity type impurity using a resist patterned for each pixel. Production method.   7. The method of manufacturing a solid-state imaging device according to claim 6, wherein the ion implantation in the fourth step and the fifth step is performed in a self-aligned manner using the trench structure.   The inversion layer of the fifth step is formed by ion implantation of an impurity having a concentration twice or more that of the impurity implanted at the time of forming the charge storage region of the sixth step. Item 8. A method for producing a solid-state imaging device according to Item 5-7.   In the fourth and fifth steps, the periphery of the trench structure not adjacent to the charge storage region is covered with a resist, and the defect suppression layer and the inversion layer are provided around the trench structure not adjacent to the charge storage region. The manufacturing method of the solid-state imaging device of Claims 5-8 which are not provided.   After the sixth step, an element isolation channel stopper layer is formed below the trench structure and the charge storage region, and a second conductivity type is formed at a boundary portion between the element isolation channel stopper layer and the bottom of the inversion layer. The manufacturing method of the solid-state imaging device according to claim 5, further comprising a seventh step of forming the channel stopper region.   11. The method of manufacturing a solid-state imaging device according to claim 10, wherein in the seventh step, the channel stopper region is formed by deeply ion-implanting a second conductivity type impurity in the vertical direction at the bottom of the trench structure.   The method of manufacturing a solid-state imaging device according to claim 11, wherein the ion implantation in the seventh step is performed in a self-aligned manner using the trench structure.

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