JP4174468B2 - Photoelectric conversion device and imaging system - Google Patents

Description

The present invention relates to a photoelectric conversion device and an imaging system , and more particularly to a CMOS area sensor and an imaging system .

  Conventionally, a CCD is known as a solid-state imaging device that converts an image signal into an electrical signal. This CCD has a photodiode array, and a pulse voltage is applied to the electric charge accumulated in each photodiode to read it out as an electric signal. In recent years, a CMOS area sensor in which a photodiode and a peripheral circuit including a MOS transistor are integrated into one chip is used as a solid-state imaging device. The CMOS area sensor has advantages such as lower power consumption and lower driving power than the CCD, and future demand expansion is expected.

  A CMOS area sensor will be described with reference to FIG. 9 as a typical example of the photoelectric conversion device. The cross-sectional schematic diagram of the photodiode part 301 and the transfer MOS transistor part 302 of a CMOS area sensor is shown. 303 is an N-type silicon substrate, 304 is a P-type well, 307 is a gate electrode of a transfer MOS transistor, 308 is an N-type charge storage region of the photodiode, 309 is a surface P-type region for embedding the photodiode, 305 Is a field oxide film for element isolation, and 310 is an N-type high concentration region which forms a floating diffusion and functions as the drain region of the transfer MOS transistor.

  311 is a silicon oxide film that insulates the gate electrode from the first wiring layer, 312 is a contact plug, 313 is the first wiring layer, 314 is an interlayer insulating film that insulates the first wiring layer and the second wiring layer, Reference numeral 315 denotes a second wiring layer, 316 denotes an interlayer insulating film that insulates the second wiring layer and the third wiring layer, 317 denotes a third wiring layer, and 318 denotes a passivation film. A color filter layer (not shown) is formed on the passivation film 318, and a microlens for improving sensitivity is formed. Light incident from the surface enters the photodiode through an opening defined by the third wiring layer 317. The light is absorbed in the N-type charge storage region 308 or the P-type well 304 of the photodiode to generate electron / hole pairs. Among these, electrons are stored in the N-type charge storage region 308.

As a conventional technology of a CMOS area sensor, for example, there is a structure having a carrier profile as shown in FIG. 10 (FIG. 6 of Patent Document 1) described in Patent Document 1. This structure has an impurity diffusion region 6A having a high concentration in a deep region in the substrate, and is considered to have an effect of increasing the efficiency of extracting charges generated by the light absorbed in the well to the surface side and improving the sensitivity.
US Pat. No. 6,483,129

  In a conventional photoelectric conversion device, particularly a CMOS area sensor, the well layer of the photodiode is formed by performing thermal diffusion after ion implantation. Therefore, as shown in FIG. The concentration distribution in the vertical direction gradually decreased. As a result, the structure does not have a potential barrier in the substrate depth direction, and a part of the light absorbed in the P-type well is lost in the substrate direction and thus does not contribute as a photoelectric conversion signal. In particular, as the pixel size becomes smaller, a problem has arisen that the required sensitivity cannot be obtained. In addition, since there are few parameters for manufacturing conditions that can be handled when controlling various characteristics such as sensitivity, the number of saturated charges, and transfer from a photodiode to a floating diffusion, there is a problem that these performances cannot be satisfied.

  On the other hand, the structure shown in FIG. 10 of the above-mentioned patent document has an impurity diffusion region having a high concentration in a deep region in the substrate and is considered to be effective in improving sensitivity. Since there are few parameters for manufacturing conditions that can be handled when controlling various characteristics such as transfer from a photodiode to a floating diffusion, there is a problem that these performances cannot be satisfied. In addition, in the simple retrograde well structure as described in Patent Document 1 described above, dark current generated in the substrate leaks into the photodiode and deteriorates the performance of the sensor. That is, until now, no technical problem has been found to achieve both improvement in sensitivity, saturation charge number, and transfer efficiency.

The present invention has been made to solve the above-described problems, and provides a photoelectric conversion device and an imaging system typified by a CMOS area sensor that improve various characteristics including sensitivity of a photodiode.

According to an aspect of the present invention, a photoelectric conversion element including a first conductivity type impurity region and a plurality of second conductivity type impurity regions is disposed on a first conductivity type semiconductor substrate. In the conversion device, the plurality of impurity regions of the second conductivity type are disposed below the impurity regions of the first conductivity type, and at least the first impurity region, the first impurity region, and the A second impurity region disposed between the impurity region of the first conductivity type, a third impurity region disposed between the second impurity region and the impurity region of the first conductivity type, Including
The concentration C1 of the impurity concentration peak of the first impurity region, the concentration C2 of the impurity concentration peak of the second impurity region, and the concentration C3 of the impurity concentration peak of the third impurity region are:
C2 <C3 <C1
And a first conductivity type impurity region is disposed in at least one of the first, second, and third impurity regions, and the first conductivity type impurity region is depleted by a built-in potential. It is becoming .

  According to the present invention, the photoelectric conversion carrier is not lost to the substrate side, and noise charge from the substrate can be reduced, so that the sensitivity can be improved. Efficiency can be improved.

  In the present invention, an impurity region of a first conductivity type of a photodiode forming a photoelectric conversion element is formed by a plurality of impurity regions having an impurity concentration peak, and the impurity concentration peak concentration C1 of the first impurity region, The impurity concentration peak concentration C2 of the second impurity region disposed on the substrate surface side from the first impurity region and the second impurity region disposed on the substrate surface side from the second impurity region to form a photodiode The concentration C3 of the impurity concentration peak of the third impurity region formed close to (in contact with) the conductive impurity region is C2 <C3 <C1.

  According to such a configuration, since it is possible to reduce the entry of noise charges from the substrate without losing photoelectrically converted carriers to the substrate side, it is possible to improve sensitivity, and further, the number of saturated charges, The transfer efficiency can be improved.

In addition, an impurity region of a first conductivity type of a photodiode forming a photoelectric conversion element is formed by a plurality of impurity regions having an impurity concentration peak, and a second conductivity forming a photodiode among the plurality of impurity regions. According to the configuration in which the impurity concentration peak concentration C of the impurity region formed close to (in contact with) the impurity region of the mold is 3 × 10 ¹⁵ <C <2 × 10 ¹⁷ cm ⁻³ , the number of saturated charges It becomes possible to achieve an improvement in transfer efficiency.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic cross-sectional view illustrating an embodiment of the present invention, and shows a photodiode portion 1 and a transfer MOS transistor portion 2 which are photoelectric conversion elements of a CMOS area sensor. Reference numeral 3 denotes an N-type silicon substrate, and reference numeral 4 denotes a P-type well including a plurality of P-type impurity regions. In this embodiment, the substrate has 4A to 4D impurity regions. N-type impurity regions 4E to 4G are sandwiched between the impurity regions 4A to 4D.

  7 is a gate electrode of a transfer MOS transistor, 8 is an N-type impurity region (charge storage region) for forming a photodiode, 9 is a surface P-type impurity region (surface charge recombination region) for embedding the photodiode, Reference numeral 5 denotes a field oxide film for element isolation, and reference numeral 10 denotes an N-type impurity region that functions as a floating diffusion to which charges from the charge storage region 8 are transferred.

  A P-type impurity region for forming a photodiode is formed from the P-type impurity regions 4A to 4D, and an N-type impurity region for forming a photodiode is formed from the 8 N-type impurity regions. 11 is a silicon oxide film functioning as an interlayer insulating film for insulating the gate electrode and the first wiring layer, 12 is a contact plug, 13 is a first wiring layer, and 14 is a first wiring layer and a second wiring. 15 is a second wiring layer, 16 is an interlayer insulating film that insulates the second wiring layer and the third wiring layer, 17 is a third wiring layer, and 18 is a passivation film. .

  Further, a color filter layer (not shown) and a microlens for improving sensitivity are formed on the passivation film 18. In this embodiment, three wiring layers are formed. However, depending on the specifications of the sensor, it is not contradictory to the gist of the present invention to have one or two wiring layers to ensure optical characteristics. In order to further increase the light receiving rate, a lens (in-layer lens) may be provided on the light receiving side of the color filter layer.

As shown in FIG. 3, the impurity region 4A has an impurity concentration peak concentration of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the depth at which the peak is located is from 2.0 μm from the substrate surface. It is at 4.0 μm. The impurity region 4B has an impurity concentration peak concentration of 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ and a peak depth of 1.2 μm to 2.5 μm from the substrate surface.

The impurity region 4C has an impurity concentration peak concentration of 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁶ cm ⁻³ and a peak depth of 0.8 μm to 1.5 μm. The impurity region 4D has an impurity concentration peak concentration of 2 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁷ cm ⁻³ and a peak depth of 0.5 μm to 1.0 μm. These ranges will be described later.

  In the present embodiment, the CMOS area sensor has been described, but the same effect can be obtained when applied to a CCD. In that case, the area of the floating diffusion 10 is replaced with the VCCD.

  Here, functions of the impurity regions 4A to 4D will be described. In the impurity regions 4B to 4D located in the shallow portion (substrate surface side), a connecting portion for guiding the optical carrier to the photodiode in the pixel is formed, and the impurity region layer 4A deeper than these has a potential for determining the spectral sensitivity. A peak is formed. Here, by setting the concentration of the deepest impurity region 4A to be higher than the concentration of the impurity region 4B, preferably 3 times or more, more preferably 5 times or more, a potential barrier is formed between them. Since the carriers generated by the emitted light can be efficiently guided to the photodiode without losing in the substrate direction, the sensitivity can be improved. Whether or not an electron becomes a potential barrier when thermally diffusing can be roughly expressed by the following equation.

  Vb = (kT / q) · ln (N1 / N2) <kT / q

  Here, Vb is a barrier, k is a Boltzmann constant, T is a temperature, q is an elementary charge, N1 is a peak concentration of the barrier, and N2 is a concentration before the barrier. In the region indicated by the inequality sign, the charge can overcome the barrier by thermal excitation. That is, when N1 / N2 <e (approximately 3 or less), the barrier can be overcome.

  Therefore, when N1 / N2 exceeds 3, a potential barrier exists, and when N1 / N2 exceeds 5, carriers exceeding the potential barrier can be almost ignored.

  Further, the number of saturated charges that can be held in the N-type charge storage region 8 can be controlled by controlling the concentration and depth of the impurity regions 4D and 4C. Regarding the concentration, the relationship between the concentrations of 4A to 4D will be described. The impurity concentration peak concentration C1 of the first impurity region (4A) and the second impurity region disposed on the substrate surface side of the first impurity region. (4B, 4C) impurity concentration peak concentration C2 and formed closer to (in contact with) the second conductivity type impurity region which is arranged closer to the substrate surface than the second impurity region and forms the photodiode. By setting the concentration C3 of the impurity concentration peak of the third impurity region (4D) thus made to be C2 <C3 <C1, it is possible to achieve both improvement in sensitivity by reducing loss of charge to the substrate and improvement in transfer efficiency It becomes.

  To improve sensitivity, it is desirable to form deeper wells because the volume of the impurity region that can absorb light increases. However, increasing the number of ion implantations to achieve this is a departure from the viewpoint of shortening the construction period. End up. Therefore, the regions 4E to 4G having the conductivity type opposite to the well are completely depleted by the built-in potential, so that the regions 4E to 4G remain so as not to cause a problem in operation. By setting energy, a plurality of impurity regions can be formed with a minimum number of ion implantations.

  In the present embodiment, the P-type well 4 composed of a plurality of impurity regions has a four-layer configuration of 4B to 4D and a deepest well layer for efficiently transferring charges to the charge storage region. Since the well depth should be set according to the required sensitivity, the number of impurity regions is not particularly set. If at least one connecting well is formed, the effect of improving the sensitivity can be obtained. That is, the plurality of impurity regions include a first impurity region (4A) and a second impurity region (at least one of 4B, 4C, and 4D) disposed on the substrate surface side with respect to the first impurity region. In addition, the first impurity region preferably has a higher impurity concentration peak concentration than the second impurity region.

  There is no problem even if the N-type impurity regions 4E to 4G sandwiched between the plurality of P-type impurity regions do not exist. In addition, when the P-type impurity regions are disposed apart from each other, the two P-type impurity regions are not in contact with each other, and as a result, there is no problem even if an N-type impurity region exists between the P-type impurity regions. However, in this case, it is necessary that the N-type impurity region sandwiched between the two P-type impurity regions is depleted.

  FIG. 2 is a potential diagram in the well. Carriers are shown as electrons. There is no problem even if the plurality of p-type impurity regions are not in contact with each other, but in this case, the n-type regions 4E to 4G in between are depleted, so that the potential profile is substantially flat. Is required. If not flat, the efficiency with which electrons generated in the vicinity of the deep well layer move to the electron accumulation region by the potential barrier deteriorates, resulting in a decrease in sensitivity.

  FIG. 3 shows an impurity profile of a P-type well forming a photodiode. In the present embodiment, the P-type impurity regions 4A to 4D each have an impurity concentration peak, and the impurity regions 4A to 4D have different effects on the photodiode characteristics.

  Since the impurity region 4A needs to have a potential peak for the purpose of improving sensitivity, a peak is necessary for the impurity concentration.

  The impurity region 4B needs to have a lower impurity concentration peak than the impurity region 4A in order to form a potential barrier as shown in FIG. 2, and the impurity concentration so that the impurity region 4A has the maximum potential peak. It is necessary to set a peak.

  It is necessary that the impurity region 4C does not affect the impurity concentration profile of the impurity region 4D, which will be described later, and that the relationship between 4A and 4B is maintained.

  The impurity region 4D near the substrate surface only needs to be in contact with the charge accumulation region of the photodiode, and the number of saturated electrons that can be accumulated in the charge accumulation region and the transfer characteristics from the charge accumulation region to the floating diffusion can be controlled independently. Is possible.

  The position of the concentration peak of each impurity region is not limited to this. In particular, 4D may be formed so as to cover the bottom of the N-type impurity region 8 (deep in the substrate depth direction).

  Next, the relationship between the peak concentrations of 4A and 4B and 4C located closer to the substrate surface than that will be described. FIG. 4 shows the relationship between the impurity peak concentration of the impurity region 4A and the impurity peak concentrations of the impurity regions 4B and 4C. Here, it is assumed that the impurity regions 4B and 4C have the same peak concentration. These conditions determine the aforementioned impurity concentration and peak depth range.

  If (4A density) / (4B density) is greater than 1, a significant improvement in sensitivity is recognized. If it is 2 or more, the sensitivity is further improved, and if it is 5 or more, sufficient sensitivity is improved. .

  Next, the position of the 4D peak adjacent to the impurity region 8 will be described. FIG. 5 shows the relationship between the depth of the impurity concentration peak in the impurity region 4D and the number of saturated electrons. From this figure, it can be seen that there is an optimum region for the depth of the diffusion layer of the impurity region 4D. Specifically, when the thickness is 0.5 to 1.0 μm, the sensitivity is improved as compared with the configuration of FIG.

  FIG. 6 shows an impurity concentration profile of a P-type well composed of a plurality of impurity regions, and FIG. 7 shows the relationship between the concentration profile, the number of saturated electrons, and sensitivity. When a flat impurity concentration profile is obtained by performing high-temperature heat treatment on the impurity region having an impurity concentration peak (when the P / V of each diffusion layer is close to 1), the characteristics of both the saturated electron number and sensitivity deteriorate. To do. This is because the ratio of the impurity concentration peak of the impurity region arranged deep in the substrate to the impurity concentration of the shallower impurity region is reduced by the high temperature heat treatment, and the peak position of the impurity concentration profile of the shallow impurity region is reduced. This is because it becomes uncertain.

  As described above, by forming a photodiode in a well including a plurality of impurity regions having an impurity concentration peak, it is possible to manufacture a photoelectric conversion device in which both improvement in sensitivity and improvement in the number of saturated electrons are achieved.

  Next, a manufacturing process will be described based on the cross-sectional view of FIG. A field oxide film 5 is formed on a substrate 3 made of silicon by a normal LOCOS separation method or a recess LOCOS method. Then, after the channel stop layer 6 is formed under the field oxide film 5, the P-type well 4 composed of a plurality of impurity regions is subjected to four P-type impurities (boron or the like) in this embodiment using a high energy ion implantation apparatus. ) Are sequentially implanted from a deep region, and thereafter, high-temperature heat treatment such as drive-in is not performed. The subsequent heat treatment is at most about 950 ° C.

  Since the P-type well 4 does not perform thermal diffusion, it is easy to control the concentration of each impurity region. By reducing the concentration of the impurity regions 4B to 4D in the upper layer portion, the potential at this point can be lowered, so that the sensitivity is improved and a potential difference from the impurity region 4A is easily formed. After the polysilicon electrode 7 is formed, an impurity region 8 that becomes an N-type charge storage region of the photodiode, an impurity region 9 that becomes a P-type surface layer, and an N-type impurity region 10 that becomes a floating diffusion are formed by ion implantation. Form.

  Since the manufacturing method after the contact opening process is the same as that of the conventional CMOS area sensor, it is omitted.

  As described above, the first conductivity type impurity region of the photodiode forming the photoelectric conversion element is formed of a plurality of impurity regions having an impurity concentration peak, and the impurity concentration peak concentration C1 of the first impurity region; The impurity concentration peak concentration C2 of the second impurity region disposed on the substrate surface side from the first impurity region, and the second impurity region disposed on the substrate surface side from the second impurity region to form a photodiode. By setting C2 <C3 <C1 as the impurity concentration peak concentration C3 of the third impurity region formed close to (in contact with) the impurity region of the conductivity type, It can be efficiently guided to the photodiode without loss, and sensitivity can be improved. Furthermore, transfer efficiency from the charge accumulation region to the floating diffusion (readout region) Can be improved.

(Second embodiment)
FIG. 8 shows a schematic cross-sectional view of the present embodiment. The difference from the first embodiment is that a well 204 composed of a plurality of P-type impurity regions is continuously formed under the element isolation field oxide film 205 and adjacent pixel portions. There is no channel stop region for element isolation under the film.

  This is because the impurity region 204D in the P-type well 204 including a plurality of impurity regions also has a function of element separation from adjacent pixels, so that ion implantation necessary for element separation can be performed simultaneously with the impurity region forming the well. The number of steps and masks can be reduced. If the concentration of 204C and 204B located deeper than the impurity region 204D is lowered and the impurity region 204A is set to a concentration higher than that, preferably 2 times or more, more preferably 5 times or more, the element isolation characteristics are maintained. However, an improvement in sensitivity can be obtained as in the first embodiment.

(Third embodiment)
A schematic cross-sectional view of the present embodiment is shown in FIG. 12, and a diagram schematically showing the impurity profile of the photodiode portion is shown in FIG. In the present embodiment, the charge storage region functioning as the charge storage region is formed so as to be embedded in a part of 4D adjacent to the charge storage region. By forming in this way, it is possible to suitably keep the depletion layer spread within 4D.

  In FIG. 12, the P-type impurity region indicated by 4H is formed in the channel portion under the gate of the transfer MOS transistor so that the region formed as the channel dope layer and the 4D P-type impurity region are continuous. Thus, a P-type impurity region is formed. 4H is a region necessary for the normal operation of the transfer MOS transistor, and it is important that no N-type impurity region exists.

  Specifically, description will be made using the impurity profile of FIG. 4A ′ is a P-type impurity region 4B, 4B ′ is a P-type impurity region 4C, 4D ′ is a P-type impurity region 4D, 8 ′ is an N-type impurity region 8, 'Corresponds to the P-type impurity region 9 and 4H' corresponds to the P-type impurity region 4H. Under the transfer MOS transistor, the N-type impurity region is not formed by adjusting the formation conditions of the channel dope region 4H ′ and the P-type impurity region 4D. According to such a structure, the sensitivity can be improved as in the above embodiment, and the transfer efficiency of the transfer MOS transistor can also be improved.

(Application to imaging system)
Next, an imaging system using the photoelectric conversion device of the above embodiment will be described. FIG. 14 is a block diagram showing an embodiment in which the photoelectric conversion device according to the present invention is used in a still video camera.

  In FIG. 14, 101 is a barrier that serves as a lens switch and a main switch, 102 is a lens that forms an optical image of a subject on the solid-state image sensor 104, 103 is a diaphragm for changing the amount of light that has passed through the lens 102, and 104 is A solid-state image sensor (corresponding to the photoelectric conversion device of the present invention) for capturing the subject imaged by the lens 102 as an image signal, 106 is an A / D converter that performs analog-digital conversion of the image signal output from the solid-state image sensor 104. A D converter 107 is a signal processing unit that performs various corrections and compresses the image data output from the A / D converter 106, 108 is a solid-state imaging device 104, an imaging signal processing circuit 105, and A / D conversion. , And a timing generator 109 for outputting various timing signals to the signal processor 107. 110 is a memory unit for temporarily storing image data, 111 is an interface unit (recording medium control I / F unit) for recording or reading on a recording medium, Reference numeral 112 denotes a removable recording medium such as a semiconductor memory for recording or reading image data, and 113 denotes an interface unit (external I / F unit) for communicating with an external computer or the like.

  Next, the operation of the still video camera at the time of shooting will be described. When the barrier 101 is opened, the main power supply is turned on, the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 106 is turned on.

  Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the diaphragm 103, and the signal output from the solid-state image sensor 104 is A / D converted by the A / D converter 106, and then subjected to signal processing. Input to the circuit 107. Based on this data, exposure calculation is performed by the overall control / calculation unit 109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the diaphragm 103 according to the result.

  Next, the high-frequency component is extracted based on the signal output from the solid-state image sensor 104 and the distance to the subject is calculated by the overall control / calculation unit 109. Thereafter, the lens 102 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 102 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit 110 by the overall control / calculation unit 109. Thereafter, the data stored in the memory unit 110 is recorded on a removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit 111 under the control of the overall control / arithmetic unit 109. Further, the image processing may be performed by directly entering the computer or the like through the external I / F unit 113.

  Since the present invention can improve the sensitivity of a CCD or CMOS area sensor, it can be used for a highly sensitive still camera or video camera.

It is sectional drawing of the CMOS area sensor of 1st embodiment of this invention. It is a potential diagram in a photodiode part well. It is a figure which shows the impurity concentration profile of 1st embodiment. It is a characteristic view showing the relationship between the concentration of the diffusion layer 4A and the ratio of the diffusion layers 4B and 4C and the sensitivity. It is a characteristic view showing the relationship between the concentration peak position of the diffusion layer 4D and the number of saturated electrons. It is a figure for demonstrating the impurity concentration profile of 1st embodiment. It is a figure which shows the relationship between the ratio of the peak of each diffusion layer, and a valley, and the number of saturated electrons. It is sectional drawing of the photoelectric conversion apparatus of 2nd embodiment of this invention. It is sectional drawing of the conventional CMOS area sensor. It is a schematic diagram of a conventional P-type well concentration distribution. It is a schematic diagram of a conventional P-type well concentration distribution. It is sectional drawing of the photoelectric conversion apparatus of 3rd embodiment of this invention. It is a figure which shows the impurity profile of the photodiode part of the photoelectric conversion apparatus of 3rd embodiment. It is a block diagram which shows one Embodiment at the time of applying the photoelectric conversion apparatus of this invention to a still video camera.

Explanation of symbols

1,201,301 Photodiode part 2,202,302 Transfer MOS transistor part
3,203,303 Semiconductor substrate (N-type silicon substrate)
4,204,304 P-type well 4A-4D, 204A-204D Impurity region 4E-4G, 204E-204G N-type impurity region 4H P-type impurity region 5,205,305 Field oxide film 6,306 Channel stop layer 7,207 , 307 Gate electrode of transfer MOS transistor 8, 208, 308 N-type impurity region (charge storage region)
9, 209, 309 Surface P-type impurity region 10, 210, 310 N-type impurity region 11, 211, 311 Silicon oxide film 12, 212, 312 Contact plug 13, 213, 313 First wiring layer 14, 214, 314 First Interlayer insulating film between one wiring layer and second wiring layer 15, 215, 315 Second wiring layer 16, 216, 316 Interlayer insulating film between second wiring layer and third wiring layer 17, 217, 317 First Three wiring layers 18, 218, 318 Passivation film 101 Barrier 102 Lens 103 Aperture 104 Solid-state imaging device 105 Imaging signal processing circuit 106 A / D converter 107 Signal processing unit 108 Timing generation unit 109 Overall control / calculation unit 110 Memory unit 111 Recording medium control I / F unit 112 Recording medium 113 External I / F unit

Claims (7)

A photoelectric conversion device in which a photoelectric conversion element configured to include a first conductivity type impurity region and a plurality of second conductivity type impurity regions is arranged on a first conductivity type semiconductor substrate,
The plurality of second conductivity type impurity regions are disposed below the first conductivity type impurity region, and include at least a first impurity region, the first impurity region, and the first conductivity type impurity. A second impurity region disposed between the second impurity region and a third impurity region disposed between the second impurity region and the impurity region of the first conductivity type,
The concentration C1 of the impurity concentration peak of the first impurity region, the concentration C2 of the impurity concentration peak of the second impurity region, and the concentration C3 of the impurity concentration peak of the third impurity region are:
C2 <C3 <C1
While satisfying the relationship
A first conductivity type impurity region is disposed in at least one of the first, second, and third impurity regions, and the first conductivity type impurity region is depleted by a built-in potential. A photoelectric conversion device. 2. The photoelectric conversion element according to claim 1, wherein the photoelectric conversion element further includes a second conductivity type fourth impurity region formed in contact with the substrate surface side of the first conductivity type impurity region. Conversion device. 3. The relationship between the concentration C1 of the impurity concentration peak of the first impurity region and the concentration C2 of the impurity concentration peak of the second impurity region is 3 × C2 ≦ C1. The photoelectric conversion device described. The relationship between the concentration C1 of the impurity concentration peak of the first impurity region and the concentration C2 of the impurity concentration peak of the second impurity region is 5 × C2 ≦ C1. Photoelectric conversion device. The concentration C1 of the impurity concentration peak of the first impurity region is 1 × 10 ¹⁶ cm ⁻³ <C1 <1 × 10 ¹⁸ cm ⁻³ ,
The concentration C2 of the impurity concentration peak in the second impurity region is 1 × 10 ¹⁵ cm ⁻³ <C2 <5 × 10 ¹⁶ cm ⁻³ ,
According to any one of claims 1 to 4, wherein the third concentration C3 of the impurity concentration peak in the impurity region is ^{2 × 10 15 cm -3 <C3} <2 × 10 17 cm -3 Photoelectric conversion device. 2. Each of the plurality of second conductivity type impurity regions is continuously arranged from a lower portion of the first conductivity type to a lower portion of an element isolation portion adjacent to the photoelectric conversion element. 6. The photoelectric conversion device according to any one of items 5 to 5 . The photoelectric conversion device according to any one of claims 1 to 6 ,
An optical system for imaging light onto the photoelectric conversion device;
An imaging system comprising: a signal processing circuit that processes a signal from the photoelectric conversion device.

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