CN101369594B - Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system - Google Patents
Photoelectric conversion device, method of manufacturing photoelectric conversion device, and image pickup system Download PDFInfo
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Abstract
The invention provides a photoelectric conversion device and a camera system. The photoelectric conversion device comprises a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentrationC2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2 < C3 < C1.
Description
The application is that application number is the dividing an application for the application of " photo-electric conversion device and manufacturing approach thereof and camera system " that " 200410100705.7 ", the applying date be on December 10th, 2004, denomination of invention.
Technical field
The present invention relates to photo-electric conversion device and manufacturing approach thereof and camera system, particularly relate to CMOS area transducer and manufacturing approach thereof and camera system.
Background technology
In the past, as the solid-state imager that image signal transformation is become the signal of telecommunication, CCD was well-known.This CCD has light diode array, pulse voltage is added on the electric charge that in each optical diode, accumulates reads as the signal of telecommunication.The CMOS area transducer that in addition in recent years, will carry out 1 chip blockization to optical diode and the peripheral circuit that comprises MOS transistor is as solid-state imager.CMOS area transducer and CCD compare, and it is little to have consumed power, the low advantage that waits of driving power, and anticipation will enlarge its needs from now on.
As the typical example of photo-electric conversion device, we explain the CMOS area transducer with Fig. 9.Fig. 9 representes the optical diode unit 301 and the profile schema diagram that transmits MOS transistor unit 302 of CMOS area transducer.The 303rd, N type silicon substrate; The 304th, P type trap, the 307th, the grid of transmission MOS transistor, the 308th, the N type charge accumulation region of optical diode; The 309th, be used to form the surperficial p type island region territory of imbedding the optical diode structure; The 305th, be used for the field oxide film that element separates, the 310th, form the floating diffusion region territory, keep N type area with high mercury as the function of the drain region of transmitting MOS transistor.The 311st, the silicon oxide layer that the grid and first wiring layer are insulated; The 312nd, contact plug, 313 is first wiring layers, the 314th, the interlayer dielectric that first wiring layer and second wiring layer are insulated; 315 is second wiring layers; The 316th, the interlayer dielectric that second wiring layer and the 3rd wiring layer are insulated, 317 is the 3rd wiring layers, the 318th, passivating film.Form not shown color-filter layer on the upper strata of passivating film 318 and be further used for improving the lenticule of sensitivity.The hole unit of light through being stipulated by the 3rd wiring layer 317 from surperficial incident incides optical diode.This light is absorbed in the N of optical diode type charge accumulation region 308 or P type trap 304, and it is right to generate the electron/hole cave.Wherein electron accumulation is in N type charge accumulation region 308.
As the transistorized prior art of CMOS area, for example,, put down in writing in No. 129 at United States Patent (USP) the 6th, 483, have the structure that the charge carrier shown in Figure 10 (United States Patent (USP) the 6th, 483, Fig. 6 of No. 129) distributes.Can think that this is configured in and has the high diffusion of impurities zone 6A of concentration in the dark zone in the substrate, have the efficient that raising will be fetched into face side owing to the electric charge that the systemic light of trap produces, improve the effect of sensitivity.
Existing photo-electric conversion device, particularly, in the CMOS area transducer, because the trap layer of optical diode forms through after injecting ion, carrying out thermal diffusion, so represent like Figure 11, usually the CONCENTRATION DISTRIBUTION of substrate depth direction reduces slowly.As a result, become the structure of not holding potential barrier at the substrate depth direction, in the part of the systemic light of P type trap owing on orientation substrate, lost to as the not contribution of light-to-current inversion signal.Particularly occurred along with Pixel Dimensions reduces, can not obtain the such problem of the sensitivity of wanting.In addition, also exist when control sensitivity, saturated charge number, all characteristics of transmission etc., because the parameter of creating conditions that can handle is few, so can not satisfy the problem of these performances from optical diode to the floating diffusion region territory.
On the other hand; Can think and hold the high diffusion of impurities zone of concentration in the dark zone that is configured in the substrate shown in Figure 10 of above-mentioned patent documentation; Has the effect that improves sensitivity; But when also existing all characteristics when control saturated charge number that will satisfy simultaneously and transmission etc., because the parameter of creating conditions that can handle is few, so can not satisfy the problem of these performances from optical diode to the floating diffusion region territory.In addition, in No. the 6th, 483,129, above-mentioned United States Patent (USP) in the sort of simple retroeflection grating trap structure of record, the dark current that in substrate, produces bleeds in the optical diode, makes the mis-behave of transducer.That is, solve the technical task that satisfies raising sensitivity and raising saturated charge number, transmission efficiency simultaneously so far.
The present invention accomplishes in order to solve above-mentioned problem, and the CMOS area transducer that the purpose of this invention is to provide to improve with all characteristics headed by the sensitivity of optical diode is the photo-electric conversion device and the manufacturing approach thereof of representative.
Summary of the invention
Be at semiconductor substrate and have in the photo-electric conversion device of the components of photo-electric conversion of extrinsic region of first conductivity type in the trap that is arranged on the extrinsic region that comprises a plurality of conductivity types second conductivity type opposite as the formation of characteristic of the present invention with first conductivity type with first conductivity type; A plurality of above-mentioned extrinsic regions comprise the 1st extrinsic region at least, more are configured in the 2nd extrinsic region of substrate surface side and more are configured in the 3rd extrinsic region of substrate surface side than the 2nd extrinsic region than the 1st extrinsic region, and the concentration C 3 of the concentration C 2 of the concentration C 1 of the impurity concentration peak value of above-mentioned the 1st extrinsic region, the impurity concentration peak value of above-mentioned the 2nd extrinsic region and the impurity concentration peak value of above-mentioned the 3rd extrinsic region satisfies following relationship.
C2<C3<C1
And for example fruit is according to other execution mode of the present invention; Then at semiconductor substrate with have in the photo-electric conversion device of the components of photo-electric conversion of extrinsic region of first conductivity type in the trap that is arranged on the extrinsic region that comprises a plurality of conductivity types second conductivity type opposite with first conductivity type with first conductivity type; Set the extrinsic region of a plurality of above-mentioned second conductivity types continuously, up to the element separated region bottom of above-mentioned components of photo-electric conversion adjacency.
And for example fruit is according to other execution mode of the present invention; Then at semiconductor substrate with have in the photo-electric conversion device of the components of photo-electric conversion of extrinsic region of first conductivity type in the trap that is arranged on the extrinsic region that comprises a plurality of conductivity types second conductivity type opposite with first conductivity type with first conductivity type; In a plurality of above-mentioned extrinsic regions; At least, with the concentration C 1 of the impurity concentration peak value of approaching the 1st extrinsic region of the extrinsic region of above-mentioned first conductivity type 3 * 10
15Cm
-3<c1<2 * 10
17Cm
-3Scope in.
Other characteristics of the present invention and advantage will be clear that from the following description that combines accompanying drawing to carry out, and wherein identically in whole accompanying drawings represent same or analogous parts with reference to label.
Description of drawings
Fig. 1 is the profile of the CMOS area transducer of the 1st execution mode.
Fig. 2 is the potential diagram in the optical diode unit trap.
Fig. 3 is the figure of the impurities concentration distribution of expression the 1st execution mode.
Fig. 4 is the performance plot of relation of ratio and sensitivity of concentration and diffusion layer 4B, the 4C of expression diffusion layer 4A.
Fig. 5 is the performance plot of relation of peak concentration position and the saturated electrons number of expression diffusion layer 4D.
Fig. 6 is the figure that is used to explain the impurities concentration distribution of the 1st execution mode.
Fig. 7 is the figure of relation of ratio and saturated electrons number of peak value and the lowest point of each diffusion layer of expression.
Fig. 8 is the profile of the photo-electric conversion device of the 2nd execution mode.
Fig. 9 is the profile of existing CMOS area transducer.
Figure 10 is the ideograph of existing P type trap CONCENTRATION DISTRIBUTION.
Figure 11 is the ideograph of existing P type trap CONCENTRATION DISTRIBUTION.
Figure 12 is the profile of the photo-electric conversion device of the 3rd execution mode.
Figure 13 is the figure of Impurity Distribution of optical diode unit of the photo-electric conversion device of expression the 3rd execution mode.
Figure 14 is the profile that is used to explain the 4th execution mode.
Figure 15 is the figure of pattern ground expression according to the CONCENTRATION DISTRIBUTION of the 4th execution mode.
Figure 16 is the profile that is used to explain the 5th execution mode.
Figure 17 is the top figure that is used to explain the 6th execution mode.
Figure 18 is the profile that is used to explain the 6th execution mode.
Figure 19 is that expression is applied to quiet block diagram when resembling video camera with photo-electric conversion device of the present invention.
These accompanying drawings combine with present patent application and constitute the part of present patent application, and execution mode of the present invention is described, and with describing, are used to illustrate principle of the present invention.
Embodiment
The present invention is the extrinsic region that constitutes first conductivity type of the optical diode that forms the components of photo-electric conversion with a plurality of extrinsic regions with impurity concentration peak value; Make the concentration C 1 of the impurity concentration peak value of the 1st extrinsic region, more be configured in than the 1st extrinsic region the substrate surface side the 2nd extrinsic region the impurity concentration peak value concentration C 2 and more be configured in the substrate surface side than the 2nd extrinsic region, the concentration C 3 of impurity concentration peak value of formed the 3rd extrinsic region of extrinsic region that forms the 2nd conductivity type of optical diode near (connection) has the C2 < C3 < invention of the relation of C1.
If according to this formation, then in substrate-side because do not lose the charge carrier through light-to-current inversion, can reduce entering in addition from the noise charge of substrate, thus can improve sensitivity, and then, can improve saturated charge number and transmission efficiency.
In addition; Constitute the extrinsic region of first conductivity type of the optical diode that forms the components of photo-electric conversion with a plurality of extrinsic regions with impurity concentration peak value, be set to 3 * 10 near the concentration C of the impurity concentration peak value of the extrinsic region of the 2nd conductivity type of formation optical diode in (connections) these a plurality of extrinsic regions
15Cm
-3<c1<2 * 10
17Cm
-3, then can reach the purpose that improves saturated charge number and transmission efficiency.
Below, we specify execution mode of the present invention with accompanying drawing.
(the 1st execution mode)
Fig. 1 is the profile schema diagram of explanation execution mode of the present invention, and expression forms the optical diode unit 1 and transmission MOS transistor unit 2 of the components of photo-electric conversion of CMOS area transducer.The 3rd, N type silicon substrate, the 4th, comprise the regional P type trap of a plurality of p type impurities, in the present embodiment, have the extrinsic region of 4A～4D.In addition, at each interregional N type extrinsic region 4E～4G that clips of extrinsic region 4A～4D.The 7th, the grid of transmission MOS transistor; The 8th, the N type extrinsic region (charge accumulation region) of formation optical diode; The 9th, be used to imbed the surperficial p type island region territory (surface charge is coupling regime again) that optical diode is constructed; The 5th, be used for the field oxide film that element separates; The 10th, bring into play the N type extrinsic region of function as the floating diffusion region territory of the electric charge that sends self charge accumulating region 8, be configured for forming the p type impurity zone of optical diode by the p type impurity zone of 4A～4D, be configured for forming the N type extrinsic region of optical diode by 8 N type extrinsic regions.The 11st, the silicon oxide layer of bringing into play function as being used to make the interlayer dielectric of grid and the insulation of first wiring layer; The 12nd, contact plug, 13 is first wiring layers, the 14th, the interlayer dielectric that first wiring layer and second wiring layer are insulated; 15 is second wiring layers; The 16th, the interlayer dielectric that second wiring layer and the 3rd wiring layer are insulated, 17 is the 3rd wiring layers, the 18th, passivating film.And then, form not shown color-filter layer on the upper strata of passivating film 18 and be used to improve the lenticule of sensitivity.In this execution mode, form 3 layers of wiring layer, still according to the specification of transducer, as long as can guarantee optical characteristics, making wiring layer be 1 layer or 2 layers does not have contradiction with purport of the present invention yet.In addition, receive the light rate, 1 metafiltration chromatograph is set with it not as lens (lens in the layer) are set in the light receiving unit side in order further to improve.
As shown in Figure 3, extrinsic region 4A, the concentration of its impurity concentration peak value is from 1 * 10
16Cm
-3To 1 * 10
18Cm
-3Scope in, the degree of depth of peak value position from 2.0 μ m of substrate surface in the scope of 4.0 μ m.Extrinsic region 4B, the concentration of its impurity concentration peak value is from 1 * 10
15Cm
-3To 5 * 10
16Cm
-3Scope in, the degree of depth of peak value position from the 1.2 μ m on surface in the scope of 2.5 μ m.Extrinsic region 4C, the concentration of its impurity concentration peak value is from 1 * 10
15Cm
-3To 5 * 10
16Cm
-3Scope in, the degree of depth of peak value position from 0.8 μ m of substrate surface in the scope of 1.5 μ m.Extrinsic region 4D, the concentration of its impurity concentration peak value is from 2 * 10
15Cm
-3To 2 * 10
17Cm
-3Scope in, peak value comfortable position the degree of depth from the 0.5 μ m on surface in the scope of 1.0 μ m.To discuss in the back about these scopes.
In addition, this example has been explained the CMOS area transducer, even if but being applied to CCD also obtains same effect.At this moment, floating diffusion region territory 10 is replaced as VCCD.
Here we explain the function of extrinsic region 4A～4D.At the extrinsic region 4B～4D that is arranged in shallow part (substrate surface side), form the coupling part that photocarrier is imported the optical diode in the pixel, in the extrinsic region 4A of the part darker, form the current potential peak value of decision spectral sensitivity than it.Here make the concentration of concentration ratio extrinsic region 4B of extrinsic region 4A of deepest part big; Be preferably more than and equal 3 times concentration; Preferably be preferably more than and equal 5 times concentration, between forms potential barrier, because the charge carrier that is produced by incident light is in not loss of orientation substrate; Lead-in light diode expeditiously is so can improve sensitivity.Aspect the electronics thermal diffusion, whether become potential barrier, roughly can show with formula.
Vb＝(kT/q)·ln(N1/N2)
<kT/>q
Here, Vb is a potential barrier, and k is a Boltzmann constant, and T is a temperature, and q is an electron charge, and N1 is the peak concentration of potential barrier, and N2 is the concentration before the potential barrier.In the zone that inequality is represented, can cross potential barrier through the thermal excitation electric charge.That is, when N1/N2 during e (roughly smaller or equal to 3 time) can cross potential barrier.
So, when N1/N2 surpasses 3, there is potential barrier, and, when N1/N2 surpasses 5, roughly can ignore the charge carrier of crossing potential barrier.
In addition, the concentration and the degree of depth through control extrinsic region 4D, 4C also can be controlled at the saturated charge number that can keep in the N type charge accumulation region 8.About concentration; When discussing the concentration relationship of 4A～4D; The concentration C 1 of the impurity concentration peak value through making the 1st extrinsic region (4A), more be configured in than the 1st extrinsic region the substrate surface side the 2nd extrinsic region (4B, 4C) the impurity concentration peak value concentration C 2 and more be configured in the substrate surface side than the 2nd extrinsic region; The concentration C 3 of impurity concentration peak value of formed the 3rd extrinsic region of extrinsic region (4D) that forms the 2nd conductivity type of optical diode near (connection) has following relationship C2 < C3 < C1; Reduce the loss of electric charge, raising sensitivity and raising transmission efficiency are set up simultaneously to substrate.
Improve sensitivity and hope to form darker trap, this be for increase can light absorbing extrinsic region volume, to increase the number of times that ion injects in order to realize it, this viewpoint from the reduction of erection time will be avoided.Therefore; Regional 4E～the 4G opposite with trap is because built-in potential and exhausting fully; Do not become problem and reserve area 4E～4G in the work in order to make, through the energy that the ion of setting each extrinsic region 4A～4D injects, can make ion inject number of times is that minimally forms a plurality of extrinsic regions.
In this execution mode; The P type trap 4 that is made up of a plurality of extrinsic regions is to be used for expeditiously electric charge being transported to the 4B～4D of charge accumulation region and 4 layers of deep trap layer constitute; But in this execution mode; Because should correspondingly set the well depth degree with the required sensitivity of the extrinsic region that becomes 4B～4D, so do not set its quantity especially.Again, if form the connection trap of one deck at least, the effect of the sensitivity that then can be improved.Promptly; A plurality of extrinsic regions comprise the 1st extrinsic region (4A) and more are configured in the 2nd extrinsic region (at least one among 4B, 4C, the 4D) of substrate surface side than the 1st extrinsic region; Compare with the 2nd extrinsic region, hope the concentration height of the impurity concentration peak value of the 1st extrinsic region.
Even if it is there is not the N type extrinsic region 4E～4G that is sandwiched in a plurality of p type impurities zone, also no problem.In addition, the p type impurity zone is separated up and down when being provided with, 2 p type impurity zones do not join, and the result is even if exist N type extrinsic region also no problem between the p type impurity zone.But, at this moment, need make the exhausting of N type extrinsic region that is clipped by 2 p type impurity zones.
Fig. 2 is the potential diagram in the trap.Charge carrier is represented as electronics.Even if it is also no problem that each zone in a plurality of p type impurities zone does not join.But at this moment, can try to achieve the Potential distribution of general planar through making the exhausting of N type extrinsic region 4E～4G that is in therebetween.When not being smooth, because potential barrier makes near the electronics that dark trap layer, produces to the mobile degradation in efficiency in electron accumulation zone, the result reduces sensitivity.
Fig. 3 is the Impurity Distribution that expression forms the P type trap of optical diode.In this execution mode, p type impurity zone 4A～4D holds the impurity concentration peak value respectively, and extrinsic region 4A～4D is different to the influence of optical diode characteristic.
Need extrinsic region 4C to after the not influence of impurities concentration distribution of the extrinsic region 4D that states, and keep the relation of 4A and 4B.
Being near the extrinsic region 4D of substrate surface can join with the charge accumulation region of diode, and the saturated electrons number and the transmission characteristic from charge accumulation region to the floating diffusion region territory that can be accumulated in the charge accumulation region can be controlled independently.
The position of the peak concentration of each extrinsic region is not limited thereto, and particularly 4D also can the form of (in the depths of substrate depth direction) form N type extrinsic region 8 below covering.
Below, we explain 4A and more are positioned at the 4B of substrate surface side, the peak concentration relation of 4C than it.Fig. 4 representes the relation of impurity peak concentration of impurity peak concentration and extrinsic region 4B, the 4C of extrinsic region 4A.Here, the peak concentration of establishing extrinsic region 4B and extrinsic region 4C equates.Scope according to above-mentioned impurity concentration of these conditional decisions and peak depth.
If (concentration of 4A)/(concentration of 4B) is bigger than 1, then thinking has raising as having a mind to poor sensitivity, if more than or equal to 2 then have the effect of further raising sensitivity, and if then more than or equal to 5 then think and improved sensitivity fully.
Below, we explain the peak near the 4D of extrinsic region 8.Fig. 5 representes that the degree of depth and the relation of saturated electrons number of the impurity concentration peak value of extrinsic region 4D can know that from Fig. 5 there is best region in the degree of depth of the diffusion layer of extrinsic region 4D.Specifically, sensitivity has improved if 0.5～1.0 μ m then compares with the formation of Figure 11.
Fig. 6 is the impurities concentration distribution of the P type trap that is made up of a plurality of extrinsic regions of expression, and Fig. 7 representes the relation of this CONCENTRATION DISTRIBUTION and saturated electrons number and sensitivity.When through the extrinsic region of holding the impurity concentration peak value is carried out high-temperature heat treatment, when forming smooth impurities concentration distribution (P/V of each diffusion layer is near 1), any one characteristic all worsens in saturated electrons number and the sensitivity.This is because through high-temperature heat treatment, is configured in the impurity concentration peak value of the extrinsic region that the deep-seated of substrate puts and diminishes and the peak of the impurities concentration distribution of the shallow extrinsic region uncertain cause that becomes than the ratio of the impurity concentration of its shallow extrinsic region.
From above-mentioned visible,, can make to satisfy simultaneously and improve sensitivity and the photo-electric conversion device that improves the saturated charge number through in the trap that comprises a plurality of extrinsic regions, forming optical diode with impurity concentration peak value.
Below, we are according to the profile explanation manufacturing step of Fig. 1.
On the substrate that constitutes by silicon 3, form field oxide film 5 with common LOCOS partition method or otch (recess) LOCOS method etc.And; Below field oxide film 5 behind the formation channel stop layer 6; Utilize the energetic ion injection device, in this execution mode, inject 4 p type impurities (boron etc.) in order, after this carry out the such high-temperature heat treatment of deep diffusion and form the P type trap 4 that constitutes by a plurality of extrinsic regions from dark zone.After this heat treatment is the highest to be about 950 ℃.Because this P type trap 4 does not carry out thermal diffusion, control each regional concentration easily.Because through making the extrinsic region 4B～4D as top section is low concentration, can reduce the current potential at this place, so improve sensitivity easily and form potential difference with extrinsic region 4A.And, after forming polysilicon electrode 7, inject through ion, become the N type charge accumulation region of optical diode extrinsic region 8, become the extrinsic region 9 of P type superficial layer and become the N type extrinsic region 10 in floating diffusion region territory.
Because the later manufacturing approach of contact hole step is identical with existing CMOS area transducer, so omit explanation to them.
As stated; Through constitute the extrinsic region of first conductivity type of the optical diode that forms the components of photo-electric conversion by a plurality of extrinsic regions with impurity concentration peak value; Make the concentration C 1 of the impurity concentration peak value of the 1st extrinsic region, more be configured in than the 1st extrinsic region the substrate surface side the 2nd extrinsic region the impurity concentration peak value concentration C 2 and more be configured in the substrate surface side than the 2nd extrinsic region; The concentration C 3 of impurity concentration peak value of formed the 3rd extrinsic region of extrinsic region that forms the 2nd conductivity type of optical diode near (connection) has the C2 < C3 < relation of C1; Can make the photocarrier of absorption not lose lead-in light diode expeditiously at orientation substrate; Can improve sensitivity, and then, transmission efficiency can be improved from charge accumulation region to floating diffusion region territory (reading the zone).
(the 2nd execution mode)
Fig. 8 representes the profile schema diagram of this execution mode.The place different with the 1st execution mode is to form trap 204 this point that are made up of a plurality of p type impurities zone continuously element isolation field oxide-film 205 times and till the adjacent pixels unit, under field oxide film, do not exist to be used for the channel stop region that element separates.Like this, through the extrinsic region 204D in the P type trap 204 that comprises a plurality of extrinsic regions have and adjacent pixels between the element separation function, can carry out element simultaneously with the extrinsic region that forms trap and separate required ion and inject, can reduce step and number of masks.Be in the locational 204C darker, the concentration of 204B if reduce than extrinsic region 204D; Making the concentration ratio of extrinsic region 204A, they are big; Setting is preferably greater than and equals 2 times, preferably is preferably greater than and equals 5 times concentration; Then can simultaneously keep the element stalling characteristic, one side likewise improves sensitivity with the 1st execution mode.
(the 3rd execution mode)
Figure 12 representes the mode sectional drawing of this execution mode, and Figure 13 is the figure of the Impurity Distribution of pattern ground expression optical diode unit.In this execution mode, form to make and imbed near the mode in the part of the 4D of this charge accumulation region as the charge accumulation region of charge accumulation region performance function.Through forming in this wise, can the expansion of depletion layer suitably be limited in the 4D.
Again, in Figure 12, in the trench cells of the p type impurity zone passage shown in the 4H under the grid that transmits MOS transistor, formation makes as the p type impurity zone of the zone of channel doping layer formation and 4D continuous, is formed as the p type impurity zone.4H is in order to transmit the required zone of MOS transistor operate as normal, importantly not have N type extrinsic region.Particularly, the Impurity Distribution with Figure 13 describes.Respectively, 4A ' is corresponding with p type impurity zone 4A, and 4B ' is corresponding with p type impurity zone 4B; 4C ' is corresponding with p type impurity zone 4C, and 4D ' is that p type impurity zone 4D is corresponding, 8 ' corresponding with N type extrinsic region 8; 9 ' corresponding with p type impurity zone 9,4H ' is corresponding with p type impurity zone 4H.Formation condition through adjustment channel doping zone 4H ' and p type impurity zone 4D below transmitting MOS transistor, realizes not forming the structure of N type extrinsic region.If according to this structure, then can likewise improve sensitivity, and then also can improve the transmission efficiency that transmits MOS transistor with above-mentioned execution mode.
(the 4th execution mode)
In this execution mode, we are special to discuss about the concentration near the impurity concentration peak value of the extrinsic region of charge accumulation region.Through reducing the impurity concentration near the extrinsic region of charge accumulation region, textural at optical diode produces drawback in the characteristic beyond the sensitivity.Exist because reduce in the concentration of the charge accumulation region of the optical diode trap below directly, thus when abundant exhausting during the replacement electric charge accumulating unit, especially when exhausting fully, the problem of exhausting voltage increases that kind.This point is illustrated in greater detail.
As the method for the replacement noise that is used to remove optical diode, making in the optical diode fully during replacement and during reading electric charges, the replacement of exhausting operation has effect, in fact practicability especially to reducing noise.In order to realize it, the voltage ratio reset voltage of (preferably fully) exhausting is low fully need to be used in optical diode, in addition, when transmitting the connection (ON) of grid, in control reference voltage, need carry out electric charge fully and transmit.Transmit easy viewpoint from this electric charge, also need make the alap design of exhausting voltage of optical diode.On the other hand, in order to ensure sufficient dynamic range, i.e. the sufficient saturated charge number of optical diode hopes that the concentration of charge accumulation region of optical diode is high.Therefore, although have the effect that the concentration that reduces charge accumulation region can reduce exhausting voltage, be unsafty from the viewpoint of guaranteeing sufficient dynamic range.
So, hope to have to satisfy simultaneously and transmit electric charge and the solid-state imager of guaranteeing the requirement of dynamic range easily.
So in this execution mode; Optical diode is that the extrinsic region (charge accumulation region) through second conductive type well that forms on the semiconductor substrate that is included in first conductivity type at least, first conductivity type forms; And above-mentioned trap comprises a plurality of extrinsic regions with impurity concentration peak value, will be set in 3 * 10 near the concentration of the impurity concentration peak value of the extrinsic region of above-mentioned charge accumulation region
15～2 * 10
17Cm
-3Scope in.
Like this; Through setting than the height of prior art near the concentration of the impurity concentration peak value (the 11st impurity concentration peak value) of the extrinsic region of charge accumulation region; Can suppress expansion to the depletion layer of trap side extension; The result can simultaneously reduce the exhausting voltage of diode, and one side is kept saturated charge.
Specifically, during the charge carrier of record distributed in No. the 6th, 483,129, above-mentioned United States Patent (USP), at the near surface near the trap of charge accumulation region, the zone under the accumulating region had about 1 * 10
15Cm
-3Concentration, at this moment, depletion layer extends about 1 μ m in the trap side.According to present inventor's actual measurement, at this moment, the depletion layer voltage that does not have contribution invalidly to need to saturated charge is roughly 1V.To this, in this execution mode, the concentration through the extrinsic region under the regulation accumulating region can reduce depletion layer voltage significantly.Here the position that disposes the extrinsic region of regulation impurity concentration is near charge accumulation region, is configured in the locational zone that forms depletion layer.
Further; Preferably will be in the concentration of the impurity concentration peak value (the 3rd impurity concentration peak value) of the formed zone line 109 of this extrinsic region downside (substrate depth direction) more than or equal near 1/4 of the concentration of the impurity concentration peak value of charge accumulation region, and smaller or equal to 1/3 of the peak concentration (concentration of the 2nd impurity concentration peak value) of the extrinsic region that is configured in depth location 110.If according to this formation, then can be taken in the prior art charge carrier in the substrate-side loss as signal charge, can improve quantization efficiency, this is more satisfactory.
In addition,, can suitably be applied in pixel, have the structure of the amplifier element of the electric charge that amplifies light-to-current inversion as the pixel structure.
Figure 14 is the profile that is used to explain this execution mode.The 101st, N type silicon substrate (semiconductor substrate); On N type silicon substrate 101, form the P type trap 108～110 comprise extrinsic region, on substrate surface, form element separated region 102, transmit transistorized grid 103, become the surperficial p type impurity zone 106 of the N type extrinsic region 104 in floating diffusion region territory, the N type extrinsic region 105 that becomes the charge accumulation region of optical diode, optical diode and be used to provide the p type impurity zone 111 of the raceway groove that transmits MOS transistor with impurity concentration peak value.On light shield layer 107, having the unit, hole is used to cover and is mapped to the light of diode with exterior domain.In addition, omitted light shield layer wiring layer in addition in the figure.In Figure 14, expression is divided into 3 zones according to the p type impurity zone that different purpose will form trap.In Figure 14, near the surface, configuration is near the p type impurity zone 108 with the 1st impurity concentration peak value below the charge accumulation region of optical diode 105.Extrinsic region 108 has the effect of the width of the depletion layer in the accumulating region (N type extrinsic region) that is suppressed at optical diode the engaging between 105.Through this effect, the exhausting voltage of optical diode is descended, the current potential that extrinsic region 104 is reset is reset to optical diode with rising, can improve transmission efficiency, more gratifying is to transmit fully.
In addition, can reduce in the replacement of optical diode and required transmission grid voltage in transmitting, the voltage the during connection (ON) that promptly reduces to transmit transistorized grid 103 can not can cause the rising ground of supply voltage to guarantee dynamic range.
In addition; For example can have the extrinsic region 110 that is configured in darker locational the 2nd impurity concentration peak value than extrinsic region 108 through injecting the formation of boron ion; When the acceleration energy with 2MeV injects, can roughly form on the degree of depth of 3 μ m leaving silicon face.Photocarrier about producing in the place darker than the place of the impurity concentration peak value that forms extrinsic region 110 loses in silicon substrate, still about collecting in the optical diode side than the photocarrier that produces in the shallow part of extrinsic region 110.The 109th, the extrinsic region in the middle of being configured in is diffused into face side in order to make near the photocarrier that extrinsic region 110, produces, to form than extrinsic region 110 low concentration.
Figure 15 is the key diagram of CONCENTRATION DISTRIBUTION of the vertical direction of optical diode unit.The 206th, the CONCENTRATION DISTRIBUTION in the surperficial p type impurity zone of expression optical diode, 106 corresponding with Figure 14.206 can form through injecting boron or boron fluoride.The 205th, the CONCENTRATION DISTRIBUTION of the accumulating region of optical diode, 105 corresponding with Figure 14.205 can form through injecting phosphorus or arsenic.The 208th, near the CONCENTRATION DISTRIBUTION in the p type impurity of accumulating region 205 zone, 108 corresponding with Figure 14.209,209 ' and be the CONCENTRATION DISTRIBUTION of zone line, 109 corresponding with Figure 14.In Figure 15, zone line is held 2 sections peak values and is formed.Like this, it also is effective injecting the situation that forms according to the ion of desirable structure through multistage.209,209 ' can inject boron or boron fluoride forms through different 2 times of acceleration energy.210 expressions than 208,209 be positioned at the extrinsic region in darker place CONCENTRATION DISTRIBUTION, 110 corresponding with Figure 14.We have omitted the explanation about 111 in addition.
Here, discuss in detail below and be used for improving simultaneously sensitivity and the method that improves the saturated charge number.
Aspect the electronics thermal diffusion, whether form potential barrier, roughly can show with formula.
Vb＝(kT/q)·ln(N1/N2)
<kT/>q
Here, Vb is a potential barrier, and k is a Boltzmann constant, and T is a temperature, and q is an electron charge, and N1 is the peak concentration of potential barrier, and N2 is the concentration before the potential barrier.In the zone that inequality is represented, can cross potential barrier through the thermal excitation electric charge.That is, when N1/N2 during e (roughly smaller or equal to 3 time) can cross potential barrier.Therefore the function of the preferred 210 current potential performance potential barriers that form in this execution mode, in addition, the current potential that forms near the well area 208 of accumulating region 205 has the formation of the potential barrier of not forming.Particularly as stated, the concentration of the impurity concentration peak value of (1) extrinsic region 210 more than or equal to zone line 209,209 ' 3 times of peak concentration.(2) near the peak concentration of the extrinsic region 208 of accumulating region 205 smaller or equal to zone line 209,209 ' 4 times of peak concentration.
The reason of getting smaller or equal to 4 times about (2) is to have the relation of cancelling out each other as Net (pure) concentration because of the well area 208 near accumulating region 205; So when only being conceived to trap (boron) even if about 4 times concentration during concentration, the cause that the Net of actual effect (pure) concentration in fact also reduces.Further, when the concrete example of concentration relationship of this condition is satisfied in expression, because be made as 3 * 10 as stated near the peak concentration of the extrinsic region 208 of accumulating region 205
15～2 * 10
17Cm
-3So, zone line 209,209 ' peak concentration be 1 * 10
15～5 * 10
16Cm
-3, the peak concentration of extrinsic region 210 is 3 * 10
15～1 * 10
18Cm
-3Be effective.
Below, discuss the exhausting voltage method that is used to suppress optical diode in detail.As the ideal designs of this execution mode, it is important that the expansion of depletion layer is stayed in the approaching extrinsic region 108.In depletion layer; When considering positive fixed charge as the power line of starting point negative fixed charge as terminal point, the fixed charge number that the sum of the fixed charge of accumulating region 105 equals in the depletion layer in the surperficial p type impurity zone 106 is counted sum with the interior fixed charge of depletion layer in the approaching p type impurity zone 108.
When we consider that the peak concentration in surperficial p type impurity zone 106 is higher than 108; More than half fixed charge numbers can be taken on by surperficial p type impurity zone 106, and the peak concentration of approaching impurity concentration 108 also can become a solution accumulating region 105 below 1/2.If according to present inventor's experiment, investigation, then the peak concentration at accumulating region 105 is 3 * 10<sup >16</sup>Cm<sup >-3</sup><the peak concentration of accumulating region 205<8 * 10<sup >17</sup>Cm<sup >-3</sup>, the peak concentration of approaching extrinsic region 208 is 3 * 10<sup >15</sup>Cm<sup >-3</sup><the peak concentration of extrinsic region 208<under the situation of the peak concentration of accumulating region 205, can access the effect of this execution mode.More suitable is, if more than or equal to accumulating region 205 14 the effect height.More gratifying is that the peak concentration that makes accumulating region 205 is 5 * 10<sup >16</sup>Cm<sup >-3</sup><the peak concentration of accumulating region 205<2 * 10<sup >17</sup>Cm<sup >-3</sup>, and the peak concentration of approaching extrinsic region 208 is 1 * 10<sup >16</sup>Cm<sup >-3</sup><the peak concentration of extrinsic region 208<the peak concentration of accumulating region 205, on be limited to the concentration of accumulating region.
In addition, it is more effective having following relationship about the degree of depth of each peak concentration.The degree of depth of the peak concentration of accumulating region is the peak concentration of V1, approaching extrinsic region 208 when being V2 in season, and < < relation of 2 * V1 can more effectively obtain the effect of this execution mode to V2 through V1.
(the 5th execution mode)
Figure 16 is the key diagram of this execution mode.301～311 101～111 corresponding with Figure 14 respectively.In this execution mode, on whole of pixel, do not form extrinsic region 308, and only in the lower part of accumulating region 305, form near the accumulating region 305 of optical diode.
This structure has advantage.
(1) [constructional advantage] sucks zone 304, so have the effect of the blooming of preventing, stain, colour mixture because can read the electric charge that overflows from pixel adjacent.The design of 308 concentration can reduce in the pixel with the influence of the characteristics of transistor of pixel region outer (not drawing among the figure), increase design freedom.Has the advantage that the junction capacitance amount is little, the gain increase causes SN ratio increase or the like because of reading the zone.
(2) [advantage in the processing] can be with identical with accumulating region 305 or form approaching p type impurity zone 308 with surperficial p type impurity zone 306 identical photoresists.Also can use same photoresist to form p type impurity zone 310 on the principle, but also need form the thick photoresist that can guarantee to stop performance, be difficult to corresponding with trickle pattern for dark ion injection.In addition; Also can use Epitaxial (extension) method to form in the situation of extrinsic region 310 that kind; Using identical or forming in the process near the p type impurity zone 308 of accumulating region 305 with surperficial p type impurity zone 306 identical photoresists with accumulating region 305; Also can not increase step, obtain the effect of this execution mode.
(the 6th execution mode)
Figure 17 is the top figure according to the pixel structure of this execution mode.401 expression active regions, 402 expressions transmit grid, 403 expression optical diode zones, the zone is read in 404 expressions.In addition, the length of the direction parallel with transistorized channel width is Dy1 and Dy2, the width in their expression optical diode zones.Because usually exhausting voltage increases in the wide part of width, thus shown in figure 15 when near transmission grid 402 sides, adopting the layout of narrow width, produce the problem that transmits the difficulty that kind that becomes fully.That is, exist when resetting or transmit, the Dy1 part is than Dy2 part exhausting fully earlier, and residual charge in the Dy2 part produces the such problem of replacement noise.This problem is because from the influence of the expansion of the transverse direction (length direction of Dy1, Dy2) of depletion layer, the relevant generation with size of exhausting voltage.When mentioning concrete structure, low in the concentration of design trap near surface, make depletion layer in the situation that depth direction is expanded extensively, become significant especially problem.In this execution mode, suppress the result of depletion layer, can alleviate restriction,, also can not produce the replacement noise even if carry out layout shown in Figure 17 to layout in the expansion of depth direction.Its reason is explained with Figure 18.Figure 18 is the ideograph of expression along the section of the Dy1 of Figure 17 and Dy2.405 are illustrated in the depletion layer area of expanding in optical diode and the trap, express its depth D z in the drawings.406 expressions are remaining neutral region at last before exhausting fully just.407 are illustrated in the appearance of the depletion layer of depth direction expansion, and 408 are illustrated in the appearance of the depletion layer of transverse direction (length direction of Dy1, Dy2) expansion.As shown in the drawing; Effect by the depletion layer of expanding at depth direction causes the situation of exhausting fully; The dependence relevant with layout all do not form identical exhausting voltage in Dy1, Dy2, can carry out the replacement fully of optical diode and transmission fully.In the situation of Dy1 big structure, cause exhausting fully because expand 408 influence by the transverse direction of depletion layer, so the relation of exhausting voltage and Dy1 width is very little in the place of Dy1 than the expansion of the depth direction of narrow situation of this figure and depletion layer 407.In view of above problem, in this execution mode,, adopt following structure for the exhausting voltage that makes Dy1 part and Dy2 part is equal to.
At Dy2>in the pixel of the layout of Dy1, suppress the width that depletion layer stretches at depth direction, set trap concentration so that Dy1>Dz.
In the structure of this execution mode, can on the plane figure of optical diode, all make exhausting voltage identical in the whichever place, can carry out high speed operation, can suppress the image quality aggravation that causes by the replacement noise again.
Each this execution mode can carry out a plurality of 2 dimension shapes configurations and uses as area transducer (solid camera head) in addition.In addition, the zone of reading of in each embodiment, explaining is connected with the grid of insulated gate electrode transistor npn npn, can be used in through the charge voltage conversion and read such amplifying-type solid-state imaging device (among the Active Pixel Sensor (CMOS active pixel sensor).
In whole execution modes, we state charge carrier as electronics in addition, are in the situation in hole at charge carrier still, can make the conductivity type of each extrinsic region become opposite conductivity type.
(in the application of camera system)
Figure 18 is the figure of the example of the block diagram of expression when photo-electric conversion device of the present invention is applied to video camera.Before photographic lens 1002 shutters 1001, the control exposure.Light quantity by aperture 1003 controls need is imaged on the solid camera head 1004 it.Handle from the signal of solid camera head 1004 outputs by signal processing circuit 1005, analog signal is transformed to digital signal by A/D converter 1006.Further carry out computing by the digital signal of 1007 pairs of outputs of signal processing unit.Treated digital signal is stored in the memory 1010, sends to external equipment through exterior I/F1013.Except with regularly 1008 pairs of solid camera heads 1004 of generating unit, camera signal processing circuit 1005, A/D converter 1006, signal processing unit 1007 are controlled, control by 1009 pairs of whole systems of whole control unit/computing unit.In order image to be recorded in the recording medium 1012, through the recording medium control I/F unit 1011 by whole control unit/computing unit control, record output digital signal.
Claims (19)
1. the photo-electric conversion device in the semiconductor substrate that is formed on first conductivity type; Have the components of photo-electric conversion; The said components of photo-electric conversion have: the extrinsic region of a plurality of second conductivity types that the extrinsic region of first conductivity type and conductivity type are opposite with first conductivity type is characterized in that:
The extrinsic region of above-mentioned a plurality of second conductivity types be configured in above-mentioned first conductivity type extrinsic region below,
The extrinsic region of above-mentioned a plurality of second conductivity types comprises the 1st extrinsic region at least, be configured in the 2nd extrinsic region between the extrinsic region of the 1st extrinsic region and above-mentioned first conductivity type and be configured in the 2nd extrinsic region and the extrinsic region of above-mentioned first conductivity type between the 3rd extrinsic region
The concentration C 3 of the concentration C 2 of the concentration C 1 of the impurity concentration peak value of above-mentioned the 1st extrinsic region, the impurity concentration peak value of above-mentioned the 2nd extrinsic region and the impurity concentration peak value of above-mentioned the 3rd extrinsic region satisfies following relationship:
C2＜C3＜C1。
2. photo-electric conversion device according to claim 1 is characterized in that:
The above-mentioned components of photo-electric conversion also have:
The 4th extrinsic region that is connected formed second conductivity type with the substrate surface side of the extrinsic region of above-mentioned first conductivity type.
3. photo-electric conversion device according to claim 1 is characterized in that:
Wherein, 3 * C2≤C1.
4. photo-electric conversion device according to claim 3 is characterized in that:
Wherein, 5 * C2≤C1.
5. photo-electric conversion device according to claim 1 is characterized in that:
The extrinsic region of other first conductivity types is configured among 1 between above-mentioned the 1st, the 2nd, the 3rd extrinsic region at least, and the extrinsic region of this other first conductivity type is by exhausting of built-in potential.
6. photo-electric conversion device according to claim 1 is characterized in that:
Wherein, 1 * 10
16Cm
-3＜C1＜1 * 10
18Cm
-3, 1 * 10
15Cm
-3＜C2＜5 * 10
16Cm
-3, 2 * 10
15Cm
-3＜C3＜2 * 10
17Cm
-3
7. photo-electric conversion device according to claim 1 is characterized in that:
Set the extrinsic region of above-mentioned a plurality of second conductivity types continuously, up to the element separated region bottom of above-mentioned components of photo-electric conversion adjacency.
8. photo-electric conversion device according to claim 7 is characterized in that:
The above-mentioned components of photo-electric conversion also have: the 4th extrinsic region that is connected formed second conductivity type with the extrinsic region of above-mentioned first conductivity type.
9. photo-electric conversion device according to claim 1 is characterized in that:
The concentration C 3 of the impurity concentration peak value of above-mentioned the 3rd extrinsic region is 3 * 10
15＜C3＜2 * 10
17Cm
-3Scope in.
10. photo-electric conversion device according to claim 1 is characterized in that:
The concentration C 2 of the impurity concentration peak value of above-mentioned the 2nd extrinsic region satisfies the relation of C2＜C1＜4 * C2.
11. photo-electric conversion device according to claim 1 is characterized in that:
The concentration C 4 of the impurity concentration peak value of the extrinsic region of above-mentioned first conductivity type is 3 * 10
16＜C4＜8 * 10
17Cm
-3Scope in, the concentration C of the impurity concentration peak value of above-mentioned the 3rd extrinsic region 3 satisfies 3 * 10
15Cm
-3The relation of＜C3＜C4.
12. photo-electric conversion device according to claim 1 is characterized in that:
The concentration C 4 of the impurity concentration peak value of the concentration C 3 of the impurity concentration peak value of above-mentioned the 3rd extrinsic region and the extrinsic region of above-mentioned first conductivity type satisfies the relation of C4/4＜C3＜C4.
13. photo-electric conversion device according to claim 1 is characterized in that:
The extrinsic region of above-mentioned a plurality of second conductivity types is not configured in below transistor and at least a portion that reads the zone in the pixel.
14. photo-electric conversion device according to claim 1 is characterized in that:
The degree of depth V2 of the concentration C 3 of the degree of depth V1 of the impurity concentration peak value of the extrinsic region of above-mentioned first conductivity type and the impurity concentration peak value of above-mentioned the 3rd extrinsic region has the relation of V1＜V2＜2 * V1.
15. photo-electric conversion device according to claim 1 is characterized in that:
In pixel, also have to transmit and use transistor,
The above-mentioned components of photo-electric conversion are optical diodes; The extrinsic region of above-mentioned first conductivity type has 2 value: Dy1, Dy2 with above-mentioned transmission with the width on the direction of transistorized channel width almost parallel at least; Above-mentioned Dy1 part is more used transistorized grid near above-mentioned transmission than the Dy2 part; When the width of the depth direction of the depletion layer when above-mentioned in season optical diode is reset is Dz, satisfy the relation of Dy2＞Dy1＞Dz.
16. a camera system is characterized in that comprising:
The described photo-electric conversion device of claim 1;
Make the optical system of photoimaging in this photo-electric conversion device;
Processing is from the signal processing circuit of the output signal of this photo-electric conversion device.
17. the manufacturing approach of a photo-electric conversion device; Said photo-electric conversion device has the components of photo-electric conversion in the semiconductor substrate of first conductivity type; The extrinsic region of following, a plurality of second conductivity types that conductivity type is opposite with first conductivity type of extrinsic region that the said components of photo-electric conversion have first conductivity type and the extrinsic region that is configured in above-mentioned first conductivity type is characterized in that comprising:
After the semiconductor substrate to above-mentioned first conductivity type carries out repeatedly the ion injection; Can keep in each zone of injecting through ion under the temperature of distribution and carry out heat diffusion treatment, form the step of the extrinsic region of above-mentioned a plurality of second conductivity types with impurity concentration peak value.
18. the manufacturing approach of photo-electric conversion device according to claim 17 is characterized in that also comprising:
Be connected, form the step of the extrinsic region of second conductivity type with the substrate surface side of the extrinsic region of this first conductivity type.
19. the manufacturing approach of photo-electric conversion device according to claim 17 is characterized in that:
The treatment temperature of above-mentioned heat diffusion treatment is smaller or equal to 950 ℃.
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| JP6541361B2 (en) | 2015-02-05 | 2019-07-10 | キヤノン株式会社 | Solid-state imaging device |
| JP2018107358A (en) * | 2016-12-27 | 2018-07-05 | キヤノン株式会社 | Manufacturing method of imaging apparatus and imaging system |
| JP7406887B2 (en) | 2019-08-07 | 2023-12-28 | キヤノン株式会社 | Photoelectric conversion device, radiation imaging system, photoelectric conversion system, mobile object |
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| US6504194B1 (en) * | 1999-12-01 | 2003-01-07 | Innotech Corporation | Solid state imaging device, method of manufacturing the same, and solid state imaging system |
| CN1453628A (en) * | 2002-04-26 | 2003-11-05 | 奥林巴斯光学工业株式会社 | Camera and its used photographic elements unit |
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| JPS63174358A (en) * | 1987-01-14 | 1988-07-18 | Hitachi Ltd | Solid-state image sensor |
| JPH1126741A (en) * | 1997-07-04 | 1999-01-29 | Toshiba Corp | Solid-state image pick-up device |
| JP3934827B2 (en) * | 1999-06-30 | 2007-06-20 | 株式会社東芝 | Solid-state imaging device |
| JP4449106B2 (en) * | 1999-07-14 | 2010-04-14 | ソニー株式会社 | MOS type solid-state imaging device and manufacturing method thereof |
| JP3315962B2 (en) * | 1999-12-01 | 2002-08-19 | イノテック株式会社 | Solid-state imaging device, method of manufacturing the same, and solid-state imaging device |
| JP3596749B2 (en) * | 1999-12-01 | 2004-12-02 | 日本ビクター株式会社 | CMOS image sensor |
| JP3688980B2 (en) * | 2000-06-28 | 2005-08-31 | 株式会社東芝 | MOS type solid-state imaging device and manufacturing method thereof |
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| US6504194B1 (en) * | 1999-12-01 | 2003-01-07 | Innotech Corporation | Solid state imaging device, method of manufacturing the same, and solid state imaging system |
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