JP4940607B2 - Solid-state imaging device, manufacturing method thereof, and camera - Google Patents

Description

  The present invention particularly relates to a MOS solid-state imaging device, a method for manufacturing the same, and a camera including the solid-state imaging device.

  In recent years, as a solid-state imaging device mounted on a mobile device such as a camera-equipped mobile phone or a PDA (personal digital assistant), a MOS type image sensor whose power supply voltage is lower than that of a CCD image sensor from the viewpoint of power consumption. Many are used. As a MOS type image sensor, one in which three transistors (active elements) are included in a unit pixel is known (see Patent Document 1).

In either case of the CCD type or the MOS type, a structure in which a p-type hole accumulation region is formed on the outermost surface of the n-type sensor unit is adopted as a structure for suppressing white spots (Patent Document 2). reference). By forming the p-type hole accumulation region on the outermost surface of the sensor unit, dark current generated at the interface between the substrate and the insulating film can be suppressed, and white spots due to dark current can be suppressed.
JP 2002-51263 A JP 2004-179473 A

  However, suppression of white spots is insufficient only by the effect of the hole accumulation region, and further suppression of white spots is desired. Here, in the ion implantation technique, it is difficult to form a deep hole accumulation region while maintaining the shallowness of the hole accumulation region. In addition, if a hole accumulation region that is too dark is formed, a strong electric field is generated at the interface between the hole accumulation region and the n-type region of the sensor unit, leading to an increase in white spots.

  From the viewpoint of improving the read characteristics, it is preferable to arrange the hole accumulation region with a space from the read gate (transfer gate). However, in this case, there is a problem that a region in which the hole accumulation region is not formed in the sensor unit causes white spots.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a solid-state imaging device capable of suppressing white spots and reducing noise, a manufacturing method thereof, and the solid-state imaging device. To provide a camera.

In order to achieve the above object, a solid-state imaging device of the present invention is formed on a substrate, and is formed on the substrate adjacent to the sensor unit, the first conductivity type sensor unit that accumulates signal charges, A transfer gate for transferring the signal charge accumulated in the sensor unit to the floating diffusion unit , and a hole accumulation region of a second conductivity type disposed on the surface layer in the sensor unit at a distance from the transfer gate And a buffer film having a film thickness of 5 to 15 nm formed to cover each upper part of the sensor part, the hole accumulation region, the transfer gate, and the floating diffusion part, and formed on the buffer film. , having a charge holding film for holding charges of the same polarity as the signal charge.

In order to achieve the above object, a solid-state imaging device of the present invention includes a step of forming a first conductivity type sensor portion on a substrate, and a step of forming a floating diffusion portion on the substrate apart from the sensor portion. , at a position adjacent to said sensor portion on the substrate, forming a transfer gate for transferring the signal charges accumulated in the sensor unit to the floating diffusion portion, a surface portion in said sensor unit, said transfer gate Forming a hole accumulation region of the second conductivity type with a space from each other, and a film so as to cover each upper part of the sensor portion, the hole accumulation region, the transfer gate, and the floating diffusion portion forming a buffer layer having a thickness 5 to 15 nm, on the buffer layer, forming a charge holding film for holding charges of the same polarity as the signal charge It has a that step.

In order to achieve the above object, a camera of the present invention includes a solid-state imaging device, an optical system that guides incident light to an imaging unit of the solid-state imaging device, and a signal processing circuit that processes an output signal of the solid-state imaging device. The solid-state imaging device includes a first conductivity type sensor unit that is formed on a substrate and accumulates signal charges, and a signal that is formed on the substrate adjacent to the sensor unit and accumulated in the sensor unit. A transfer gate for transferring charges to the floating diffusion portion; a surface layer portion in the sensor portion; a second conductivity type hole accumulation region disposed at a distance from the transfer gate; the sensor portion; hole accumulation region, the transfer gate and the floating diffusion portion is formed so as to cover the respective upper, a buffer film having a thickness of 5 to 15 nm, is formed on the buffer layer, A charge holding film for holding the same polarity charge as the serial signal charge, a solid-state imaging device having a.

  According to the present invention, it is possible to realize a solid-state imaging device and a camera that suppress white points and reduce noise.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of a configuration of an amplification type solid-state imaging device according to the present embodiment. In the present embodiment, for example, a MOS image sensor will be described as an example.

  The solid-state imaging device 10 includes a unit pixel 11 including a photodiode that is a photoelectric conversion element, a pixel array unit (imaging unit) 12 in which the pixels 11 are two-dimensionally arranged in a matrix, a vertical selection circuit 13, It has a column circuit 14 that is a signal processing circuit, a horizontal selection circuit 15, a horizontal signal line 16, an output circuit 17, and a timing generator (TG) 18.

  In the pixel array unit 12, a vertical signal line 121 is arranged for each column with respect to a matrix-like pixel arrangement. A specific circuit configuration of the unit pixel 11 will be described later.

  The vertical selection circuit 13 is configured by a shift register or the like. The vertical selection circuit 13 sequentially outputs control signals such as a transfer signal for driving the transfer transistor of the pixel 11 and a reset signal for driving the reset transistor in units of rows, thereby causing each pixel 11 in the pixel array unit 12 to be in units of rows. Select drive.

  The column circuit 14 is a signal processing circuit arranged for each pixel in the column direction of the pixel array unit 12, that is, for each vertical signal line 121. The column circuit 14 includes, for example, an S / H (sample hold) circuit and a CDS (Correlated Double Sampling) circuit.

  The horizontal selection circuit 15 is configured by a shift register or the like, and sequentially selects the signal of each pixel 11 output through the column circuit 14 and outputs it to the horizontal signal line 16. In FIG. 1, the horizontal selection switch is not shown for simplification of the drawing. The horizontal selection switch is sequentially turned on / off by the horizontal selection circuit 15 in units of columns.

  The signals of the unit pixels 11 that are sequentially output from the column circuit 14 for each column by the selection drive by the horizontal selection circuit 15 are supplied to the output circuit 17 through the horizontal signal line 16, and the output circuit 17 performs signal processing such as amplification. After being applied, it is output outside the device.

  The timing generator 18 generates various timing signals, and performs drive control of the vertical selection circuit 13, the column circuit 14, the horizontal selection circuit 15 and the like based on these various timing signals.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 11.

  The unit pixel 11A includes three transistors (active elements), for example, a transfer transistor 112, a reset transistor 113, and an amplification transistor 114 in addition to a photoelectric conversion element, for example, a photodiode 111. Here, for example, n-channel MOS transistors are used as the transistors 112 to 114.

  The transfer transistor 112 is connected between the cathode of the photodiode 111 and an FD (floating diffusion) portion 116. By applying a transfer pulse φTRG to the gate of the transfer transistor 112, photoelectric conversion is performed by the photodiode 111, and signal charges (here, electrons) accumulated therein are transferred to the FD unit 116.

  The reset transistor 113 has a drain connected to the selected power supply SELVDD and a source connected to the FD unit 116. Prior to the transfer of signal charges from the photodiode 111 to the FD unit 116, the potential of the FD unit 116 is reset by applying a φ reset pulse RST to the gate. The selected power supply SELVDD is a power supply that selectively takes a VDD level and a GND level as a power supply voltage.

  The amplification transistor 114 constitutes a source follower circuit in which a gate is connected to the FD unit 116, a drain is connected to the selection power supply SELVDD, and a source is connected to the vertical signal line 121. The amplification transistor 114 outputs the potential of the FD unit 116 after resetting by the reset transistor 113 to the vertical signal line 121 as a reset level, and further, the potential of the FD unit 116 after transferring the signal charge by the transfer transistor 112 is set to the signal level. To the vertical signal line 121.

  FIG. 3 is a circuit diagram illustrating another example of the circuit configuration of the unit pixel 11.

  The unit pixel 11B is a pixel circuit having four transistors, for example, a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115 in addition to a photoelectric conversion element, for example, a photodiode 111. Here, for example, n-channel MOS transistors are used as the transistors 112 to 115.

  The transfer transistor 112 is connected between the cathode of the photodiode 111 and an FD (floating diffusion) portion 116. By applying a transfer pulse φTRG to the gate of the transfer transistor 112, photoelectric conversion is performed by the photodiode 111, and signal charges (here, electrons) accumulated therein are transferred to the FD unit 116.

  The reset transistor 113 has a drain connected to the power supply VDD and a source connected to the FD unit 116. Prior to the transfer of the signal charge from the photodiode 111 to the FD unit 116, the potential of the FD unit 116 is reset by applying a reset pulse φRST to the gate of the reset transistor 113.

  The selection transistor 115 has, for example, a drain connected to the power supply VDD and a source connected to the drain of the amplification transistor 114. The selection transistor 115 is turned on when a selection pulse φSEL is applied to its gate, and the pixel 11B is selected by supplying the power supply VDD to the amplification transistor 114. The selection transistor 115 may be configured to be connected between the source of the amplification transistor 114 and the vertical signal line 121.

  The amplification transistor 114 forms a source follower circuit in which a gate is connected to the FD unit 116, a drain is connected to the source of the selection transistor 115, and a source is connected to the vertical signal line 121. The amplification transistor 114 outputs the potential of the FD unit 116 after resetting by the reset transistor 113 to the vertical signal line 121 as a reset level, and further, the potential of the FD unit 116 after transferring the signal charge by the transfer transistor 112 is set to the signal level. To the vertical signal line 121.

  In the unit transistor 11A having the three-transistor configuration and the unit pixel 11B having the four-transistor configuration, the signal charge obtained by photoelectric conversion by the photodiode 111 is transferred to the FD unit 116 by the transfer transistor 112, and the signal of the FD unit 116 is transmitted. An analog operation is performed in which a potential corresponding to the electric charge is amplified by the amplification transistor 114 and output to the vertical signal line 121.

  FIG. 4 is a main part plan view of a unit pixel of the solid-state imaging device according to the present embodiment. FIG. 5 is a cross-sectional view taken along the line A-A ′ of FIG. 4. In the present embodiment, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

  For example, a p-type region 21 made of a p-type well or a p-type epitaxial layer is formed on a semiconductor substrate 20 made of an n-type silicon substrate. An n-type sensor portion 22 is formed in the p-type region 21. A p-type hole accumulation region 23 is formed on the surface of the sensor unit 22. The sensor unit 22 corresponds to the photodiode 111 in FIGS.

  A transfer gate 24 of the transfer transistor 112 is formed on the semiconductor substrate 20 adjacent to the sensor unit 22 via a gate insulating film made of silicon oxide (not shown). The transfer gate 24 is made of polysilicon. An n-type region 25 is formed on the side opposite to the sensor unit 22, and an n-type FD unit 116 is formed so as to be connected to the n-type region 25. The n-type region 25 becomes a source / drain region of the transfer transistor 112.

  The hole accumulation region 23 is arranged with a space from the transfer gate 24. As a result, the read characteristics can be improved, and the read voltage (voltage of the transfer pulse φTRG) necessary for reading the signal charges accumulated in the sensor unit 22 can be lowered.

  A buffer film 30 made of, for example, silicon oxide is formed on the semiconductor substrate 20 so as to cover the transfer gate 24. On the buffer film 30, a charge holding film 31 that holds negative charges (electrons) in the film is formed. The charge holding film 31 is, for example, a silicon nitride film.

  A sidewall insulating film 32 made of, for example, a silicon oxide film is formed on the charge holding film 31 and on the side of the transfer gate 24. Although not shown, a silicon oxide film (corresponding to the buffer film 30), a silicon nitride film (corresponding to the charge holding film 31), and a silicon oxide film (side) are formed on the side walls of the gates of other transistors in the pixel array unit 12. A sidewall insulating film having a three-layer structure is formed.

  A protective film 33 is formed on the charge holding film 31. The protective film 33 is made of, for example, a silicon nitride film. The protective film 33 is formed by, for example, the LPCVD method. On the protective film 33, an interlayer insulating film 40 made of silicon oxide is formed.

  Although not shown, contacts and wirings are formed in the interlayer insulating film 40. A planarization layer, a color filter, a planarization layer, and an on-chip lens are formed on the interlayer insulating film 40.

  Next, effects of the solid-state imaging device according to the above-described embodiment will be described.

  In the present embodiment, a charge holding film 31 that holds a negative charge is formed on the sensor unit 22. The charge retention film 31 induces a hole accumulation layer in which many holes are accumulated near the interface between the semiconductor substrate 20 and the buffer film 30. Therefore, the dark current suppression effect of the hole accumulation region 23 can be enhanced, and white spots can be suppressed.

  Moreover, the generation of dark current from the surface region of the sensor unit 22 where the hole accumulation region 23 is not formed can be suppressed, and white spots can be suppressed. For this reason, in the present embodiment, the white point can be suppressed while the transfer gate 24 and the hole accumulation region 23 are separated to reduce the read voltage.

  The charge holding film 31 capable of holding charges is a film having defects. In order to suppress the generation of white spots due to the formation of the charge holding film 31 directly on the semiconductor substrate 20, a buffer film 30 made of silicon oxide is provided between the charge holding film 31 and the semiconductor substrate 20. Yes. In order to induce a hole accumulation layer on the surface layer of the semiconductor substrate 20 by the charge retention film 31, the buffer film 30 is preferably as thin as possible. The thickness of the buffer film 30 is 5 to 15 nm.

In the present embodiment, a protective film 33 is provided on the charge retention film 31. As will be described later, hydrogen annealing (also referred to as sinter annealing) is performed in the wiring layer formation step, so that the negative charge in the charge holding film 31 may be lost by hydrogen. By covering the charge holding film 31 with the protective film 33, intrusion of hydrogen (H ⁺ ) can be prevented, and neutralization of negative charges due to hydrogen can be prevented.

  The buffer film 30 and the charge holding film 31 can be formed of other materials. However, by forming a silicon nitride film as the charge holding film 31 on the buffer film 30 made of silicon oxide, the charge holding film 31 also functions as an antireflection film. As a result, the sensitivity of the pixel can be improved.

  Further, by using silicon nitride, which is also used for nonvolatile memories such as MONOS, as the charge holding film 31, the charge holding film 31 in which more negative charges are accumulated can be formed. The charge holding film 31 can have a charge amount of about −1 V, for example.

  Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 6A, for example, a p-type region 21 is formed on a semiconductor substrate 20 made of n-type silicon. The p-type region 21 is, for example, a p-well formed by ion implantation or a p-type epitaxial layer formed by epitaxial growth. Subsequently, the sensor portion 22, the FD portion 116, and the n-type region 25 are formed in the p-type region 21 by an ion implantation technique. Subsequently, a transfer gate 24 is formed on the semiconductor substrate 20 by depositing and patterning a polysilicon film. Subsequently, a p-type hole accumulation region 23 is formed in a region within the sensor unit 22 and away from the transfer gate 24 by an ion implantation technique. Thus, the photodiode 111, the FD portion 116, and the transfer transistor 112 are formed on the semiconductor substrate 20. Note that other transistors are also formed in a region not shown.

  Next, as shown in FIG. 6B, a buffer film 30 made of silicon oxide is formed on the semiconductor substrate 20 so as to cover the transfer transistor 112. The buffer film 30 is formed by, for example, a thermal oxidation method or a CVD method.

  Next, as shown in FIG. 6C, a charge retention film 31 is formed on the buffer film 30. For example, a silicon nitride film is formed as the charge holding film 31. A method for forming the charge retention film 31 will be described below.

  For example, the charge retention film 31 can be formed by depositing a silicon nitride film by plasma CVD or LPCVD and then irradiating with ultraviolet rays. This is because the electrons on the surface layer of the semiconductor substrate 20 are excited by the ultraviolet irradiation, and the excited electrons jump over the buffer film 30 and are captured by the charge holding film 31.

  Alternatively, after depositing the silicon nitride film, the positively charged electrodes are made to face each other, thereby exciting the electrons on the surface layer of the semiconductor substrate 20 and injecting the excited electrons into the charge holding film 31.

Alternatively, the charge holding film 31 having a negative charge can be formed by performing plasma irradiation or plasma nitriding after depositing the silicon nitride film. Furthermore, by controlling the conditions of the plasma CVD method, a silicon nitride film containing a large amount of hydrogen is formed, the hydrogen in the film is eliminated by a base (or annealing), and a charge having a negative charge (OH ⁻ ) in the film The holding film 31 can also be formed.

  Next, as illustrated in FIG. 7A, a sidewall insulating film 32 is formed on the sidewall of the transfer gate 24 by depositing and etching back a silicon oxide film.

  Next, as shown in FIG. 7B, a protective film 33 is formed on the charge retention film 31. As the protective film 33, a silicon nitride film is formed by LPCVD.

  After forming the protective film 33, a wiring layer is formed. FIG. 5 illustrates only the interlayer insulating film 40 constituting the wiring layer. After forming the wiring layer, a hydrogen annealing process is performed. In the present embodiment, since the protective film 33 is formed on the charge holding film 31, it is possible to prevent the negative charge in the charge holding film 31 from being neutralized by hydrogen.

  After the wiring layer is formed, a solid-state imaging device is completed by forming a planarizing film, a color filter, a planarizing film, and an on-chip lens.

  As described above, according to the method for manufacturing a solid-state imaging device according to the present embodiment, it is possible to manufacture a solid-state imaging device with reduced white spots without increasing the number of manufacturing steps.

  The solid-state imaging device is used for a camera such as a video camera, a digital still camera, or an electronic endoscope camera, for example.

  FIG. 8 is a schematic configuration diagram of a camera in which the solid-state imaging device is used.

  The camera 50 includes the solid-state imaging device 10 described above, an optical system 51, and a signal processing circuit 53.

  The optical system 51 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 10. Thereby, in the sensor unit 22 of the solid-state imaging device 10, incident light is converted into signal charges corresponding to the amount of incident light, and the signal charges are accumulated in the sensor unit 22 for a certain period.

  The signal processing circuit 53 performs various signal processing on the output signal of the solid-state imaging device 10 and outputs it as a video signal.

  According to the camera including the solid-state imaging device according to the present embodiment, it is possible to realize a camera that reduces white spots.

The present invention is not limited to the description of the above embodiment.
For example, the hole accumulation region 23 may not be provided. Further, the layer configuration is not limited as long as the charge holding film 31 is formed on the sensor unit 22. 9 and 10 are cross-sectional views of modified examples of the solid-state imaging device according to the present embodiment.

  As shown in FIG. 9, a sidewall insulating film 32 may be formed on the buffer film 30, and the charge holding film 31 may be formed so as to cover the sidewall insulating film 32. Note that the protective film 33 described in the first embodiment may be formed on the charge holding film 31.

Further, as shown in FIG. 10, the charge holding film 31 is preferably formed only on the sensor unit 22. By providing the sensor portion 22 only, the charge holding film 31 is in a floating state, and can hold charges stably for a long period of time. Further, the contact between the charge holding film 31 and a contact (not shown) can be prevented, and there is no possibility that the charge of the charge holding film 31 affects the operation. The charge holding film 31 described in the first embodiment is also preferably formed only on the sensor unit 22.
In addition, various modifications can be made without departing from the scope of the present invention.

It is a block diagram which shows an example of a structure of the solid-state imaging device which concerns on this embodiment. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is a circuit diagram which shows the other example of the circuit structure of a unit pixel. It is a principal part top view of the unit pixel of the solid-state imaging device concerning this embodiment. It is sectional drawing in the A-A 'line | wire of FIG. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is process sectional drawing in manufacture of the solid-state imaging device which concerns on this embodiment. It is a block diagram which shows the structure of the camera with which the solid-state imaging device which concerns on this embodiment is applied. It is sectional drawing which shows the modification of the solid-state imaging device which concerns on this embodiment. It is sectional drawing which shows the modification of the solid-state imaging device which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device 11, 11A, 11B ... Unit pixel, 12 ... Pixel array part, 13 ... Vertical selection circuit, 14 ... Column circuit, 15 ... Horizontal selection circuit, 16 ... Horizontal signal line, 17 ... Output circuit, 18 ... Timing generator (TG), 20 ... Semiconductor substrate, 21 ... p-type region, 22 ... Sensor part, 23 ... Hole accumulation region, 24 ... Transfer gate, 25 ... N-type region, 30 ... Buffer film, 31 ... Charge retention Film 32, sidewall insulating film 33, protective film 40, interlayer insulating film 111, photodiode, 112 transfer transistor 113 reset transistor 114 amplification transistor 115 selection transistor 116 FD section

Claims (6)

A first conductivity type sensor unit that is formed on the substrate and accumulates signal charges;
A transfer gate formed on the substrate adjacent to the sensor unit and transferring the signal charge accumulated in the sensor unit to a floating diffusion unit ;
A hole accumulation region of a second conductivity type disposed in a surface layer portion in the sensor portion with a distance from the transfer gate;
A buffer film having a film thickness of 5 to 15 nm, formed so as to cover each upper part of the sensor unit, the hole accumulation region, the transfer gate, and the floating diffusion unit;
Wherein formed on the buffer layer, having a charge holding film for holding charges of the same polarity as the signal charge,
Solid-state imaging device. A protective film that is formed on the charge retention film and suppresses intrusion of hydrogen into the charge retention film ;
The solid-state imaging device according to claim 1. The charge holding film is formed over the buffer layer only on the upper portion of the sensor unit,
The solid-state imaging device according to claim 1. Forming a first conductivity type sensor portion on a substrate;
Forming a floating diffusion part on the substrate apart from the sensor part;
Forming a transfer gate for transferring signal charges accumulated in the sensor unit to the floating diffusion unit at a position adjacent to the sensor unit on the substrate;
Forming a hole accumulation region of a second conductivity type in a surface layer portion in the sensor portion with a space from the transfer gate;
Forming a buffer film having a film thickness of 5 to 15 nm so as to cover each upper part of the sensor unit, the hole accumulation region, the transfer gate, and the floating diffusion unit;
On the buffer layer, and a step of forming a charge holding film for holding charges of the same polarity as the signal charge,
Manufacturing method of solid-state imaging device. Forming a protective film on the charge retention film;
After forming the protective layer further comprises a step of applying hydrogen annealing to form the wiring layer,
The manufacturing method of the solid-state imaging device of Claim 4 . A solid-state imaging device;
An optical system for guiding incident light to the imaging unit of the solid-state imaging device;
A signal processing circuit for processing an output signal of the solid-state imaging device,
The solid-state imaging device
A first conductivity type sensor unit that is formed on the substrate and accumulates signal charges;
A transfer gate formed on the substrate adjacent to the sensor unit and transferring the signal charge accumulated in the sensor unit to a floating diffusion unit ;
A hole accumulation region of a second conductivity type disposed in a surface layer portion in the sensor portion with a distance from the transfer gate;
A buffer film having a film thickness of 5 to 15 nm, formed so as to cover each upper part of the sensor unit, the hole accumulation region, the transfer gate, and the floating diffusion unit;
Wherein formed on the buffer film, a solid-state imaging device having a charge holding film for holding charges of the same polarity as the signal charge,
camera.

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