JP2535701B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2535701B2 JP2535701B2 JP4071686A JP7168692A JP2535701B2 JP 2535701 B2 JP2535701 B2 JP 2535701B2 JP 4071686 A JP4071686 A JP 4071686A JP 7168692 A JP7168692 A JP 7168692A JP 2535701 B2 JP2535701 B2 JP 2535701B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxygen concentration
- silicon substrate
- semiconductor device
- interstitial oxygen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 72
- 239000001301 oxygen Substances 0.000 claims description 72
- 229910052760 oxygen Inorganic materials 0.000 claims description 72
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 33
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 13
- 239000000155 melt Substances 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 description 15
- 238000001556 precipitation Methods 0.000 description 15
- 230000007547 defect Effects 0.000 description 11
- 239000012535 impurity Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 9
- 125000004430 oxygen atom Chemical group O* 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000002411 adverse Effects 0.000 description 4
- 238000005247 gettering Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 150000002926 oxygen Chemical class 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001376 precipitating effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B13/00—Single-crystal growth by zone-melting; Refining by zone-melting
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/928—Active solid-state devices, e.g. transistors, solid-state diodes with shorted PN or schottky junction other than emitter junction
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置、特に引上げ
法（ＣＺ法）若しくは融液浮遊法（ＦＺ法）によって製
造されたシリコンゴッドから切り出されたシリコン基板
を用いた半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a silicon substrate cut out from a silicon god manufactured by a pulling method (CZ method) or a melt floating method (FZ method).
【０００２】[0002]
【従来の技術】現在、シリコン基板を用いた半導体装置
では、チョクラルスキー引上げ法（ＣＺ法）で製造され
た半導体ウェーハ（以下、ＣＺウェーハという）が一般
に使用されている。このＣＺウェーハには、シリコンを
石英るつぼから引き上げる時に酸素が溶け込むため、酸
素が常温で過飽和状態に含まれており、この過剰な酸素
原子は、半導体装置製造プロセス中の熱処理により、例
えばＳｉＯ2 という形で析出される。2. Description of the Related Art At present, in a semiconductor device using a silicon substrate, a semiconductor wafer manufactured by the Czochralski pulling method (CZ method) (hereinafter referred to as a CZ wafer) is generally used. This CZ wafer contains oxygen in a supersaturated state at room temperature because oxygen dissolves when silicon is pulled out from the quartz crucible. The excess oxygen atoms are called, for example, SiO 2 by heat treatment during the semiconductor device manufacturing process. Deposited in shape.
【０００３】前記シリコン中に含まれる酸素原子は、Ｃ
Ｚウェーハの機械的強度の向上に役立ち、また上述の如
く析出することでデバイスに有害な金属不純物を捕獲
（ゲッタリング）すると言われているため、ＣＺウェー
ハの製造時に適切な格子間酸素濃度となるように制御す
ることが一般に行われている。The oxygen atom contained in the silicon is C
It is said to help improve the mechanical strength of the Z wafer and to capture (getter) metal impurities harmful to the device by precipitating as described above. It is generally performed to control so that
【０００４】しかしながら、デバイス活性領域であるＣ
Ｚウェーハのデバイス作製側表面の近傍で酸素が析出さ
れると、ＯＳＦ（Oxidation induced Stacking Fault）
等の結晶欠陥やＣＺウェーハ上に積層された酸化膜の不
良の発生等、デバイスに悪影響を及ぼしてしまう。However, the device active region C
When oxygen is deposited near the surface of the Z wafer on which the device is manufactured, OSF (Oxidation induced Stacking Fault) occurs.
And other defects such as crystal defects and defects in the oxide film laminated on the CZ wafer are adversely affected.
【０００５】このために、ＣＺウェーハのデバイス作製
側の表面近傍で酸素原子の析出が生じないよう、予めシ
リコン基板の表面近傍の格子間酸素濃度を酸素原子析出
が生じない程度まで低下させることが行われている。For this reason, the interstitial oxygen concentration in the vicinity of the surface of the silicon substrate may be lowered in advance so that the precipitation of oxygen atoms does not occur in the vicinity of the surface of the CZ wafer on the device manufacturing side. Has been done.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、予めシ
リコン基板の表面近傍の格子間酸素濃度を酸素原子の析
出が生じない程度まで、即ち例えば最表面の酸素濃度が
７×１０17cm-3（旧ＡＳＴＭ換算、以下同じ）程度とな
るまで低下させたとしも、格子間酸素濃度の基板の深さ
方向に沿った分布を見ると、デバイス活性領域若しくは
デバイスの動作に影響を及ぼす表面より１０μｍ程度の
深さ領域では、１×１０18cm-3以上の酸素濃度となって
おり、密度は低いものの、酸素析出が生ずるのに充分な
格子間酸素原子が存在している。However, the interstitial oxygen concentration in the vicinity of the surface of the silicon substrate is reduced to a level at which oxygen atom precipitation does not occur, that is, for example, the oxygen concentration on the outermost surface is 7 × 10 17 cm -3 (old). Even if it is lowered to about the same level (ASTM equivalent), the distribution of the interstitial oxygen concentration along the depth direction of the substrate shows that it is about 10 μm from the device active region or the surface affecting the device operation. In the depth region, the oxygen concentration is 1 × 10 18 cm −3 or more, and although the density is low, there are sufficient interstitial oxygen atoms for oxygen precipitation.
【０００７】更に、Ｆｅ等の金属不純物がデバイス作製
プロセス時にシリコン基板中に侵入した場合、これらの
金属不純物により酸素析出の臨界濃度が低下するため、
上記酸素濃度では酸素析出を抑えるのに不十分な濃度と
なり、シリコン基板の最表面だけでなく、デバイスの動
作に影響を与える深さ領域の範囲内においても、充分に
低い酸素濃度にする必要があるのが現状であった。Further, when metallic impurities such as Fe enter the silicon substrate during the device manufacturing process, the critical concentration of oxygen precipitation is lowered by these metallic impurities.
The above oxygen concentration is insufficient to suppress oxygen precipitation, and it is necessary to make the oxygen concentration sufficiently low not only on the outermost surface of the silicon substrate but also within the range of the depth region that affects the operation of the device. It was the current situation.
【０００８】なお、シリコン基板の表面にシリコンの単
結晶半導体層を均一にエピタキシャル成長させた、いわ
ゆるエピタキシャルウェーハにおいては、エピタキシャ
ル層における酸度濃度が低く、酸素析出を抑えるのに十
分な酸素濃度となっているが、このウェーハは一般に製
造コストがかなり高いばかりでなく、その製造に高度な
技術が必要となってしまう。In a so-called epitaxial wafer in which a silicon single crystal semiconductor layer is uniformly epitaxially grown on the surface of a silicon substrate, the acidity concentration in the epitaxial layer is low, and the oxygen concentration is sufficient to suppress oxygen precipitation. However, this wafer is not only considerably expensive to manufacture, but also requires high technology for its manufacture.
【０００９】さらに格子間酸素濃度が低いと熱応力など
に対する耐力が低下するため、エピタキシャルウェハー
やＦＺウェハーではＣＺウェハーに比べて強度が劣るた
めにデバイスの動作に悪影響を与える転位やスリップな
どの欠陥が発生しやすい。Further, when the interstitial oxygen concentration is low, the proof stress against thermal stress and the like is lowered. Therefore, the epitaxial wafer and the FZ wafer are inferior in strength to the CZ wafer, and therefore defects such as dislocations and slips which adversely affect the operation of the device. Is likely to occur.
【００１０】本発明は上記問題に鑑み、デバイスへ悪影
響を及ぼす金属不純物のゲッタリング効果をもち、かつ
デバイスの動作に対して影響のない酸素濃度分布構造を
もつ半導体装置を提供することを目的とする。In view of the above problems, it is an object of the present invention to provide a semiconductor device having an oxygen concentration distribution structure which has a gettering effect of metal impurities which adversely affect the device and which does not affect the operation of the device. To do.
【００１１】[0011]
【課題を解決するための手段】本発明は、引上げ法若し
くは融液浮遊法によって製造されたシリコンインゴット
から切り出されたシリコン基板を用いて作製された半導
体装置において、前記シリコン基板を用いて作製された
作製後のシリコン基板のデバイス作製側表面より約１０
μｍまでの深さ領域内であって前記表面以外の部分に格
子間酸素濃度の最小値があり、デバイス作製側表面より
１０μｍの深さより深い領域に格子間酸素濃度の最大値
があり、このため前記表面における格子間酸素濃度は前
記最小値と前記最大値との間の値をとることを特徴とす
る半導体装置である。The present invention is a semiconductor device manufactured by using a silicon substrate cut out from a silicon ingot manufactured by a pulling method or a melt floating method, and is manufactured by using the silicon substrate. Approximately 10 from the device fabrication side surface of the fabricated silicon substrate
Within the depth region up to μm, the interstitial oxygen concentration has a minimum value in a region other than the surface, and the interstitial oxygen concentration has a maximum value in a region deeper than 10 μm from the device fabrication side surface. The semiconductor device is characterized in that the interstitial oxygen concentration on the surface has a value between the minimum value and the maximum value.
【００１２】[0012]
【作用】しかして本願発明によれば、作製後の半導体装
置において、デバイスの動作に影響を与えるシリコン基
板のデバイス作製側表面より約１０μｍまでの深さ領域
内であって表面以外の部分に格子間酸素濃度の最小値が
あるので、半導体装置の製造プロセスにおいてこの領域
内に酸素が析出することはない。またデバイス作製側表
面より１０μｍの深さより深い領域に格子間酸素濃度の
最大値があるので、この領域においては酸素の析出によ
る金属不純物のゲッタリング効果が期待できる。さらに
デバイス作製側表面における格子間酸素は、上記最小値
と上記最大値との間の値をとるので、表面にある程度の
格子間酸素を存在させて結晶欠陥の発生を未然に防止す
ることができる。According to the present invention, however, in the semiconductor device after fabrication, the lattice is formed in a region other than the surface within a depth region of up to about 10 μm from the device fabrication side surface of the silicon substrate which affects the operation of the device. Since there is a minimum value of the oxygen concentration during the period, oxygen is not deposited in this region in the semiconductor device manufacturing process. Further, since the interstitial oxygen concentration has a maximum value in a region deeper than 10 μm deep from the device fabrication side surface, a gettering effect of metal impurities due to oxygen precipitation can be expected in this region. Further, the interstitial oxygen on the surface of the device fabrication side takes a value between the above-mentioned minimum value and the above-mentioned maximum value, so that it is possible to prevent the occurrence of crystal defects by allowing interstitial oxygen to a certain extent on the surface. .
【００１３】さらに表面の格子間酸素濃度が５×１０17
cm-3（旧ＡＳＴＭ換算）を越える場合は前記熱応力に対
する耐力の向上の効果がみられる。Further, the interstitial oxygen concentration on the surface is 5 × 10 17.
When it exceeds cm -3 (formerly known as ASTM), the effect of improving the proof stress against the thermal stress is observed.
【００１４】[0014]
【実施例】以下、本発明の一実施例を説明する。なお、
本実施例では、チョクラルスキー引上げ法によって製造
されたシリコンインゴットから切り出されたシリコン基
板を用いた例を示しているが、融液浮遊法によって製造
されたシリコンインゴットから切り出されたシリコン基
板についても同様である。EXAMPLE An example of the present invention will be described below. In addition,
In this embodiment, an example using a silicon substrate cut out from a silicon ingot manufactured by the Czochralski pulling method is shown, but a silicon substrate cut out from a silicon ingot manufactured by the melt floating method is also used. It is the same.
【００１５】先ず、チョクラルスキー引上げ法によっ
て、シリコンインゴットを製作し、このインゴットから
所定の厚さのシリコン基板を切り出す。そして、デバイ
ス製造の第１工程として、このシリコン基板を高純度の
水素ガス１００％雰囲気中で、例えば１１５０℃の温度
で４時間に亘るアニールを施し、以後従来と同様のＣＭ
ＯＳ製造工程を経て半導体装置を得る。First, a silicon ingot is manufactured by the Czochralski pulling method, and a silicon substrate having a predetermined thickness is cut out from this ingot. Then, as a first step of device manufacturing, this silicon substrate is annealed in a high-purity 100% hydrogen gas atmosphere at a temperature of, for example, 1150 ° C. for 4 hours, and thereafter, the same CM as the conventional one is used.
A semiconductor device is obtained through an OS manufacturing process.
【００１６】このように、シリコンインゴットから切り
出されたシリコン基板を水素ガスの還元性雰囲気で処理
すると、シリコン基板表面の酸素原子が水素と反応して
シリコン基板表面の酸素濃度がほぼゼロとなり、この結
果、酸素原子の外方拡散が促進されるために、上記熱処
理直後の格子間酸素濃度の状況は図１に実線で示す如く
表面で最も低い形となる。Thus, when the silicon substrate cut out from the silicon ingot is treated in a reducing atmosphere of hydrogen gas, oxygen atoms on the surface of the silicon substrate react with hydrogen, and the oxygen concentration on the surface of the silicon substrate becomes almost zero. As a result, since the outward diffusion of oxygen atoms is promoted, the interstitial oxygen concentration immediately after the heat treatment is the lowest on the surface as shown by the solid line in FIG.
【００１７】ここに、デバイスに最も有害な金属元素の
一つであるＦｅは、低温でシリコン基板中の酸素原子と
結合して酸素の析出核となることが知られており、デバ
イス活性領域及び該領域に影響を及ぼす領域に酸素原子
の析出が発生すると、デバイスの不良原因となる可能性
が著しく高まる。即ち、上記領域にＦｅと過飽和な酸素
が存在すると酸素析出が加速することになり、これを防
ぐには、上記領域に過飽和酸素の存在をなくすことが有
効である。Here, it is known that Fe, which is one of the most harmful metal elements for devices, combines with oxygen atoms in the silicon substrate to form oxygen precipitation nuclei at low temperatures. If oxygen atom precipitation occurs in a region that influences the region, the possibility of causing a device defect is significantly increased. That is, if Fe and supersaturated oxygen are present in the above region, oxygen precipitation is accelerated, and in order to prevent this, it is effective to eliminate the presence of supersaturated oxygen in the above region.
【００１８】そこで、前述のようにシリコン基板に水素
ガス雰囲気によるアニールを施すことによって、上記領
域に過飽和な酸素が存在することをなくすとともに、か
かる領域に存在するＦｅ原子を降温時に外方に拡散させ
て表面に析出させることができる。Therefore, by annealing the silicon substrate in a hydrogen gas atmosphere as described above, supersaturated oxygen does not exist in the above region, and Fe atoms existing in the region are diffused outward when the temperature is lowered. And can be deposited on the surface.
【００１９】このような格子間酸素濃度の分布をもつ半
導体装置であれば、シリコン基板中に金属不純物が存在
していたとしても、デバイス活性領域及び該領域に影響
を及ぼす領域の格子間酸素濃度が酸素析出を生じせしめ
るほど高くないため、デバイスの製造歩留を大幅に改善
することができる。In the semiconductor device having such a distribution of interstitial oxygen concentration, even if metal impurities are present in the silicon substrate, the interstitial oxygen concentration of the device active region and the region affecting the region is affected. Is not high enough to cause oxygen precipitation, so the manufacturing yield of devices can be significantly improved.
【００２０】図１の破線は、半導体装置作製後における
シリコン基板表面の格子間酸素濃度を示すもので、この
濃度の最小値は、シリコン基板のデバイス作製側表面よ
り、例えば１μｍ程度の深さ領域に存在する。この最小
値より表面側の酸素は、デバイス作製時の熱処理工程で
拡散により入ってきた分であり、酸素析出物が成長する
温度では上記領域の格子間酸素は過飽和状態となってい
ないために、析出が進行しないことによる。The broken line in FIG. 1 shows the interstitial oxygen concentration on the surface of the silicon substrate after the semiconductor device is manufactured. The minimum value of this concentration is, for example, about 1 μm from the surface of the silicon substrate on the device manufacturing side. Exists in. Oxygen on the surface side from this minimum value is the amount that has entered by diffusion in the heat treatment step during device fabrication, and because interstitial oxygen in the above region is not in a supersaturated state at the temperature at which oxygen precipitates grow, This is because precipitation does not proceed.
【００２１】即ち、図１中のＡで示された熱処理時の酸
素の固溶限より格子間酸素濃度が低い領域、例えばデバ
イス活性領域及び該領域に影響を及ぼす領域では酸素が
析出しないため、デバイスに悪影響を及ぼさず、またよ
り深い領域では酸素が析出するため金属不純物のゲッタ
リング効果が期待できることになる。That is, since oxygen does not precipitate in the region shown by A in FIG. 1 where the interstitial oxygen concentration is lower than the solid solubility limit of oxygen during the heat treatment, for example, the device active region and the region affecting the region, It does not adversely affect the device, and since oxygen is precipitated in a deeper region, a gettering effect of metal impurities can be expected.
【００２２】図２は、シリコン基板のデバイス作製面表
面から深さ１０μｍ以内における最小格子間酸素濃度と
デバイス歩留との関係を調べたものである。格子間酸素
濃度の最小値は、上記デバイス作製表面より１μｍの深
さの領域に存在していた。FIG. 2 shows the relationship between the minimum interstitial oxygen concentration and the device yield within a depth of 10 μm from the surface of the device fabrication surface of the silicon substrate. The minimum value of interstitial oxygen concentration was present in a region 1 μm deep from the device fabrication surface.
【００２３】これにより、シリコン基板の表面より約１
０μｍの深さ領域に、格子間酸素濃度が５×１０１７ｃ
ｍ−３以下となる領域が存在するようにすることによ
り、歩留まりの向上を図ることができることが判る。As a result, the surface area of the silicon substrate is about 1
The interstitial oxygen concentration is 5 × 10 17 c in the depth region of 0 μm.
It can be seen that the yield can be improved by allowing the region having m −3 or less to exist.
【００２４】これは、従来の一般的な格子間酸素濃度分
布をもつ半導体装置（図３(a) 参照）では、最表面のみ
が酸素の非飽和領域であり、実際上飽和温度が低いため
ＤＺなる酸素析出の存在しない領域が発生するが、上述
の如く金属不純物の侵入があった場合、上記ＤＺに酸素
の析出が発生するため、金属汚染に対し敏感なデバイス
となって歩留が向上しないが、本実施例における格子間
酸素濃度分布をもつ半導体装置（図３(c) 参照）では、
上述の如く金属不純物の侵入があった場合にも酸素の析
出が発生しないためである。This is because in the conventional semiconductor device having a general interstitial oxygen concentration distribution (see FIG. 3 (a)), only the outermost surface is an unsaturated region of oxygen, and the saturation temperature is actually low, so that DZ However, when a metal impurity invades, as described above, oxygen precipitation occurs in the DZ, which makes the device sensitive to metal contamination and does not improve the yield. However, in the semiconductor device having the interstitial oxygen concentration distribution in this embodiment (see FIG. 3C),
This is because the precipitation of oxygen does not occur even when the metal impurities enter as described above.
【００２５】なお、図３は、上記従来例におけるＣＺウ
ェーハを用いた半導体装置（ＣＭＯＳデバイス）と、上
記従来例におけるエピタキシャルウェーハを用いた半導
体装置（同）と、上記実施例によって作製した半導体装
置（同）におけるシリコン基板内の格子間酸素濃度分布
をそれぞれ(a) 〜(c) として示すものである。Incidentally, FIG. 3 shows a semiconductor device (CMOS device) using the CZ wafer in the above conventional example, a semiconductor device using the epitaxial wafer in the above conventional example (the same), and a semiconductor device manufactured by the above example. The distributions of interstitial oxygen concentration in the silicon substrate in (the same) are shown as (a) to (c), respectively.
【００２６】図４は、ＣＣＤデバイスの白キズ歩留、Ｄ
ＲＡＭのポーズ不良歩留及びＭＲＯＭのＯＳＦ（結晶表
面欠陥）密度について、上記従来例における格子間酸素
濃度分布をもつ半導体装置（図３(a) 参照）と、上記実
施例によって作製した格子間酸素濃度分布をもつ半導体
装置（図３(c) 参照）とを比較したものであり、３例と
も従来の酸素分布構造に比べて、本実施例の酸素分布構
造が有効であることを示している。FIG. 4 is a white defect yield of the CCD device, D
Regarding the pause defect yield of the RAM and the OSF (crystal surface defect) density of the MROM, the semiconductor device having the interstitial oxygen concentration distribution in the above conventional example (see FIG. 3A) and the interstitial oxygen produced in the above example. This is a comparison with a semiconductor device having a concentration distribution (see FIG. 3 (c)), and it is shown that the oxygen distribution structure of this embodiment is more effective than the conventional oxygen distribution structure in all three cases. .
【００２７】このように、格子間酸素濃度がデバイス作
成側表面より深さ１０μｍまでの領域内に５×１０17at
oms ／cm3 以下の最小値を持つ分布を示すように制御す
ることで、図４に示す如く高い歩留が得られることが判
る。In this way, the interstitial oxygen concentration is 5 × 10 17 at in the region from the surface of the device formation side to a depth of 10 μm.
It can be seen that a high yield can be obtained as shown in FIG. 4 by controlling so that the distribution has a minimum value of oms / cm 3 or less.
【００２８】なお、上記格子間酸素濃度分布を得る手段
として、上述の条件の他に、１００％高純度水素ガス雰
囲気中で、１２００℃の温度で１時間、高純度のＡｒガ
ス１００％雰囲気中で、１１００℃の温度で４時間、ま
たは上記水素ガスとＡｒガスの混合気体中で、１１００
℃の温度で４時間に亘るアニールを施しても、同様な格
子間酸素分布構造が得られることが確認されている。As means for obtaining the above interstitial oxygen concentration distribution, in addition to the above conditions, in a 100% high purity hydrogen gas atmosphere, at a temperature of 1200 ° C. for 1 hour, in a high purity Ar gas 100% atmosphere. At a temperature of 1100 ° C. for 4 hours or in a mixed gas of the above hydrogen gas and Ar gas at 1100 ° C.
It has been confirmed that a similar interstitial oxygen distribution structure can be obtained even when annealing is performed at a temperature of ° C for 4 hours.
【００２９】[0029]
【発明の効果】しかして本願発明によれば、作製後の半
導体装置において、デバイスの動作に影響を与えるシリ
コン基板のデバイス作製側表面より約１０μｍまでの深
さ領域内であって表面以外の部分に格子間酸素濃度の最
小値があるので、半導体装置の製造プロセスにおいてこ
の領域内に酸素が析出することはない。またデバイス作
製側表面より１０μｍの深さより深い領域に格子間酸素
濃度の最大値があるので、この領域においては酸素の析
出による金属不純物のゲッタリン効果が期待できる。さ
らにデバイス作製側表面における格子間酸素は、上記最
小値と上記最大値との間の値をとるので、表面にある程
度の格子間酸素を存在させて結晶欠陥の発生を未然に防
止することができる。このため、半導体装置の誤動作を
防止して、高い製品歩留まりを得ることができる。According to the present invention, however, in a semiconductor device after fabrication, a portion other than the surface within a depth region up to about 10 μm from the device fabrication side surface of the silicon substrate that affects the operation of the device. Since the interstitial oxygen concentration has the minimum value, oxygen is not deposited in this region in the semiconductor device manufacturing process. Further, since the interstitial oxygen concentration has a maximum value in a region deeper than 10 μm deep from the device fabrication side surface, a gettering effect of metal impurities due to oxygen precipitation can be expected in this region. Further, the interstitial oxygen on the surface of the device fabrication side takes a value between the above-mentioned minimum value and the above-mentioned maximum value, so that it is possible to prevent the occurrence of crystal defects by allowing interstitial oxygen to a certain extent on the surface. . Therefore, a malfunction of the semiconductor device can be prevented and a high product yield can be obtained.
【図１】還元性雰囲気中で熱処理を施したシリコン基板
表面近傍の格子間酸素濃度分布を示すグラフ。FIG. 1 is a graph showing an interstitial oxygen concentration distribution near the surface of a silicon substrate that has been heat-treated in a reducing atmosphere.
【図２】デバイス表面から深さ１０μｍ以内における最
小格子間酸素濃度とデバイス歩留との関係を示すグラ
フ。FIG. 2 is a graph showing the relationship between the minimum interstitial oxygen concentration and the device yield within a depth of 10 μm from the device surface.
【図３】従来例及び本実施例のＣＭＯＳデバイスのシリ
コン基板内の格子間酸素濃度分布を示すグラフ。FIG. 3 is a graph showing interstitial oxygen concentration distributions in the silicon substrate of the CMOS devices of the conventional example and the present example.
【図４】ＣＣＤの白キズ歩留、ＤＲＡＭのポーズ不良歩
留及びＭＲＯＭのＯＳＦ密度の従来例と本実施例と比較
を示すグラフ。FIG. 4 is a graph showing a comparison between a white defect yield of CCD, a defective pause yield of DRAM, and an OSF density of MROM in the conventional example and this example.
Claims (3)
されたシリコンインゴットから切り出されたシリコン基
板を用いて作製された半導体装置において、前記シリコ
ン基板を用いて作製された作製後のシリコン基板のデバ
イス作製側表面より約１０μｍまでの深さ領域内であっ
て前記表面以外の部分に格子間酸素濃度の最小値があ
り、デバイス作製側表面より１０μｍの深さより深い領
域に格子間酸素濃度の最大値があり、このため前記表面
における格子間酸素濃度は前記最小値と前記最大値との
間の値をとることを特徴とする半導体装置。1. A semiconductor device manufactured by using a silicon substrate cut out from a silicon ingot manufactured by a pulling method or a melt floating method, and a device of the manufactured silicon substrate manufactured by using the silicon substrate. The interstitial oxygen concentration has a minimum value in a region up to about 10 μm from the fabrication side surface, except for the surface, and the interstitial oxygen concentration has a maximum value in a region deeper than 10 μm from the device fabrication side surface. Therefore, the interstitial oxygen concentration on the surface has a value between the minimum value and the maximum value.
い領域に、格子間酸素濃度が１．２×１０18cm-3（旧Ａ
ＳＴＭ換算）以上となる領域が存在するようにしたこと
を特徴とする請求項１記載の半導体装置。2. An interstitial oxygen concentration of 1.2 × 10 18 cm −3 (former A) in a region deeper than a depth region of about 10 μm from the surface.
2. The semiconductor device according to claim 1, wherein a region having a size equal to or more than STM) is present.
cm-3（旧ＡＳＴＭ換算）以下であることを特徴とする請
求項１記載の半導体装置。3. The minimum value of the interstitial oxygen concentration is 5 × 10 17
The semiconductor device according to claim 1, wherein the semiconductor device has a cm -3 (formerly ASTM) conversion or less.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071686A JP2535701B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
| KR1019930004773A KR960016219B1 (en) | 1992-03-27 | 1993-03-26 | Semiconductor device and method of producing the same |
| US08/357,351 US5574307A (en) | 1992-03-27 | 1994-12-16 | Semiconductor device and method of producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071686A JP2535701B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0636979A JPH0636979A (en) | 1994-02-10 |
| JP2535701B2 true JP2535701B2 (en) | 1996-09-18 |
Family
ID=13467690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4071686A Expired - Lifetime JP2535701B2 (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5574307A (en) |
| JP (1) | JP2535701B2 (en) |
| KR (1) | KR960016219B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017076772A (en) * | 2015-06-12 | 2017-04-20 | キヤノン株式会社 | Imaging device and method for manufacturing the same, and camera |
| US10693023B2 (en) | 2015-06-12 | 2020-06-23 | Canon Kabushiki Kaisha | Imaging apparatus, method of manufacturing the same, and camera |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07247197A (en) * | 1994-03-09 | 1995-09-26 | Fujitsu Ltd | Semiconductor device and its production |
| TW589415B (en) * | 1998-03-09 | 2004-06-01 | Shinetsu Handotai Kk | Method for producing silicon single crystal wafer and silicon single crystal wafer |
| US6077343A (en) * | 1998-06-04 | 2000-06-20 | Shin-Etsu Handotai Co., Ltd. | Silicon single crystal wafer having few defects wherein nitrogen is doped and a method for producing it |
| DE10024710A1 (en) | 2000-05-18 | 2001-12-20 | Steag Rtp Systems Gmbh | Setting defect profiles in crystals or crystal-like structures |
| DE10025871A1 (en) * | 2000-05-25 | 2001-12-06 | Wacker Siltronic Halbleitermat | Epitaxial semiconductor wafer and method for its production |
| JP5251137B2 (en) * | 2008-01-16 | 2013-07-31 | 株式会社Ｓｕｍｃｏ | Single crystal silicon wafer and manufacturing method thereof |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51134071A (en) * | 1975-05-16 | 1976-11-20 | Nippon Denshi Kinzoku Kk | Method to eliminate crystal defects of silicon |
| JPS59202640A (en) * | 1983-05-02 | 1984-11-16 | Toshiba Corp | Treatment for semiconductor wafer |
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4505759A (en) * | 1983-12-19 | 1985-03-19 | Mara William C O | Method for making a conductive silicon substrate by heat treatment of oxygenated and lightly doped silicon single crystals |
| JPS62210627A (en) * | 1986-03-11 | 1987-09-16 | Toshiba Corp | Manufacture of semiconductor wafer |
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| JP2579680B2 (en) * | 1988-12-28 | 1997-02-05 | 東芝セラミックス株式会社 | Heat treatment method for silicon wafer |
| JP2523380B2 (en) * | 1989-10-05 | 1996-08-07 | 東芝セラミックス株式会社 | Silicon wafer cleaning method |
| US5198881A (en) * | 1989-12-28 | 1993-03-30 | Massachusetts Institute Of Technology | Barrier layer device processing |
| US5159429A (en) * | 1990-01-23 | 1992-10-27 | International Business Machines Corporation | Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same |
| JPH043937A (en) * | 1990-04-20 | 1992-01-08 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1992
- 1992-03-27 JP JP4071686A patent/JP2535701B2/en not_active Expired - Lifetime
-
1993
- 1993-03-26 KR KR1019930004773A patent/KR960016219B1/en not_active IP Right Cessation
-
1994
- 1994-12-16 US US08/357,351 patent/US5574307A/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017076772A (en) * | 2015-06-12 | 2017-04-20 | キヤノン株式会社 | Imaging device and method for manufacturing the same, and camera |
| US10693023B2 (en) | 2015-06-12 | 2020-06-23 | Canon Kabushiki Kaisha | Imaging apparatus, method of manufacturing the same, and camera |
| US11355658B2 (en) | 2015-06-12 | 2022-06-07 | Canon Kabushiki Kaisha | Imaging apparatus, method of manufacturing the same, and camera |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960016219B1 (en) | 1996-12-07 |
| US5574307A (en) | 1996-11-12 |
| KR930020607A (en) | 1993-10-20 |
| JPH0636979A (en) | 1994-02-10 |
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