JP5297135B2 - Photoelectric conversion device, imaging system, and method of manufacturing photoelectric conversion device - Google Patents

Description

  The present invention relates to a photoelectric conversion device, an imaging system, and a method for manufacturing a photoelectric conversion device.

  A photoelectric conversion device used in an imaging system such as a digital camera or a video camera is required to increase the resolution and image quality of an image obtained from the output image signal and to reduce the cost in the manufacturing process. In order to satisfy the demand for higher resolution, photoelectric conversion devices are required to increase the number of pixels in the pixel array by reducing the dimensions of the pixels without increasing the chip size. In order to meet the demand for higher image quality, photoelectric conversion devices are required to improve the sensitivity of photodiodes in pixels and reduce noise in output signals. In order to satisfy the demand for cost reduction, it is required to improve the manufacturing yield of the photoelectric conversion device.

In Patent Document 1, as shown in FIG. 1 of Patent Document 1, the width of the element isolation region 401 between the photoelectric conversion elements of adjacent pixels is made narrower than the width of the element isolation region 402 between the transistor and the photoelectric conversion elements. It is described. Thus, according to Patent Document 1, it is supposed that the light receiving area of the photoelectric conversion element can be secured even if the size of the pixel is reduced.
JP 2001-189441 A

  In Patent Document 1, as shown in FIG. 2 of Patent Document 1, it is described that element isolation is performed using a thick oxide film 302 formed in each of element isolation regions 401, 402, and 403 by a selective oxidation method.

  Here, in the selective oxidation method, that is, LOCOS (LOCal Oxidation of Silicon) isolation, an oxide film is formed in the element isolation region by thermally oxidizing the semiconductor substrate. This oxide film is generally formed at a depth designed so that no parasitic MOS transistor is formed in any element isolation region.

  However, among the plurality of element isolation regions in the semiconductor substrate, not only the region where the parasitic MOS transistor is likely to be formed, but also the depth of the oxide film for element isolation that makes it difficult to form the parasitic MOS transistor. There is a region where there is no problem even if it is shallower than this. In the element isolation region where the parasitic MOS transistor is hard to be formed, the width of the oxide film for element isolation becomes wider than necessary due to the restriction of the width of the bird's beaks at both ends corresponding to the designed depth. This makes it difficult to reduce the pixel dimensions.

  An object of the present invention is to prevent a parasitic MOS transistor from operating while securing a light receiving area of a photoelectric conversion unit in a pixel even when the dimensions of the pixel are miniaturized.

The photoelectric conversion device according to the first aspect of the present invention had an imaging region in which a plurality of transistors are arranged for reading out the plurality of the photoelectric conversion portion and the plurality of accumulated in each photoelectric conversion unit signals respectively A semiconductor substrate, and in the imaging region, a photoelectric conversion unit included in the plurality of photoelectric conversion units, another photoelectric conversion unit included in the plurality of photoelectric conversion units and adjacent to the certain photoelectric conversion unit, and A first element isolation unit that electrically isolates the transistor , and a transistor included in the plurality of transistors and a second transistor that is included in the plurality of transistors and is adjacent to the transistor . The first element isolation part has a portion whose width in the plane direction is narrower and shallower than that of the second element isolation part.

  According to the present invention, even when the size of the pixel is reduced, the light receiving area of the photoelectric conversion unit can be secured in the pixel and the parasitic MOS transistor can be prevented from operating.

  A photoelectric conversion device 100 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing a circuit configuration of a photoelectric conversion apparatus 100 according to the first embodiment of the present invention.

  The photoelectric conversion device 100 includes a semiconductor substrate SB (see FIG. 3). The semiconductor substrate SB has an imaging area IA and a peripheral area PA. A pixel array 10 is arranged in the imaging area IA. A first control circuit 7 and a second control circuit 8 are arranged in the peripheral area PA.

  In the pixel array 10, a plurality of pixels 6 are arranged in the row direction and the column direction. In FIG. 1, for simplification of description, a pixel array composed of pixels of 2 rows × 2 columns is illustrated. Each pixel 6 includes a photoelectric conversion unit 1, a transfer transistor 2, a charge / voltage conversion unit 21, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. The photoelectric conversion unit 1 generates and accumulates charges corresponding to light. The photoelectric conversion unit 1 is, for example, a photodiode. The transfer transistor 2 transfers the charge generated in the photoelectric conversion unit 1 to the charge voltage conversion unit 21. The transfer transistor 2 is, for example, a transfer MOS transistor, and is generated in the photoelectric conversion unit 1 by being turned on when an active transfer control signal is supplied from the first control circuit 7 to the gate via the row control line. The charge is transferred to the charge / voltage converter 21. The charge-voltage converter 21 converts the transferred charge into a voltage. The charge voltage conversion unit 21 is, for example, a floating diffusion. The reset transistor 3 resets the charge-voltage conversion unit 21. The reset transistor 3 is, for example, a reset MOS transistor and is turned on when an active reset control signal is supplied to the gate from the first control circuit 7 via the row control line, thereby resetting the charge-voltage conversion unit 21. To do. The amplification transistor 4 outputs a signal corresponding to the voltage of the charge-voltage conversion unit 21. The amplification transistor 4 is, for example, an amplification MOS transistor, and performs a source follower operation together with a constant current source (not shown) connected to the column signal line SL, so that a signal corresponding to the voltage of the charge-voltage conversion unit 21 is obtained. Output to the column signal line SL. That is, the amplification transistor 4 outputs a reset signal corresponding to the voltage of the charge voltage conversion unit 21 to the column signal line SL in a state where the charge voltage conversion unit 21 is reset by the reset transistor 3. The amplification transistor 4 outputs an optical signal corresponding to the voltage of the charge-voltage conversion unit 21 to the column signal line SL in a state where the charge of the photoelectric conversion unit 1 is transferred to the charge-voltage conversion unit 21 by the transfer transistor 2. The selection transistor 5 brings the pixel 6 into a selected state / non-selected state. The selection transistor 5 is, for example, a selection MOS transistor, and is turned on when an active selection control signal is supplied to the gate from the first control circuit 7 via the row control line, thereby bringing the pixel 6 into a selected state. . The selection transistor 5 is, for example, a selection MOS transistor, and is turned on when a non-active selection control signal is supplied to the gate from the first control circuit 7 via the row control line, so that the pixel 6 is not selected. To.

  The first control circuit 7 selects a row in the pixel array PA, and a plurality of pixels in the pixel array PA are output so that a noise signal and an optical signal are output from each pixel in the selected row to the column signal line SL at different timings. The pixel 6 is controlled.

  The second control circuit 8 temporarily holds a noise signal and an optical signal output from each pixel in the selected row to the column signal line SL, and then outputs each held signal to an output amplifier (not shown). ).

  Next, a detailed configuration of the photoelectric conversion apparatus 100 according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing a layout configuration of the photoelectric conversion apparatus 100 according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a cross-sectional configuration of the photoelectric conversion device 100 according to the first embodiment of the present invention, and a cross section when the photoelectric conversion device 100 illustrated in FIG. 2 is cut along A-B-C-D. FIG.

  In the photoelectric conversion device 100, in the imaging area IA of the semiconductor substrate SB, as shown in FIG. 2, a plurality of pixels 6 are arranged in the row direction and the column direction. Each pixel 6 includes the photoelectric conversion unit 1 and the transistor groups (2 to 5) (see FIG. 1) as described above.

  The photoelectric conversion units 1 are arranged in the row direction and the column direction corresponding to the arrangement of the plurality of pixels 6. The transistor group (2 to 5) is arranged between the photoelectric conversion unit 1 of the pixel 6 and the photoelectric conversion unit 1 of the pixel 6 adjacent to the pixel 6 in the column direction. The plurality of photoelectric conversion units 1 are adjacent between the pixels 6 adjacent in the row direction. A plurality of transistor groups (2 to 5) are adjacent between the pixels 6 adjacent in the row direction. Between the pixels adjacent in the column direction, the photoelectric conversion unit 1 and the transistor groups (2 to 5) are adjacent to each other.

  The photoelectric conversion unit 1 includes a charge storage layer 26 and a protective layer 25. The charge storage layer 26 is disposed in the semiconductor substrate SB and stores charges generated by photoelectric conversion. The charge storage layer 26 includes a first conductivity type (for example, N-type) impurity. The protective layer 25 is disposed near the surface of the semiconductor substrate SB and protects the charge storage layer 26. The protective layer 25 includes a second conductivity type (for example, P-type) impurity.

  The transistor group (2 to 5) is a group of transistors for reading signals (charges) accumulated in the charge accumulation layer 26 of the photoelectric conversion unit 1. The transistor group (2 to 5) includes a transfer transistor 2, a reset transistor 3, an amplification transistor 4, and a selection transistor 5. A charge-voltage converter 21 is disposed between the transfer transistor 2 and the reset transistor 3. Between the reset transistor 3 and the amplification transistor 4, a semiconductor region 22 (see FIG. 1) serving as an electrode to which a power supply voltage is supplied via a wiring layer (not shown) and a contact plug (not shown) is arranged. Has been. The semiconductor region 22 includes a first conductivity type impurity. A semiconductor region 23 (see FIG. 1) is disposed between the amplification transistor 4 and the selection transistor 5. The semiconductor region 23 contains an impurity of the first conductivity type. A semiconductor region 24 serving as an electrode for outputting a signal to a column signal line SL (see FIG. 1) via a contact plug (not shown) is provided at a position adjacent to the selection transistor 5 on the opposite side to the amplification transistor 4. (See FIG. 1). The semiconductor region 24 includes a first conductivity type impurity.

  In the photoelectric conversion device 100, in the imaging region IA of the semiconductor substrate SB, as illustrated in FIGS. 2 and 3, the first element isolation unit 11, the second element isolation unit 13, and the third element isolation unit. 12 is arranged. In each of the first element isolation unit 11, the second element isolation unit 13, and the third element isolation unit 12, an insulator (for example, silicon oxide) is embedded in a trench formed in the semiconductor substrate SB. Have an STI structure.

The first element isolation unit 11 electrically isolates the plurality of photoelectric conversion units 1 between adjacent pixels. The second element isolation unit 13 electrically isolates the plurality of transistor groups (2 to 5) between adjacent pixels. The first element isolation portion 11 has a portion whose width in the plane direction is narrower and shallower than that of the second element isolation portion 13. Specifically, the width in the plane direction of the element isolation portion 11 is W11, the depth of the element isolation portion 11 from the surface SBa of the semiconductor substrate SB is D11, the width in the plane direction of the element isolation portion 13 is W13, and the semiconductor substrate SB. The depth of the element isolation part 13 from the surface SBa is D13. At this time,
W11 <W13 Formula 1
And D11 <D13 ... Equation 2
It has become.

  Here, consider a case where the power supply voltage is 5V. Considering the operation thresholds of the reset transistor 3 and the transfer transistor 2 and the operation of the amplification transistor 4 in the linear operation region, only about 3 V, for example, less than the power supply voltage is applied to the photoelectric conversion unit 1. The potential difference between both ends of the element isolation unit 11 is low, and there is no problem even if the withstand voltage due to the potential difference is low. Since the potential applied to the element isolation unit 11 is small, malfunction occurs even if the operation threshold of the parasitic MOS transistor is low. Hateful.

  Here, suppose a case where all the element isolation portions are formed with a depth designed in accordance with a region where the withstand voltage is most severe. In this case, when the aspect ratio (depth / width) of the trench is large, the insulator is not uniformly embedded in the trench, causing extra stress on the air gap and interface, and the element isolation characteristics vary from the design value. there is a possibility. Therefore, when the isolation portion is formed with an aspect ratio of the trench that provides sufficient filling characteristics, even if the breakdown voltage is low as described above, even if it is a region where there is no problem, the aspect ratio is limited. It is difficult to make it finer than the width corresponding to the depth. That is, in a region where there is no problem even if the breakdown voltage is low, the width of the element isolation portion becomes wider than necessary even though the depth of the element isolation portion is less than the designed depth.

  On the other hand, in this embodiment, even if the aspect ratio is restricted, the depth of the element isolation unit 11 is made shallower than the depth of the element isolation unit 13 as shown in Equation 2, and as shown in Equation 1, The width of the element isolation part 11 is made narrower than the width of the element isolation part 13. As a result, the width of the element isolation portion 11 is prevented from being increased more than necessary.

Further, the upper surface 11a of the first element isolation unit 11, the upper surface 13a of the second element isolation unit 13, and the upper surface 12a of the third element isolation unit 12 have the same height from the surface SBa of the semiconductor substrate SB. Specifically, the height of the upper surface 11a of the first element isolation portion 11 from the surface SBa of the semiconductor substrate SB is H11, and the height of the upper surface 13a of the second element isolation portion 13 from the surface SBa of the semiconductor substrate SB. Is H13. The height of the upper surface 12a of the third element isolation part 12 from the surface SBa of the semiconductor substrate SB is set to H12. At this time,
H11 = H12 = H13 Formula 3
It becomes. This makes it easy to form wirings and the like above each element isolation portion.

  Further, in the photoelectric conversion device 100, as shown in FIGS. 2 and 3, the first semiconductor region 131, the second semiconductor region 133, and the third semiconductor region 132 are arranged in the imaging region IA of the semiconductor substrate SB. Has been.

  The first semiconductor region 131 is disposed under the first element isolation unit 11. The first semiconductor region 131 is a region containing a second conductivity type (for example, P-type) impurity that is the opposite conductivity type to the first conductivity type (for example, N-type), and is a P-type impurity layer. In addition to 31, a P-type impurity layer 32 is included. This is because the photoelectric conversion parts are close to each other and the electrons photoelectrically converted in a deep place may cross-talk to the adjacent photoelectric conversion part by preventing the element isolation part 11 from being narrowed and shallow. It is. That is, the P-type impurity layer 31 and the P-type impurity layer 32 have a function as a potential with respect to electrons with respect to the semiconductor substrate SB. In addition, the operation threshold of the parasitic MOS transistor can be lowered by adding the P-type impurity layer 32.

  The second semiconductor region 133 is disposed under the second element isolation unit 13. The second semiconductor region 133 is a region containing a second conductivity type impurity and includes a P-type impurity layer 31.

The length of the first semiconductor region 131 in the depth direction is longer than the length of the second semiconductor region 133 in the depth direction. Specifically, when the length in the depth direction of the first semiconductor region 131 is L11 and the length L13 in the depth direction of the second semiconductor region 133 is,
L11 > L13 Formula 4
It becomes.

  On the other hand, in the photoelectric conversion device 100, the fourth element isolation portion 14 (see FIG. 12) is arranged in the peripheral area PA of the semiconductor substrate SB. The fourth element isolation portion 14 has an STI structure in which an insulator (for example, silicon oxide) is embedded in a trench formed in the semiconductor substrate SB.

The fourth element isolation unit 14 electrically isolates a plurality of elements (not shown) included in the first control circuit 7 or the second control circuit 8 (see FIG. 1). The first element isolation portion 11 has a portion whose width in the plane direction is narrower and shallower than that of the fourth element isolation portion 14. Specifically, when the width in the planar direction of the element isolation portion 14 is W14 and the depth of the element isolation portion 14 from the surface SBa of the semiconductor substrate SB is D14,
W11 <W14 ... Formula 5
And D11 <D14 Equation 6
It has become.

  As described above, the element isolation portion that electrically isolates the region between the adjacent photoelectric conversion portions in which the parasitic MOS transistor is difficult to be formed in the imaging region is narrow in the planar direction and shallow in depth. . As a result, even when the pixel size is reduced, the area of the photoelectric conversion portion can be increased, and the amount of etching of the semiconductor substrate when forming the element isolation portion around the photoelectric conversion portion is reduced. Therefore, the effect of reducing dark current can also be obtained.

  On the other hand, the element isolation portion that electrically isolates a region between a plurality of adjacent transistor groups or a region between a plurality of elements in a peripheral region where a parasitic MOS transistor may be formed in the imaging region is a planar direction. Is wide and deep. This can prevent the parasitic MOS transistor from operating.

  That is, even when the size of the pixel is reduced, in the pixel, the dark current in the photoelectric conversion unit can be reduced while securing the light receiving area of the photoelectric conversion unit, and the parasitic MOS transistor can be prevented from operating.

  Next, a method for manufacturing the photoelectric conversion device 100 according to the first embodiment of the present invention will be described with reference to FIGS. 4-12 is process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. 4 to 12, the region corresponding to the first element isolation unit 11 is X, the region corresponding to the third element isolation unit 12 is Y, and the second element isolation unit 13 is corresponding. A manufacturing process of each element isolation part is shown, where Z is an area and P is an area corresponding to the fourth element isolation part 14.

  In the step shown in FIG. 4, the surface of the semiconductor substrate SB is oxidized to form an oxide film 51, and then a silicon nitride film 52 is formed on the oxide film 51.

  In the step shown in FIG. 5, the silicon nitride film 52 at a location where an element isolation portion is to be formed later is selectively removed.

  In the step shown in FIG. 6 (second etching step), a region in which the first element isolation portion 11 that electrically isolates a plurality of photoelectric conversion portions between adjacent pixels on the surface SBa of the semiconductor substrate SB is to be formed. SBa1 is covered with a resist pattern 53. Thereafter, the semiconductor substrate SB is etched to form the second trench 54Z, the third trench 54Y, and the fourth trench 54P. That is, by selectively etching the region SBa3 where the second element isolation portion 13 that electrically isolates the plurality of transistor groups between adjacent pixels on the surface SBa of the semiconductor substrate SB is formed, the second A trench 54Z is formed. By selectively etching the region SBa2 where the third element isolation portion 12 that electrically isolates the photoelectric conversion portion and the transistor group between adjacent pixels on the surface SBa of the semiconductor substrate SB is formed, The trench 54Y is formed. By selectively etching the region SBa4 in which the fourth element isolation portion 14 for electrically isolating a plurality of elements included in the control circuit in the peripheral region of the surface SBa of the semiconductor substrate SB is formed, a fourth trench is formed. 54P is formed.

  In the step shown in FIG. 7 (first etching step), after removing the resist pattern 53, the second trench 54Z, the third trench 54Y, and the fourth trench 54P are covered with the resist pattern 55. Thereafter, the first trench 56 is formed by selectively etching the region SBa1 (see FIG. 7). In this step, the first trench 56 is formed so as to have a portion whose width in the planar direction is narrower and shallower than the second trench 54Z. In this step, the first trench 56 is formed so as to have a portion whose width in the planar direction is narrower and shallower than that of the fourth trench 54P.

  In the step shown in FIG. 8, after the resist pattern 55 is removed, the exposed portion of the semiconductor substrate SB is oxidized by heat treatment.

  In the step shown in FIG. 9, a resist pattern 57 covering the peripheral area PA is formed, and P-type impurities are implanted. As a result, the P-type impurity layer 31 as a channel stop layer is formed below the first trench 56, the second trench 54Z, and the third trench 54Y in the imaging region IA.

  In the step shown in FIG. 10, after removing the resist pattern 57, the insulator 58 is formed by HDP-CVD (High Density Plasma Chemical Vapor Deposition) method or the like. The insulator 58 is, for example, silicon oxide. As a result, the first element isolation unit 11, the second element isolation unit 13, the third element isolation unit 12, and the fourth element isolation unit 14 are formed, and the surface SBa of the semiconductor substrate SB is entirely formed. It is covered with an insulator 58.

  In the step shown in FIG. 11, the insulator 58 on the silicon nitride film 52 is removed by polishing the surface 58a of the insulator 58 by using a CMP (Chemical Mechanical Polishing) method or the like. At this time, the silicon nitride film 52 functions as a CMP stopper layer, and it is possible to perform polishing by controlling the height of the portion where the element isolation portion protrudes from the semiconductor substrate. Accordingly, the first element isolation unit 11, the second element isolation unit 13, the third element isolation unit 12, and the fourth element isolation unit 14 are separated from each other.

  In the step shown in FIG. 12, the oxide film 51 and the silicon nitride film 52 are removed.

  According to such a forming method, it is possible to form the element isolation portion in the present embodiment with the addition of the minimum necessary steps compared to the conventional STI forming method.

  Further, by sharing the polishing process for controlling the portion where the element isolation portion protrudes from the semiconductor substrate, the flatness is not deteriorated even when the STI structure having different depths is formed. That is, it is possible to improve the flatness of an insulating film or a wiring layer formed above the element isolation portion, and as a result, it is possible to improve the yield of the photoelectric conversion device itself.

  As described above, according to the present embodiment, in the photoelectric conversion device, the effect of miniaturization and dark current reduction by the narrow and shallow element isolation part, and the wider and deep element isolation part. Thus, it is possible to achieve both the effect of suppressing the operation of the parasitic MOS transistor.

  2 and 3, only the semiconductor substrate, the element isolation portion, and the gate electrode are shown for the sake of simplicity. In practice, an insulating film, a wiring layer, a contact hole, a color filter, an on-chip microlens, and the like are formed as necessary.

  Next, an example of an imaging system to which the photoelectric conversion device of the present invention is applied is shown in FIG.

  As shown in FIG. 13, the imaging system 90 mainly includes an optical system, an imaging device 86, and a signal processing unit. The optical system mainly includes a shutter 91, a lens 92, and a diaphragm 93. The imaging device 86 includes a photoelectric conversion device 100. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the lens 92 on the optical path, and controls exposure.

  The lens 92 refracts the incident light to form an image of the subject on the imaging surface of the photoelectric conversion device 100 of the imaging device 86.

  The diaphragm 93 is provided between the lens 92 and the photoelectric conversion device 100 on the optical path, and adjusts the amount of light guided to the photoelectric conversion device 100 after passing through the lens 92.

  The photoelectric conversion device 100 of the imaging device 86 converts the subject image formed on the imaging surface of the photoelectric conversion device 100 into an image signal. The imaging device 86 reads the image signal from the photoelectric conversion device 100 and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 86 and processes the image signal output from the imaging device 86.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into an image signal (digital signal).

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 86, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the photoelectric conversion device 100, a good image (image data) can be obtained.

  A photoelectric conversion device 200 according to the second embodiment of the present invention will be described with reference to FIGS. 14 and 15. FIG. 14 is a diagram showing a layout configuration of the photoelectric conversion apparatus 200 according to the second embodiment of the present invention. FIG. 15 is a diagram illustrating a cross-sectional configuration of a photoelectric conversion apparatus 200 according to the second embodiment of the present invention, and a cross section when the photoelectric conversion apparatus 200 illustrated in FIG. 14 is cut along A-B-C-D. FIG. Below, it demonstrates centering on a different part from 1st Embodiment.

Further, in the photoelectric conversion device 200, as shown in FIGS. 14 and 15, the third element isolation unit 212 is arranged in the imaging region IA of the semiconductor substrate SB. The third element isolation part 212 has a portion whose width in the plane direction is narrower and shallower than that of the second element isolation part 13. Specifically, the width of the element isolation part 212 in the planar direction is W212, and the depth of the element isolation part 212 from the surface SBa of the semiconductor substrate SB is D212. At this time,
W212 <W13 ... Formula 6
And D212 <D13 ... Formula 7
It has become.

  Here, consider a case where the power supply voltage is 5V. Considering the operation thresholds of the reset transistor 3 and the transfer transistor 2 and the operation of the amplification transistor 4 in the linear operation region, only about 3 V, for example, less than the power supply voltage is applied to the photoelectric conversion unit 1. Further, considering the operation thresholds of the amplification transistor 4 and the selection transistor 5, only about 3.5 V, for example, lower than the power supply voltage is applied to the semiconductor region 24. Therefore, the potential difference between both ends of the element isolation portions 11 and 212 is low, and it is not necessary to worry about the breakdown voltage due to the potential difference, and the element isolation portion can be narrowed. In addition, since the potential applied to the element isolation part itself is small, even if the operation threshold value of the parasitic MOS transistor is low, malfunction is unlikely to occur, so that the element isolation part can be shallowed.

  Furthermore, in the photoelectric conversion device 200, as shown in FIGS. 14 and 15, the first semiconductor region 231 and the third semiconductor region 232 are arranged in the imaging region IA of the semiconductor substrate SB.

  The first semiconductor region 231 includes a P-type impurity layer 33 instead of the P-type impurity layer 31. The P-type impurity layer 33 contains a second conductivity type impurity at a higher concentration than the P-type impurity layer 31. That is, the concentration of the second conductivity type impurity in the first semiconductor region 231 is higher than the concentration of the second conductivity type impurity in the second semiconductor region 133.

  The third semiconductor region 232 is disposed under the third element isolation unit 212. The third semiconductor region 232 is a region containing an impurity of a second conductivity type (for example, P type) which is the opposite conductivity type to the first conductivity type (for example, N type), and is a P type impurity layer. In addition to 31, a P-type impurity layer 32 is included. This is because the photoelectric conversion parts are close to each other and the electrons photoelectrically converted in a deep place may cross-talk to the adjacent photoelectric conversion part by preventing the element isolation part 11 from being narrowed and shallow. It is. Further, the operation threshold of the parasitic MOS transistor can be lowered by adding the P-type impurity layer 32 and increasing the concentration.

  The second semiconductor region 133 is disposed under the second element isolation unit 13. The second semiconductor region 133 is a region containing a second conductivity type impurity and includes a P-type impurity layer 31.

The length of the first semiconductor region 231 in the depth direction is longer than the length of the second semiconductor region 133 in the depth direction. Specifically, when the length in the depth direction of the first semiconductor region 231 is L11 and the length L13 in the depth direction of the second semiconductor region 133 is,
L11 > L13 Formula 8
It becomes.

  Thus, the P-type impurity layer 33 containing the second conductivity type impurity at a higher concentration than the lower portion of the element isolation portion 13 is formed below the element isolation portions 11 and 212. As a result, the operating threshold value of the parasitic MOS transistor is lowered than the element isolation unit 13, and the element isolation units 11 and 212 can be formed shallower than the element isolation unit 13.

  According to such a configuration, even when the pixel size is miniaturized, the area of the photoelectric conversion unit can be increased, and element isolation in the periphery of the photoelectric conversion unit is further increased than in the first embodiment. It becomes possible to reduce the etching amount of the semiconductor substrate when forming the portion. Thereby, the effect of further reducing the dark current can be obtained.

  A photoelectric conversion device 300 according to the third embodiment of the present invention will be described with reference to FIGS. 16 and 17. FIG. 16 is a diagram illustrating a layout configuration of a photoelectric conversion apparatus 300 according to the third embodiment of the present invention. FIG. 17 is a diagram illustrating a cross-sectional configuration of a photoelectric conversion device 300 according to the third embodiment of the present invention, and is a diagram illustrating a cross section when the photoelectric conversion device 300 illustrated in FIG. 17 is cut along EF. is there. Below, it demonstrates centering on a different part from 1st Embodiment.

  As shown in FIG. 17, element isolation portions 15 having an STI structure embedded with a silicon oxide film or the like formed in a semiconductor substrate SB are formed adjacent to each other with different depths.

  Here, the depth of the element isolation portion 15 is determined by whether or not a wiring made of the same material as that of the gate electrode connected to the gate electrode is disposed on the upper portion. This is because a potential is applied to the element isolation portion in the vicinity of the element isolation portion where the wiring having the same potential as the gate electrode is disposed, compared to the element isolation portion where no wiring is placed. Therefore, the parasitic MOS transistor is easy to operate, and it is necessary to increase the depth of the element isolation portion in order to prevent this.

  In a region away from the gate electrode or a region away from the wiring formed of the same material as the gate electrode, the operation of the parasitic MOS transistor is difficult, so that the element isolation portion can be made narrow and shallow.

  According to such a configuration, even when the pixel size is miniaturized, the area of the photoelectric conversion portion can be increased, and the semiconductor substrate is etched when forming the element isolation portion around the photoelectric conversion portion. Since the amount can be reduced, an effect of reducing dark current can be obtained.

  In the above embodiment, the case where each element isolation unit is the STI type is shown, but each element isolation unit may be a LOCOS type.

  Moreover, although the pixel includes the configuration including the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor each corresponding to the photoelectric conversion unit and the photoelectric conversion unit, the present invention is limited to the above-described embodiment. is not. Various modifications can be made without departing from the scope of the present invention.

  For example, the present invention can be applied to a configuration without a selection transistor, a configuration without a transfer transistor, and a configuration in which a reset transistor, an amplification transistor, and a selection transistor are shared by a plurality of pixels. That is, any pixel including a photoelectric conversion unit and at least one transistor can be applied.

  Further, in the above embodiment, the case where the conductivity type of the charge storage region of the photoelectric conversion unit is N type has been described. However, the present invention is not limited to this, and the conductivity type of the charge storage region of the photoelectric conversion unit is P type. There may be.

  In the above embodiment, the element isolation portion has only two types of depth. However, the depth is not limited to this, and an element isolation portion having three or more types of depth may be formed.

  As described above, according to the photoelectric conversion device of the present invention, it is possible to improve the image quality by reducing the dark current in addition to improving the sensitivity by increasing the light receiving area of the photoelectric conversion unit.

The figure which shows the circuit structure of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. The figure which shows the layout structure of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the photoelectric conversion apparatus 100 which concerns on 1st Embodiment of this invention. 1 is a configuration diagram of an imaging system to which a photoelectric conversion device according to a first embodiment is applied. The figure which shows the layout structure of the photoelectric conversion apparatus 200 which concerns on 2nd Embodiment of this invention. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 200 which concerns on 2nd Embodiment of this invention. The figure which shows the layout structure of the photoelectric conversion apparatus 300 which concerns on 3rd Embodiment of this invention. The figure which shows the cross-sectional structure of the photoelectric conversion apparatus 300 which concerns on 3rd Embodiment of this invention.

Explanation of symbols

90 Imaging System 100, 200, 300 Photoelectric Conversion Device

Claims (11)

Comprising a semiconductor substrate having an imaging region in which a plurality of transistors are arranged for reading out the plurality of the photoelectric conversion portion and the plurality of accumulated in each photoelectric conversion unit signals respectively,
The imaging region electrically isolates a certain photoelectric conversion unit included in the plurality of photoelectric conversion units and another photoelectric conversion unit included in the plurality of photoelectric conversion units and adjacent to the certain photoelectric conversion unit. And a second element isolation unit that electrically isolates a transistor included in the plurality of transistors and another transistor included in the plurality of transistors and adjacent to the transistor. Is arranged,
The first element isolation portion has a portion having a narrower width in the plane direction and a shallower depth than the second element isolation portion .
A photoelectric conversion device characterized by that. The imaging region electrically separates the certain photoelectric conversion unit and a transistor included in the plurality of transistors and transferring a signal of another photoelectric conversion unit adjacent to the certain photoelectric conversion unit . Is further arranged,
The third element isolation portion has a portion whose width in the plane direction is narrower and shallower than the second element isolation portion .
The photoelectric conversion device according to claim 1. The photoelectric conversion unit of the pixel includes a charge storage layer containing impurities of a first conductivity type that accumulates charges generated by photoelectric conversion,
The imaging region includes a first semiconductor region containing a second conductivity type impurity having a conductivity type opposite to the first conductivity type and disposed under the first element isolation portion, and the first A second semiconductor region including an impurity of the second conductivity type disposed under the two element isolation portions;
The length in the depth direction of the first semiconductor region is longer than the length in the depth direction of the second semiconductor region .
The photoelectric conversion device according to claim 1 or 2, wherein The photoelectric conversion unit of the pixel includes a charge storage layer including a first conductivity type impurity that stores charges generated by photoelectric conversion,
The imaging region includes a first semiconductor region containing a second conductivity type impurity having a conductivity type opposite to the first conductivity type and disposed under the first element isolation portion, and the first A second semiconductor region including an impurity of the second conductivity type disposed under the two element isolation portions;
A concentration of the second conductivity type impurity in the first semiconductor region is higher than a concentration of the second conductivity type impurity in the second semiconductor region ;
The photoelectric conversion device according to claim 1 or 2, wherein The semiconductor substrate further includes a peripheral region in which a control circuit for controlling the plurality of pixels is disposed,
The peripheral region includes a fourth element isolation unit that electrically isolates an element included in the control circuit and an element adjacent thereto ,
The first element isolation portion has a portion having a narrower width in the plane direction and a shallower depth than the fourth element isolation portion .
The photoelectric conversion device according to claim 1 or 2, wherein The upper surface of the first element isolation portion and the upper surface of the second element isolation portion have the same height from the surface of the semiconductor substrate ,
The photoelectric conversion device according to any one of claims 1 to 5, wherein The photoelectric conversion device according to any one of claims 1 to 6,
An optical system that forms an image on the imaging surface of the photoelectric conversion device;
A signal processing unit for generating image data by processing a signal output from said photoelectric conversion device, Ru provided with,
An imaging system characterized by that. A method for manufacturing a photoelectric conversion device including a semiconductor substrate having an imaging region in which a plurality of pixels each including a photoelectric conversion unit and a transistor for reading a signal accumulated by the photoelectric conversion unit are arranged,
A first trench is formed by selectively etching a region where a first element isolation portion for electrically isolating a plurality of the photoelectric conversion portions between adjacent pixels on the surface of the semiconductor substrate is formed. A first etching step to be formed;
A second trench is formed by selectively etching a region where a second element isolation portion for electrically isolating the plurality of transistors between adjacent pixels on the surface of the semiconductor substrate is to be formed. A second etching step;
Forming a first element isolation portion by embedding an insulator in the first trench, and forming the second element isolation portion by embedding an insulator in the second trench; With
In the first etching step, the first trench is formed so as to have a portion whose width in the planar direction is narrower and shallower than the second trench .
A method for manufacturing a photoelectric conversion device. Further comprising a polishing step of separating the first element isolation part and the second element isolation part from each other by polishing the embedded insulator;
The first element isolation portion has a portion having a narrower width in the plane direction and a shallower depth than the second element isolation portion .
The method for manufacturing a photoelectric conversion device according to claim 8. In the first etching step, a region where a third element isolation portion that electrically isolates the photoelectric conversion portion and the transistor between the adjacent pixels on the surface of the semiconductor substrate is selectively formed. Etching forms a third trench,
In the embedding step, the third element isolation portion is formed by embedding an insulator in the third trench,
In the polishing step, the first element isolation portion, the second element isolation portion, and the third element isolation portion are separated from each other by polishing the embedded insulator.
In the first etching step, the third trench is formed so as to have a portion whose width in the planar direction is narrower and shallower than the second trench,
The third element isolation portion has a portion whose width in the plane direction is narrower and shallower than the second element isolation portion .
The method for producing a photoelectric conversion device according to claim 9. The semiconductor substrate further includes a peripheral region in which a control circuit for controlling the plurality of pixels is disposed,
In the second etching step, a region where a fourth element isolation portion for electrically isolating a plurality of elements included in the control circuit in the peripheral region on the surface of the semiconductor substrate is selectively etched. To form a fourth trench,
In the embedding step, the fourth element isolation portion is formed by embedding an insulator in the fourth trench,
In the polishing step, the first element isolation portion, the second element isolation portion, and the fourth element isolation portion are separated from each other by polishing the embedded insulator,
In the first etching step, the first trench is formed so as to have a portion whose width in the planar direction is narrower and shallower than the fourth trench,
The first element isolation portion has a portion having a narrower width in the plane direction and a shallower depth than the fourth element isolation portion .
The method for producing a photoelectric conversion device according to claim 9 or 10, wherein:

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