JP2007201087A - Solid-state image pickup element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a solid-state image pickup element capable of manufacturing a solid-stage image pickup element having satisfactory characteristics easily. <P>SOLUTION: The solid-state image pickup element comprises a photoelectric conversion element including an n layer 2 made of an n-type impurity for accumulating charge read from a vertical CCD 5, and a p layer 3 made of a p-type impurity formed on the n layer 2. The p layer 3 is in a two-layer structure comprising a high-concentration impurity layer 3b having a relatively high impurity concentration, and a low-concentration impurity layer 3a having a relatively low impurity concentration formed between the high-concentration impurity layer 3b and the n layer 2. In the formation process of the high-concentration impurity layer 3b, ion implantation having a different amount of dose and injection energy is performed for a plurality of times to form the high-concentration impurity layer 3b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a CCD (Charge Coupled Device) type solid-state imaging device.

  In Patent Document 1, a photodiode portion that has an n-type impurity layer and generates signal charges by photoelectric conversion, a charge transfer portion that transfers signal charges, and a noise formed on the n-type impurity layer of the photodiode portion. In a CCD solid-state imaging device including a noise-reducing p-type impurity layer for reducing noise, the noise-reducing p-type impurity layer includes a high-concentration impurity layer having a relatively high impurity concentration formed on the light-receiving surface side. There is disclosed a CCD solid-state imaging device comprising a low-concentration impurity layer formed on the photodiode portion side and having a relatively low impurity concentration.

  In the CCD solid-state imaging device, when forming the p-type impurity layer for noise reduction, first, ion implantation is performed with a predetermined dose and implantation energy to form a low concentration impurity layer, and then the dose and implantation energy. The high-concentration impurity layer is formed by performing ion implantation while changing the above.

JP-A-8-97392

  If the gradient of the impurity concentration in the substrate depth direction of the high-concentration impurity layer is too gentle, the charge generated in the high-concentration impurity layer leaks to the adjacent charge transfer section, which causes smear and sensitivity reduction. . On the other hand, if the gradient is too steep, the electric field becomes strong, causing breakdown between the p-type impurity layer for noise reduction and the charge transfer portion, or white flaws. For this reason, when forming the p-type impurity layer for noise reduction, it is necessary to keep the gradient of the impurity concentration of the high-concentration impurity layer within an appropriate range that is neither too slow nor too steep. However, in the manufacturing method described in Patent Document 1, it is difficult to finely adjust the gradient, and it is difficult to manufacture a solid-state imaging device having good characteristics.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a solid-state imaging device capable of easily manufacturing a solid-state imaging device having good characteristics.

  The solid-state imaging device manufacturing method of the present invention is a CCD-type solid-state imaging device manufacturing method, wherein the solid-state imaging device includes a first conductivity type impurity that accumulates charges read to the CCD. A photoelectric conversion element including an impurity layer and a second impurity layer made of an impurity of a second conductivity type opposite to the first conductivity type formed on the first impurity layer; The second impurity layer has a two-layer structure of a low-concentration impurity layer having a relatively low impurity concentration and a high-concentration impurity layer formed on the surface portion of the low-concentration impurity layer. In the step of forming the high-concentration impurity layer, the high-concentration impurity layer is formed by performing ion implantation different in dose amount and implantation energy a plurality of times.

  In the solid-state imaging device manufacturing method according to the present invention, in the step of forming the high-concentration impurity layer, a first ion implantation having a relatively large dose and a relatively low implantation energy and an implantation having a relatively small dose. The high concentration impurity layer is formed by performing ion implantation twice with the second ion implantation having relatively high energy.

  In the method for manufacturing a solid-state imaging device of the present invention, in the step of forming the high-concentration impurity layer, the second ion implantation is performed after the first ion implantation.

  In the solid-state imaging device manufacturing method of the present invention, in the step of forming the high-concentration impurity layer, the high-concentration impurity layer is formed so as to be surrounded by the low-concentration impurity layer except for its light receiving surface.

  The method for manufacturing a solid-state imaging device according to the present invention includes: a charge reading region for the solid-state imaging device to read charges accumulated in the first impurity layer to the CCD; and the photoelectric conversion device excluding the charge reading region In the step of forming the low-concentration impurity layer, the impurity concentration of the low-concentration impurity layer is lower than the impurity concentration of the element isolation layer. Thus, the low concentration impurity layer is formed.

  In the solid-state imaging device manufacturing method of the present invention, in the step of forming the high-concentration impurity layer, the length from the end portion of the low-concentration impurity layer to the end portion of the high-concentration impurity layer is 0.1 μm or more. The high concentration impurity layer is formed.

  The solid-state imaging device of the present invention is a solid-state imaging device manufactured by the manufacturing method.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the solid-state image sensor which can manufacture the solid-state image sensor with a favorable characteristic easily can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a solid-state imaging device for explaining an embodiment of the present invention. FIG. 2 is a schematic plan view showing a state in which the member above the semiconductor substrate of the solid-state imaging device shown in FIG. 1 is removed.
The semiconductor substrate 1 includes an n-type semiconductor substrate 1a having a first conductivity type and a p-type p-well layer 1b having a second conductivity type formed on the n-type semiconductor substrate 1a. A p-type impurity layer (hereinafter abbreviated as p layer) 3 is formed on the surface portion of the p well layer 1b, and an n-type impurity layer (hereinafter abbreviated as n layer) 2 is formed under the p layer 3. Yes. Charges (electrons and holes) generated by photoelectric conversion in the n layer 2 and at the pn junction between the n layer 2 and the p well layer 1 b are accumulated in the n layer 2. Further, the charges generated in the p layer 3 are also accumulated in the n layer 2. The p layer 3, the n layer 2, and the p well layer 1b constitute a photoelectric conversion element. The p layer 3 is provided to prevent noise from being generated on the surface of the semiconductor substrate 1 from the depletion layer above the n layer 2. Details of the p layer 3 will be described later.

  A vertical CCD 5 composed of n layers is formed on the right side of the p layer 3 and the n layer 2 with a slight distance therebetween. In the p-well layer 1 b between the p-layer 3 and the n-layer 2 and the vertical CCD 5, a charge reading region 6 for reading out the charges generated in the photoelectric conversion element and accumulated in the n-layer 2 to the vertical CCD 5 is formed. The Above the vertical CCD 5, an electrode 8 made of polysilicon or the like serving as a drive electrode for driving the vertical CCD 5 and a charge readout electrode is formed via a gate insulating film 10 made of an ONO film or the like. A light shielding film 9 made of tungsten, aluminum or the like is formed on the electrode 8. An opening is formed in the light shielding film 9 above the photoelectric conversion element.

  Around the photoelectric conversion element, the charge accumulated in the photoelectric conversion element is read out in a portion excluding the charge readout region 6 formed between the photoelectric conversion element and the vertical CCD 5 from which the charge accumulated in the photoelectric conversion element is read out. An element isolation layer 7 made of a high-concentration p-type impurity is formed to separate the adjacent vertical CCD 5 (hereinafter referred to as the adjacent vertical CCD 5) and other elements such as the photoelectric conversion element adjacent to the photoelectric conversion element. Has been.

  The p-layer 3 includes a low-concentration impurity layer 3a having a relatively low impurity concentration of p-type impurities, and a high-concentration impurity layer having an impurity concentration higher than that of the low-concentration impurity layer 3a formed on the surface portion of the low-concentration impurity layer 3a. It is a two-layer structure consisting of 3b. Here, the surface portion of the low-concentration impurity layer 3a indicates the inside of the vicinity of the surface including the surface of the low-concentration impurity layer 3a. The impurity concentration of the low-concentration impurity layer 3a is lower than the impurity concentration of the element isolation layer 7 and the impurity concentration of the charge readout region 6, thereby preventing smear.

As shown in FIG. 2, the high-concentration impurity layer 3b is formed in a region inside the surface portion of the low-concentration impurity layer 3a and the region where the low-concentration impurity layer 3a is formed in plan view. Here, the region inside the region where the low concentration impurity layer 3a is formed is a region not including the peripheral portion of the region where the low concentration impurity layer 3a is formed. That is, the high-concentration impurity layer 3b is formed so that the portion other than the light receiving surface is surrounded by the low-concentration impurity layer 3a.
If the charge readout region 6 or the element isolation layer 7 and the high concentration impurity layer 3b are directly connected, a leakage current increases between the adjacent vertical CCD 5 and the high concentration impurity layer 3b, and white scratches may occur. There is. Therefore, as shown in FIGS. 1 and 2, by adopting a structure in which the low-concentration impurity layer 3a is interposed between the charge readout region 6 and the element isolation layer 7 and the high-concentration impurity layer 3b, Occurrence can be prevented. The low-concentration impurity layer 3a also functions to relieve an electric field between the high-concentration impurity layer 3b and the n layer 2 and suppress white scratches. Also, as shown in FIGS. 1 and 2, the charge accumulated in the n layer 2 can be reduced by adopting a structure in which the low concentration impurity layer 3a is interposed between the charge readout region 6 and the high concentration impurity layer 3b. It is also possible to obtain an effect that the reading voltage when reading to the vertical CCD 5 can be lowered.

  FIG. 3 shows the relationship between the length L from the end of the low concentration impurity layer 3a to the end of the high concentration impurity layer 3b shown in FIG. 2 and the leakage current between the adjacent vertical CCD 5 and the high concentration impurity layer 3b. It is a figure which shows the simulation result shown. As shown in FIG. 3, it can be seen that when the length L shown in FIG. 2 is 0.1 μm or more, the leakage current decreases rapidly. Thus, in order to suppress leakage current and effectively prevent white scratches from occurring, the length L is particularly preferably 0.1 μm or more.

  FIG. 4 shows simulation results showing the relationship between the length L from the end of the low-concentration impurity layer 3a shown in FIG. 2 to the end of the high-concentration impurity layer 3b and the read voltage applied to the charge read region 6. FIG. As can be seen from FIG. 4, the read voltage can be lowered as the length L shown in FIG. 2 increases.

  As described above, the gradient of the impurity concentration in the depth direction in the substrate of the high concentration impurity layer 3b needs to be within an appropriate range that is neither too loose nor too steep. This gradient can be adjusted by changing the ion implantation energy. However, if the gradient at a depth close to the surface of the substrate 1 is to be steeped to some extent, the gradient becomes steep even at a deep position away from the surface of the substrate 1, which is not preferable. On the other hand, if an attempt is made to prevent the gradient at a position away from the surface of the substrate 1 from becoming so steep, the gradient at a position close to the surface of the substrate 1 becomes too loose. That is, it is difficult to simultaneously optimize the impurity concentration gradient at a shallow position near the surface of the substrate 1 and the impurity concentration gradient at a deep position away from the surface of the substrate 1 only by changing the implantation energy. . Therefore, in the present embodiment, the gradient can be optimized by forming the high concentration impurity layer 3b by performing ion implantation with different dose amount and implantation energy a plurality of times.

  Hereinafter, a method for manufacturing the solid-state imaging device shown in FIG. 1 will be described. The manufacturing process until the p-layer 3 is formed is the same as the conventional process. The formation process of the p layer 3 includes a low concentration impurity layer 3a formation process for forming the low concentration impurity layer 3a and a high concentration impurity layer 3b formation process for forming the high concentration impurity layer 3b. In the low-concentration impurity layer 3a forming step and the high-concentration impurity layer 3b forming step, ion implantation using boron is performed using a predetermined mask, and then heat treatment is performed at 900 ° C. to 1000 ° C. Form. In the step of forming the p layer 3, after the low concentration impurity layer 3a is formed, ion implantation is performed on the surface portion of the low concentration impurity layer 3a and in the region inside the low concentration impurity layer 3a in plan view. Impurity layer 3b is formed.

First, in the low concentration impurity layer 3a formation step, for example, a dose is used under the condition that the impurity concentration of the low concentration impurity layer 3a is lower than the impurity concentration of the charge readout region 6 and the element isolation layer 7 using a predetermined mask. The low concentration impurity layer 3a is formed by performing ion implantation under the conditions of an amount: 3 × 10 ¹² / cm ² and an implantation energy: 20 keV. Thereafter, the process proceeds to the high concentration impurity layer 3b forming step. In the step of forming the high concentration impurity layer 3b, the first ion implantation under the condition of dose amount: 7 × 10 ¹³ / cm ² and implantation energy: 7 keV, dose amount: 3 × 10 ¹³ / cm ² , implantation energy: 10 keV The high concentration impurity layer 3b is formed by performing the second ion implantation under conditions. The conditions for the first ion implantation are such that the dose is larger than that of the second ion implantation and the implantation energy is low. The first ion implantation and the second ion implantation are performed using a mask smaller than the mask used in the low-concentration impurity layer 3a formation step, and inward of the region where the low-concentration impurity layer 3a is formed in plan view. To the region. In the high-concentration impurity layer 3b formation step, ion implantation is performed by setting a region so that the length L from the end of the low-concentration impurity layer 3a to the end of the high-concentration impurity layer 3b is 0.1 μm or more. It is preferable.

  The condition range of the ion implantation described above is that the thickness of the gate insulating film 10 is in the range of 100 nm to 150 nm, the depth of the low concentration impurity layer 3a from the surface of the semiconductor substrate 1 is 200 nm, and the high concentration impurity layer 3b. This is optimized by simulation and experiment so that the depth from the surface of the semiconductor substrate 1 becomes 20 nm.

When the high concentration impurity layer 3b is formed by performing one ion implantation under the conditions of a dose amount of 1 × 10 ¹⁴ / cm ² and an implantation energy of 7 keV, the high concentration impurity layer 3b in the depth direction in the substrate 1 is formed. It can be seen that the impurity concentration is as shown by the curve indicated by symbol a in FIG. With such a gradient, since the gradient at a shallow position (0 μm to 0.05 μm) is steep, it is possible to suppress smear, but it is difficult to suppress breakdown and white scratches. Further, the depth of the high concentration impurity layer 3b in the substrate 1 when the high concentration impurity layer 3b is formed by performing one ion implantation under the conditions of a dose amount of 1 × 10 ¹⁴ / cm ² and an implantation energy of 10 keV. It can be seen that the impurity concentration in the direction is as shown by a curve indicated by symbol b in FIG. With such a gradient, there is little concern about breakdown or white scratches, but since the gradient at a shallow position is too gentle, smear occurs.

  The curve indicated by symbol c in FIG. 5 indicates the impurity concentration in the depth direction in the substrate 1 of the high concentration impurity layer 3b when the second ion implantation is performed after the first ion implantation to form the high concentration impurity layer 3b. It is. The curve indicated by reference symbol c has a shallower slope at a shallower position than the curve a and steeper than the curve b, and the slope at a deep position is substantially the same as the curve b. In this way, by dividing the first ion implantation and the second ion implantation into two times, it is possible to make the gradient at the shallow position steep while not making the gradient at the deep position so steep. Become.

  As described above, by performing the first ion implantation and the second ion implantation to form the high-concentration impurity layer 3b, a solid-state imaging device capable of suppressing the occurrence of smear, breakdown, and white scratches. Can be manufactured.

  The first ion implantation and the second ion implantation may be performed in reverse order, but as described above, it is preferable to perform the first ion implantation first. This is because it is easier to adjust the peak position when the peak of the impurity concentration is formed at a shallow position and then the adjustment is performed by moving the peak position in the deep direction.

  In the above description, the low-concentration impurity layer 3a surrounds the high-concentration impurity layer 3b. However, as described in Patent Document 1, the low-concentration impurity layer 3a is simply formed under the high-concentration impurity layer 3b. Even with the formed two-layer structure, the above-described effects can be obtained. When the low-concentration impurity layer 3a surrounds the high-concentration impurity layer 3b, it is more difficult to adjust the impurity concentration gradient in the depth direction in the substrate 1 of the high-concentration impurity layer 3b than the configuration described in Patent Document 1. Become. For this reason, it is effective to form the high concentration impurity layer 3b by the method described above.

  In the above description, the high-concentration impurity layer 3b is formed by two ion implantations having different dose amounts and implantation energies. However, the high concentration impurity layer 3b is formed by three or more ion implantations having different dose amounts and implantation energies. The impurity layer 3b may be formed. By doing in this way, adjustment of the impurity concentration gradient of the high concentration impurity layer 3b can be performed more finely.

  In the above description, the n layer 2 corresponds to the first impurity layer in the claims, and the p layer 3 corresponds to the second impurity layer in the claims.

Schematic cross-sectional view of a solid-state imaging device for explaining an embodiment of the present invention FIG. 1 is a schematic plan view showing a state where a member above a semiconductor substrate of the solid-state imaging device shown in FIG. The figure which shows the simulation result which shows the relationship between the length L from the edge part of the low concentration impurity layer shown in FIG. 2 to the edge part of a high concentration impurity layer, and the leakage current between adjacent vertical CCD and a high concentration impurity layer The figure which shows the simulation result which shows the relationship between the length L from the edge part of the low concentration impurity layer shown in FIG. 2 to the edge part of a high concentration impurity layer, and the read-out voltage applied to a charge read-out area | region Diagram showing the relationship between ion implantation conditions and impurity concentration curve

Explanation of symbols

1 Semiconductor substrate 2 n layer 3 p layer 3a low concentration impurity layer 3b high concentration impurity layer 5 vertical CCD
6 charge readout region 7 element isolation layer 8 electrode 9 light shielding film 10 gate insulating film

Claims (7)

A manufacturing method of a CCD type solid-state imaging device,
The solid-state imaging device has a first impurity layer made of an impurity of a first conductivity type that accumulates charges read out to the CCD, and is opposite to the first conductivity type formed on the first impurity layer. And a second impurity layer made of impurities of the second conductivity type,
The second impurity layer has a two-layer structure of a low-concentration impurity layer having a relatively low impurity concentration and a high-concentration impurity layer formed on the surface portion of the low-concentration impurity layer. Yes,
In the step of forming the high concentration impurity layer, a method of manufacturing a solid-state imaging device, wherein the high concentration impurity layer is formed by performing ion implantation with different dose amount and implantation energy a plurality of times. It is a manufacturing method of the solid-state image sensing device according to claim 1,
In the step of forming the high-concentration impurity layer, a first ion implantation having a relatively large dose and a relatively low implantation energy and a second ion implantation having a relatively small dose and a relatively high implantation energy. The solid-state imaging device manufacturing method of forming the high-concentration impurity layer by performing ion implantation twice. A method for producing a solid-state imaging device according to claim 2,
In the step of forming the high-concentration impurity layer, a method of manufacturing a solid-state imaging device in which the second ion implantation is performed after the first ion implantation is performed. It is a manufacturing method of the solid-state image sensing device according to any one of claims 1 to 3,
In the high concentration impurity layer forming step, the high concentration impurity layer is formed such that the portion other than the light receiving surface is surrounded by the low concentration impurity layer. It is a manufacturing method of the solid-state image sensing device according to claim 4,
The solid-state imaging device has a charge readout region for reading out the charges accumulated in the first impurity layer to the CCD, and the second conductive formed around the photoelectric conversion element excluding the charge readout region. An element isolation layer made of a mold,
A method of manufacturing a solid-state imaging device, wherein the low concentration impurity layer is formed in the low concentration impurity layer forming step so that an impurity concentration of the low concentration impurity layer is lower than an impurity concentration of the element isolation layer. It is a manufacturing method of the solid-state image sensing device according to claim 4 or 5,
In the step of forming the high-concentration impurity layer, the solid-state imaging in which the high-concentration impurity layer is formed so that the length from the end portion of the low-concentration impurity layer to the end portion of the high-concentration impurity layer is 0.1 μm or more. Device manufacturing method.   A solid-state imaging device manufactured by the manufacturing method according to claim 1.

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