JP2004172229A - Solid-state imaging device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower the voltage VT for reading electric charges without further developing white blemish and degrading such characteristics as a blooming margin. <P>SOLUTION: Prior to implantation of n-type impurity ions for forming an electric charge accumulation region of a photo diode (photoelectric conversion section), a gate insulation film is made thin and is formed with steps along both sides of a photo detection region of the photo diode. On both sides of the photo detection region, thick film portions are formed which are formed thicker than the other parts to attenuate ion implantation energy. By implanting n-type impurity ions under this condition, both side portions of an N layer which will become the electric charge accumulation region can be formed at a shallow position of a semiconductor substrate than the other portions due to the existence of the thick film portions of the gate insulation film. Consequently, the doping concentration of a P layer in the front surface of the substrate can be lowered near an electric charge reading section without damaging the whole structure, resulting in facilitating the read-out of electric charges. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to various solid-state imaging devices such as a CCD image sensor and a CMOS image sensor and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, as this type of solid-state imaging device, for example, one having a structure as shown in FIG. 12 is known.
This solid-state imaging device is an example of a CCD type image sensor. A photodiode (photoelectric conversion unit) 20, a charge readout unit 30, a vertical charge transfer unit 40, and a channel stop unit 50 are provided in an upper layer region of a semiconductor substrate 10. ing.
A vertical transfer electrode 70 is provided on the upper surface of the semiconductor substrate 10 with a gate insulating film 60 interposed therebetween, and a light-shielding film 90 is provided thereon with an interlayer insulating film 80 interposed therebetween.
[0003]
The photodiode (photoelectric conversion unit) 20 includes an upper hole accumulation region (P + layer) 22 and a lower charge accumulation region (N layer) 24, and the hole accumulation region (P + layer) 22 is incident. It has a function of absorbing holes separated from electrons by light on the surface side of the semiconductor substrate 10, and the charge storage region (N layer) 24 has a function of storing electrons in a lower depletion layer.
The hole accumulation region (P + layer) 22 and the charge accumulation region (N layer) 24 are formed by adding P-type impurity ions or N-type impurity ions by ion implantation from above the substrate, respectively.
[0004]
The charge readout section (P layer) 30 reads out the signal charges stored in the charge storage region 24 of the photodiode 20 via the P− layer 32. Note that the P − layer 32 is formed by the N-type impurity of the charge storage region 24 being diffused in the P layer of the charge readout unit 30 in the lateral direction by the activation annealing process after the ion implantation.
The vertical charge transfer section 40 includes an upper N layer 42 and a lower P layer 44, and transfers the signal charges read by the charge read section (P layer) 30 in the vertical direction (the direction of the paper surface of FIG. 12). .
The channel stop section (P layer) 50 separates the photodiode 20 from the vertical charge transfer section 40 of an adjacent pixel.
[0005]
The gate insulating film 60 has, for example, a MONOS structure in which a silicon nitride film is sandwiched between upper and lower silicon oxide films, and a portion corresponding to a light receiving region of the photodiode 20 is thinned, leaving only a lower silicon oxide film. It has become.
The vertical transfer electrode 70 is made of a polycrystalline silicon film, and drives the vertical charge transfer unit 40 via the gate insulating film 60.
The interlayer insulating film 80 is a silicon oxide film or the like, and is disposed in the entire region from the vertical transfer electrode 70 to the light receiving region of the photodiode 20.
Further, the light-shielding film 90 is a film made of aluminum or the like, and is disposed along the upper surface of the interlayer insulating film 80. The light-shielding film 90 has an opening 90A corresponding to the light receiving region of the photodiode 20. Light is incident on the light receiving region of the diode 20 and blocks incident light on the vertical charge transfer unit 40.
[0006]
[Problems to be solved by the invention]
By the way, in the solid-state imaging device having the above-described structure, the voltage (hereinafter abbreviated as VT) required to read out the electrons stored in the charge storage region 24 of the photodiode 20 is reduced in power consumption and manufacturing. The lower the better, from the viewpoint of improving the yield.
Therefore, in order to lower the VT, the impurity concentration of the P layer of the charge reading unit 30 may be reduced, and the potential barrier of the charge reading unit 30 may be reduced.
However, if the impurity concentration of the P layer is uniformly reduced, there is a disadvantage that the blooming margin (hereinafter, abbreviated as VAB) also decreases.
[0007]
Here, it is considered that the path of the charge when reading from the photodiode 20 to the vertical charge transfer unit 40 is on the surface side of the semiconductor substrate 10 as compared with the path of the charge when blooming occurs.
Therefore, in order to facilitate reading without causing blooming, the concentration of boron (B) near the substrate surface of the charge reading unit 30 may be reduced.
For example, if the implantation energy of the ion implantation for forming the charge storage region (n layer) 24 of the photodiode 20 is reduced, the N-type impurity diffuses laterally through a subsequent heat treatment step, and the vicinity of the surface of the substrate 10 is reduced. The impurity concentration of the P layer of the charge reading section 30 can be reduced.
However, in this method, the distance between the hole accumulation region (P + layer) 22 of the photodiode 20 is reduced, and the electric field between the P + layer 22 and the N layer 24 of the photodiode 20 is increased. There is a disadvantage that defects increase.
[0008]
Accordingly, an object of the present invention is to provide a solid-state imaging device capable of lowering the voltage VT for charge reading without deteriorating characteristics such as white flaws and blooming margin, and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention forms, on a semiconductor substrate, a photoelectric conversion unit that generates a signal charge according to an amount of received light, and a reading unit that reads out the signal charge generated by the photoelectric conversion unit. A method for manufacturing a solid-state imaging device, wherein an upper layer film including a gate insulating film is formed on the semiconductor substrate, wherein a thin film portion corresponding to a light receiving region of the photoelectric conversion unit is formed on the gate insulating film formed on the semiconductor substrate. Forming a first conductivity type impurity region of the photoelectric conversion portion by performing ion implantation into a semiconductor substrate through a thin film portion of the gate insulating film; Ion implantation into the semiconductor substrate through the thin film portion of the insulating film to form a second conductivity type impurity region of the photoelectric conversion unit in an upper layer portion of the first conductivity type impurity region; An impurity region forming step, wherein when the thin film portion is formed in the gate insulating film by the thin film portion forming step, at least a region of the gate insulating film on the light receiving region of the photoelectric conversion portion which is close to the charge readout portion The thickness of the gate insulating film is formed to be larger than the thickness of the gate insulating film in the other region of the light receiving region.
[0010]
In addition, the present invention includes a photoelectric conversion unit that generates a signal charge according to an amount of received light on a semiconductor substrate, and a reading unit that reads out the signal charge generated by the photoelectric conversion unit, and the photoelectric conversion unit is formed on the semiconductor substrate. A first conductivity type impurity region, and a second conductivity type impurity region formed above the first conductivity type impurity region, wherein the first conductivity type impurity region is a light receiving region of the photoelectric conversion unit. Wherein the impurity distribution in at least the region near the charge readout portion is formed at a position shallower in the semiconductor substrate than the impurity distribution in other regions of the light receiving region.
[0011]
In the method for manufacturing a solid-state imaging device according to the present invention, in the gate insulating film on the light receiving region of the photoelectric conversion unit, at least the thickness of the gate insulating film in the region close to the charge readout unit is changed to the gate of the other region of the light receiving region. By forming the first conductive type impurity region to a thickness larger than the thickness of the insulating film, in the subsequent first conductive type impurity region forming step, the first conductive type impurity region is formed near the substrate surface near the charge readout portion. Become. Therefore, the first conductivity type impurity diffuses in the lateral direction during the activation annealing, and the concentration of the second conductivity type impurity in the charge readout portion on the substrate surface side is lower than in the conventional structure, so that the charge readout becomes easy.
On the other hand, since the first conductivity type impurity region is formed at a deep position at the center of the photoelectric conversion unit, the distance between the first conductivity type impurity region and the second conductivity type impurity region on the surface of the photoelectric conversion unit is increased. The electric field between the junctions of the conductivity type is weakened, and white scratches are less likely to occur.
As a result, the charge reading voltage VT can be reduced without deteriorating characteristics such as white scratches and blooming margin.
[0012]
In the solid-state imaging device according to the present invention, the first conductivity type impurity region of the photoelectric conversion unit is formed near the substrate surface in a region close to the charge readout unit. Therefore, the first conductivity type impurity diffuses in the lateral direction during the activation annealing, and the concentration of the second conductivity type impurity in the charge readout portion on the substrate surface side is lower than in the conventional structure, so that the charge readout becomes easy.
On the other hand, since the first conductivity type impurity region is formed at a deep position at the center of the photoelectric conversion unit, the distance between the first conductivity type impurity region and the second conductivity type impurity region on the surface of the photoelectric conversion unit is increased. The electric field between the junctions of the conductivity type is weakened, and white scratches are less likely to occur.
As a result, the charge reading voltage VT can be reduced without deteriorating characteristics such as white scratches and blooming margin.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a solid-state imaging device and a method for manufacturing the same according to the present invention will be described in detail.
1 to 11 are a cross-sectional view and a plan view illustrating a stacked state of a solid-state imaging device in each step using a method for manufacturing a solid-state imaging device according to an embodiment of the present invention. In this embodiment, the N-type corresponds to the first conductivity type, and the P-type corresponds to the second conductivity type.
In the manufacturing method according to the present embodiment, prior to the operation of implanting N-type impurity ions for forming the charge accumulation region of the photodiode (photoelectric conversion unit), the operation of thinning the gate insulating film is performed. A step is formed in the film along both sides of the light receiving region of the photodiode, and formed on both sides of the light receiving region (that is, a region near the charge readout portion and the channel stop portion) to be thicker than other portions. A thick film portion for attenuating ion implantation energy is provided.
In this state, by implanting N-type impurity ions, both sides of the N layer serving as a charge storage region due to the thick film portion of the gate insulating film are located at a shallower position of the semiconductor substrate than other portions. Form.
[0014]
By using such a method, the N layer is formed closer to the substrate surface because the gate insulating film is thicker near the charge readout portion. Therefore, at the time of activation annealing, the N-type impurity diffuses in the horizontal direction, and the P layer concentration in the reading portion on the substrate surface side is reduced as compared with the conventional structure, so that the charge can be easily read.
On the other hand, in a region where the gate insulating film at the center of the photodiode is thin, the N layer is formed at a deep position, so that the distance from the P + layer on the photodiode surface is increased, and the electric field between the PN junctions is weakened. White scratches are less likely to occur.
Further, by increasing the thickness of the gate insulating film on the channel stop portion side, it is possible to reduce a component (smear) in which electrons photoelectrically converted into the charge transfer portion near the surface of the substrate.
[0015]
Specifically, a step formed on the gate insulating film between both sides of the light receiving region and the other portion is set to about 20 nm to 100 nm, and N-type impurity ions are implanted at an energy of 0.4 to 1.5 MeV and 1 e. By performing ion implantation at a concentration of ¹² cm ⁻² to 5e ¹² cm ⁻² , the charge reading voltage VT can be effectively reduced without deteriorating characteristics such as white flaws and blooming margin.
[0016]
Hereinafter, the manufacturing method of this example will be specifically described with reference to FIGS.
First, FIG. 1 shows a step of forming a gate insulating film on an upper surface of a semiconductor substrate. At this point, the semiconductor substrate (silicon substrate) 110 is already provided with the charge readout unit (P layer) 130, the vertical charge transfer unit (N layer 142 and P layer 144) 140, and the channel stop unit (P layer) 150. It is assumed that Then, a gate insulating film 160 is formed on the semiconductor substrate 110.
The gate insulating film 160 of this example has a MONOS structure in which a silicon nitride film is sandwiched between upper and lower silicon oxide films, similarly to the conventional example shown in FIG. Note that the gate insulating film 160 is formed by first forming a lower silicon oxide film on the semiconductor substrate 110 by thermal oxidation or low-pressure CVD, and then forming a silicon nitride film thereon by low-pressure CVD or the like. Further, a lower silicon oxide film is formed thereon by thermal oxidation or low-pressure CVD.
Then, the upper silicon oxide film and the middle silicon nitride film are sequentially removed by etching to form a step between the both sides and the other part (thick film part on both sides), and The thick film portion left in the portion is removed.
[0017]
Next, FIG. 2 shows a step of patterning a photoresist film 170 for an etching mask for forming a step in the gate insulating film 160 and removing the silicon oxide film on the gate insulating film 160 by etching. .
The photoresist film 170 is formed in such a manner that only the central portion of the light receiving region (shown in FIG. 6 and thereafter) of the photodiode is opened, and both sides of the light receiving region are masked. Then, wet etching or dry etching is performed using the photoresist film 170 as a mask, whereby the silicon oxide film on the gate insulating film 160 is removed.
[0018]
Next, in FIG. 3, wet etching or dry etching is performed using the photoresist film 170 formed in FIG. 2 as a mask to remove the middle silicon nitride film of the gate insulating film 160.
By such etching, the central portion (the portion excluding both side portions) of the light receiving region in the gate insulating film 160 is thinned.
As a result, a thick film portion 162 is left only on both sides of the light receiving region, and a thin film portion 164 made of a lower silicon oxide film is formed in other portions.
[0019]
FIG. 4 is an explanatory diagram showing the pattern of the gate insulating film 160 after the etching performed in FIG. 3 together with the pattern of the light receiving region and the transfer electrode. FIG. 3 corresponds to a cross section taken along line AA ′ of FIG.
In the drawing, a region 180A indicated by a thin oblique line indicates a pattern of a transfer electrode arranged in a lower layer, and a region 180B indicated by a thick frame indicates a pattern of a transfer electrode in an upper layer.
The gap portion 200A between these transfer electrodes is a portion to be a light receiving region of the photodiode. Thick film portions 162 are formed in stripes on both sides of the central thin film portion 164.
[0020]
Next, in FIG. 5, after the photoresist film 170 shown in FIG. 4 is removed, a vertical transfer electrode 180 is formed on the gate insulating film 160. In this method, a desired pattern is formed by, for example, forming a film of an electrode material by a CVD (chemical vapor deposition) method or the like and then opening a window by a photoresist method. Then, a photoresist film 190 is formed on the vertical transfer electrode 180.
Next, in FIG. 6, N-type impurities are ion-implanted to form a charge storage region (N-layer) 204 of the photodiode 200.
At this time, due to the difference in film thickness between the thick film portion 162 and the thin film portion 164 of the gate insulating film 160, the ion implantation energy is attenuated more in the region where the thick film portion 162 is provided, and the charge storage region (N layer The N-type impurity region 204B on both sides is formed at a shallower position in the semiconductor substrate 110 than the N-type impurity region 204A at the center of the semiconductor substrate 110.
[0021]
Next, in FIG. 7, the thick film portion 162 of the gate insulating film 160 is removed by etching, and the thickness of the thin film portion 164 is made uniform. Thereafter, in FIG. 8, ion implantation of a P-type impurity is performed to form a hole accumulation region (P + layer) 202 of the photodiode 200.
Therefore, the hole accumulation region (P + layer) 202 is formed at a uniform depth. As a result, the upper region of the N-type impurity region 204B of the charge storage region (N layer) 204 formed at the shallow position of the semiconductor substrate 110 and the lower region on both sides of the hole storage region (P + layer) 202 overlap. Means that a low concentration N- region 206 is formed.
Next, in FIG. 9, an interlayer insulating film 210 is formed on the entire surface, and in FIG. 10, an activation annealing process is performed. The N-type impurity in the charge storage region 204 diffuses in the P layer of the charge readout unit 130 in the lateral direction by the activation annealing process, so that the P − layer 132 is formed.
In FIG. 11, a light-shielding film 220 is formed, and thereafter, although not shown, various insulating films and wiring layers are formed on the light-shielding film 220, and further flattening is provided on the upper layer to form an on-chip The color filter and on-chip lens are arranged to complete the image sensor.
[0022]
According to the above-described method, the charge accumulation region (N layer) 204 of the photodiode 200 is formed near the surface of the substrate near the charge readout unit 130. In the central portion of the photodiode 200, the charge accumulation region (N layer) 204 is provided in the central portion of the photodiode 200. Is formed at a deep position, so that the distance from the hole accumulation region (P + layer) 202 is increased, the electric field between the PN junctions is weakened, and white defects are less likely to occur.
In addition, by making the channel stop portion 150 thick, it is possible to reduce a component (smear) in which electrons photoelectrically converted near the surface of the substrate enter the vertical charge transfer portion 140.
[0023]
In the above, an example in which the present invention is applied to a CCD image sensor has been described. However, as a solid-state imaging device to which the present invention is applied, if a semiconductor substrate is provided with a photoelectric conversion unit and a charge readout unit, a CCD image sensor is used. It is also possible to apply to a solid-state imaging device other than the sensor.
Further, the specific configuration such as the type of the gate insulating film and the ion implantation conditions is not limited to the above example, but can be appropriately modified.
[0024]
【The invention's effect】
As described above, in the method for manufacturing a solid-state imaging device of the present invention, in the gate insulating film on the light receiving region of the photoelectric conversion unit, at least the film thickness of the gate insulating film in the region close to the charge readout unit is reduced. By forming the gate insulating film to a thickness larger than the thickness of the gate insulating film in the other region, in the subsequent first conductive type impurity region forming step, the first conductive type impurity region is located near the substrate surface near the charge readout portion. Will be formed.
Therefore, at the time of activation annealing, the first conductivity type impurity diffuses in the horizontal direction, and the second conductivity type impurity concentration in the charge readout portion on the substrate surface side is reduced as compared with the conventional structure. Since the first conductivity type impurity region is formed at a deep position in the center of the photoelectric conversion unit, the distance between the first conductivity type impurity region and the second conductivity type impurity region on the surface of the photoelectric conversion unit is increased. The electric field between the junctions is weakened, and white scratches hardly occur.
As a result, the charge reading voltage VT can be reduced without deteriorating characteristics such as white scratches and blooming margin.
[0025]
In the solid-state imaging device according to the present invention, the first conductivity type impurity region of the photoelectric conversion unit is formed near the substrate surface in a region close to the charge readout unit.
Therefore, at the time of activation annealing, the first conductivity type impurity diffuses in the horizontal direction, and the second conductivity type impurity concentration in the charge readout portion on the substrate surface side is reduced as compared with the conventional structure. Since the first conductivity type impurity region is formed at a deep position in the center of the photoelectric conversion unit, the distance between the first conductivity type impurity region and the second conductivity type impurity region on the surface of the photoelectric conversion unit is increased. The electric field between the junctions is weakened, and white scratches hardly occur.
As a result, the charge reading voltage VT can be reduced without deteriorating characteristics such as white scratches and blooming margin.
[Brief description of the drawings]
FIG. 1 is a sectional view illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a solid-state imaging device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 4 is a plan view illustrating the method for manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 6 is a sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 7 is a sectional view showing the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 8 is a cross-sectional view illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 9 is a sectional view illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 10 is a sectional view illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 11 is a sectional view illustrating the method of manufacturing the solid-state imaging device according to the embodiment of the present invention.
FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional solid-state imaging device.
[Explanation of symbols]
110 semiconductor substrate, 130 charge readout unit, 140 vertical charge transfer unit, 143 N layer, 144 P layer, 150 channel stop unit, 160 gate insulating film, 162 Thick film portion, 164 thin film portion, 170, 190 photoresist film, 180 vertical transfer electrode, 200 photodiode, 202, hole accumulation region (P + layer), 204 charge accumulation region (N layer), 206... N-region, 210... Interlayer insulating film, 220.

Claims (8)

Forming a photoelectric conversion unit that generates signal charges according to the amount of received light on a semiconductor substrate, and a reading unit that reads out signal charges generated by the photoelectric conversion unit, and forming an upper layer film including a gate insulating film on the semiconductor substrate A method for manufacturing a solid-state imaging device,
For a gate insulating film formed on the semiconductor substrate, a thin film portion forming step of forming a thin film portion corresponding to a light receiving region of the photoelectric conversion portion,
A first conductivity type impurity region forming step of forming a first conductivity type impurity region of the photoelectric conversion portion by performing ion implantation into the semiconductor substrate through the thin film portion of the gate insulating film;
A second conductivity type impurity region forming a second conductivity type impurity region of the photoelectric conversion unit in an upper layer portion of the first conductivity type impurity region by performing ion implantation into a semiconductor substrate through a thin film portion of the gate insulating film; And a forming step,
When forming a thin film portion in the gate insulating film by the thin film portion forming step, of the gate insulating film on the light receiving region of the photoelectric conversion unit, at least the thickness of the gate insulating film in the region close to the charge readout unit, Forming a film thickness larger than the film thickness of the gate insulating film in the other region of the light receiving region;
A method for manufacturing a solid-state imaging device, comprising: In the thin film portion forming step, a portion of the gate insulating film formed on the light receiving region of the photoelectric conversion portion having a large thickness is removed after ion implantation of the first conductivity type impurity region. 2. The method for manufacturing a solid-state imaging device according to claim 1, further comprising a step of adjusting the thickness of the film. 3. The method according to claim 2, wherein the ion implantation in the second conductivity type impurity region forming step is performed after the thickness of the gate insulating film is uniformed in the entire light receiving region. When forming the thin film portion on the gate insulating film by the thin film portion forming step, the thickness of the gate insulating film in the region near the charge readout portion and the channel stop of the gate insulating film on the light receiving region of the photoelectric conversion portion 2. The solid-state imaging device according to claim 1, wherein the thickness of the gate insulating film in a region close to the portion is formed to be larger than the thickness of the gate insulating film in another region of the light receiving region. Production method. The gate insulating film has a stacked structure of a plurality of films of different film types, and the thin film portion is formed by removing an upper layer film of the plurality of films by etching. 2. A method for manufacturing the solid-state imaging device according to 1. 6. The method according to claim 5, wherein the gate insulating film has a structure in which a silicon nitride film is sandwiched between upper and lower silicon oxide films. A photoelectric conversion unit that generates a signal charge according to the amount of light received on the semiconductor substrate; and a read unit that reads out the signal charge generated by the photoelectric conversion unit. A first conductivity type impurity region, and a second conductivity type impurity region formed above the first conductivity type impurity region,
In the first conductivity type impurity region, an impurity distribution of at least a region of the light receiving region of the photoelectric conversion unit close to the charge readout unit is formed at a shallower position of the semiconductor substrate than an impurity distribution of another region of the light receiving region. Yes,
A solid-state imaging device characterized by the above-mentioned. In the first conductivity type impurity region, an impurity distribution of a region of the light receiving region of the photoelectric conversion unit near the charge readout unit and an impurity distribution of a region of the light receiving region of the photoelectric conversion unit near the channel stop unit are different from those of the light receiving region. 8. The solid-state imaging device according to claim 7, wherein the solid-state imaging device is formed at a position shallower in the semiconductor substrate than the impurity distribution in the portion.

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