KR100450363B1 - Solid state image sensor and manufacturing method thereof - Google Patents

Abstract

Due to the low power supply voltage, the potential barrier is further increased, resulting in further increase in afterimages and noise. As described above, in the conventional solid-state imaging device, the device solves the problems of the pseudo signal and the potential barrier caused by the demand for miniaturization and low power supply voltage, thereby improving the device performance.

A read gate electrode 13a is selectively formed on the silicon substrate, and an N-type drain region 14a is formed at one end of the read gate electrode 13a. In addition, an N-type signal accumulation region 15 is formed at the other end of the read gate electrode 13a. On the signal accumulation region 15, a P ⁺ type surface shield region 21a is formed by selective epitaxial growth. On this surface shield region 21a, a silicon oxide film and a silicon nitride film are formed, and the signal accumulation region 15 is formed. A silicide block layer 19 is formed that covers at least a portion of the. Ti silicide film 33a is formed on the drain region 14a.

Description

Solid-state imaging device and its manufacturing method {SOLID STATE IMAGE SENSOR AND MANUFACTURING METHOD THEREOF}

The present invention relates to a solid-state imaging device having a photodiode and a MOS field effect transistor, and a manufacturing method thereof.

In recent years, the rapid spread of personal computers and portable information device terminals has increased the opportunity for individuals to easily acquire, process, and edit images. For this reason, the necessity of downsizing, low power consumption, and low cost is increasing also about the solid-state imaging device which was centered on CCD. To satisfy these needs, MOS-type solid-state imaging devices (commonly known as CMOS image sensors) based on general-purpose CM0S semiconductor technology have emerged and are being spread. Currently, products of CM0S image sensors are made using CMOS technology of 0.35 탆 or more. However, in the future, the necessity of downsizing and low power consumption of the solid-state imaging device is high, and further miniaturization is expected to proceed.

29 shows a cross-sectional view of a conventional MOS type solid-state imaging device as disclosed in, for example, Japanese Patent Laid-Open No. 10-150182. In FIG. 29, region A shows a pixel region, and region B shows a peripheral circuit region.

As shown in FIG. 29, gate electrodes 13a, 13b, and 13c made of polysilicon are selectively formed on the P-type silicon substrate 11 through the gate insulating film (silicon oxide film) 12. As shown in FIG. . Here, in area A, reference numeral 13a denotes a read gate electrode, and 13b denotes a reset or address gate electrode. In addition, since the LOCOS structure is common in the non-fine pattern of 0.35 탆 technology or more, an element isolation region (hereinafter referred to as LOCOS) of the LOCOS structure is selectively formed in the silicon substrate 11.

In the region A, an N-type drain region 14a and an N-type signal accumulation region 15 of the photodiode are formed in a predetermined region of the surface of the silicon substrate 11, and the N-type signal accumulation region 15 On the surface, a P ⁺ type surface shield region 21 is formed. As a result, buried photodiodes 34a and 34b of the P ⁺ NP type which accumulate signal charges corresponding to the incident light amount are formed. In the region B, Nwell and Pwell are formed in the silicon substrate 11, and the N-type LDD (Light1y Doped Drain) region 14b and the P-type LDD region 14c are formed in the Nwell and Pwell, respectively.

A first interlayer insulating film 25 is formed on the entire surface, and a second interlayer insulating film 27 is formed on the first interlayer insulating film 25, and the Al light shielding film 28 is formed on the second interlayer insulating film 27. ) Is formed. The Al light shielding film 28 is provided with an opening 30 for injecting light into the photodiodes 34a and 34b. Further, on the first interlayer insulating film 25 in the second interlayer insulating film 27, an Al wiring 26 serving as a signal line or a connection wiring in a unit pixel is selectively formed. Moreover, the surface protection film 29, such as a silicon nitride film, which covers the whole surface is formed in the uppermost surface. In addition, intermediate refractive index films such as Ti and TiN films may be provided on the upper and lower surfaces of the Al wiring 26 and the Al light shielding film 28 (Japanese Patent Laid-Open No. 11-45989).

In such a M0S type solid-state imaging device, the signal charge accumulated in the signal accumulation region 15 of the photodiode is read into the N-type drain region 14a by applying a positive voltage to the read gate electrode 13a. As a result, the potential of the drain region 14a is modulated. The drain region 14a is electrically connected to the gate electrode 13b of the amplifying transistor, and the amplified electric signal is output to the signal line. Here, a reset transistor and reset gate line 13b for electrically resetting the drain region 14a, an address transistor and an address gate line 13b for addressing the amplifying transistor and the amplifying transistor are used.

However, in the above-mentioned conventional solid-state imaging device, one of the problems that occur when the pixels are miniaturized is that the effect of stray light is more intense.

The stray light is, for example, the surface of the Al wiring 26, the drain region 14a, and the gate electrode 13b after a part of the light incident on the photodiodes 34a and 34b is reflected from the surface of the silicon substrate 11. It refers to the phenomenon of multi-reflection from and reaching far. In the solid-state imaging device shown in Fig. 29, the surface of the gate electrodes 13a, 13b, 13c and the surfaces of the source / drain regions 14a, 14b, 14c have a light reflectance such that the light reflectance is 40% or more in the visible light region. It is a high silicon material. For this reason, stray light reflected from the surface of the photodiode 34a reaches the adjacent photodiode 34b without sufficiently attenuating, and as a result, a similar signal such as smear or blooming occurs.

As the pixel becomes smaller, when the interval between the photodiodes 34a and 34b is shortened, stronger stray light enters the neighboring photodiode. As a result, similar signals such as smear and blooming are likely to occur. In addition, since the stray light does not sufficiently attenuate, the stray light reaches the source / drain regions 14b and 14c and the gate electrode 13c in the B region (peripheral circuit region), resulting in malfunction of the transistor. Therefore, of course, as the pixels become finer in the future, the adverse effects of stray light become more intense.

By the way, a power supply voltage of 3.3 V or more is used in the CM0S image sensor. In order to meet the necessity of further miniaturization and low power consumption of the solid-state imaging device, development of low power supply voltage of 3.3 V or less is expected to proceed simultaneously with the miniaturization of 0.35 μm or less described above.

However, when the buried photodiode structure in which other conductive type surface shield regions are formed on the photodiode surface is used as the signal accumulation region, the problem due to the low power supply voltage, that is, the low power supply of the read gate becomes large.

FIG. 30A shows a cross-sectional view of a buried photodiode which is a part of region A of FIG. 29. 30 (b) and 30 (c) show potential cross-sectional views at the time of low voltage reading (when the read gate electrode is ON), and FIG. 30 (c) reads at a lower voltage than FIG. 30 (b). The case is showing.

As shown in FIGS. 30A and 30B, a device isolation region having a LOCOS structure is formed in the P-type silicon substrate 11, and a gate insulating film 12 such as a silicon oxide film is formed on the silicon substrate 11. ), The read gate electrode 13a is formed. On the surface of the silicon substrate 11, an N-type drain region 14a, an N-type signal accumulation region 15, and a P ⁺ type surface shield region 21 are formed by ion implantation. In addition, the silicon substrate 11 and the surface shield region 21 are provided at a reference potential.

In such a solid-state imaging device, when light is incident on the photodiode 34a, the incident light is photoelectrically converted, and signal electrons are accumulated in the signal accumulation region 15. Here, the surface shield region 21 serves to reduce the junction leakage current by blocking the depletion layer at the interface of the gate insulating film 12 made of Si / SiO ₂ and the signal embedded in the surface shield region 21 and the silicon substrate 11. The potential 42 of the accumulation region 15 is set to be lower than the channel potential 43 under the read gate electrode 13a which is modulated by turning on the read gate electrode 13a. Therefore, the signal electrons accumulated in the signal accumulation region 15 can be completely transferred to the drain region 14a in principle.

However, in the conventional solid-state imaging device as shown in FIG. 30A, the entire area of the surface shield region 21 is embedded in the silicon substrate 11. For this reason, the upper surface of the surface shield region 21 is located below the lower surface of the read gate electrode 13a. Therefore, in the potential barrier generating portion 40 at the end of the surface shield region 21, a potential barrier 41 as shown in Fig. 30B is generated. As a result, the residual charge 44 remains in the signal accumulation region 15 without being completely transferred, which causes a large amount of afterimage and noise.

In addition, in response to the demand for low power supply voltage reduction, when the power supply voltage decreases, that is, when the voltage (read voltage) when the read gate electrode 13a is turned on (for example, the read voltage is 2.5 from the conventional 3.3 V), In the case of lowering to about V), as shown in Fig. 30C, the potential barrier 41 becomes higher, and more residual charge 45 is generated. As a result, afterimage and noise increase further, and also the sensitivity fall also becomes large, and it became a big problem practically.

As mentioned above, in recent years, the influence of stray light appears more strongly by the refinement | miniaturization of an element, and it has become easy to generate similar signals, such as smear and blooming. In addition, the potential barrier became higher due to the lower power supply voltage, and the afterimage and the noise were further increased. As described above, in the conventional solid-state imaging device, various noises are generated due to the miniaturization of elements and the demand for low power supply voltage, resulting in deterioration of device performance.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and to provide a solid-state imaging device capable of improving the performance of the device and a manufacturing method thereof.

BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows the manufacturing process of the solid-state imaging device which concerns on 1st Embodiment of this invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the first embodiment of the present invention following FIG. 1. FIG.

FIG. 3 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the first embodiment of the present invention following FIG. 2.

4 is a cross-sectional view illustrating a process of manufacturing the solid-state imaging device according to the first embodiment of the present invention following FIG. 3.

FIG. 5 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the first embodiment of the present invention following FIG. 4. FIG.

FIG. 6 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the first embodiment of the present invention following FIG. 5. FIG.

FIG. 7 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the first embodiment of the present invention following FIG. 6. FIG.

8 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

9 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

10 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

11 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

12 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

Fig. 13 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

Fig. 14 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

FIG. 15 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention. FIG.

Fig. 16 is a plan view showing a planar pattern of the silicide block layer 19 according to the first embodiment of the present invention.

17 is a graph comparing light reflectances between a first embodiment of the present invention and a conventional example.

18 is a cross-sectional view illustrating a process of manufacturing the solid-state imaging device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the second embodiment of the present invention following FIG. 18. FIG.

20 is a cross-sectional view illustrating a process for manufacturing the solid-state imaging device according to the second embodiment of the present invention following FIG. 19.

FIG. 21 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the second embodiment of the present invention following FIG. 20.

FIG. 22 is a cross-sectional view illustrating a manufacturing step of the solid-state imaging device according to the second embodiment of the present invention following FIG. 21.

FIG. 23 is a cross-sectional view illustrating the process of manufacturing the solid-state imaging device according to the second embodiment of the present invention following FIG. 22.

Fig. 24 is a view showing the drop of the potential barrier in the second embodiment of the present invention.

25 is a cross-sectional view illustrating a modification of the second embodiment of the present invention.

Fig. 26 is a cross-sectional view showing the manufacturing process of the solid-state imaging device according to the third embodiment of the present invention.

FIG. 27 is a cross-sectional view illustrating the process of manufacturing the solid-state imaging device according to the third embodiment of the present invention following FIG. 26.

FIG. 28 is a cross-sectional view illustrating the process of manufacturing the solid-state imaging device according to the third embodiment of the present invention following FIG. 27.

29 is a cross-sectional view showing a solid-state imaging device according to the prior art.

30 is a cross-sectional view of a solid-state imaging device for explaining the problem of the potential barrier in the prior art.

<Explanation of symbols for the main parts of the drawings>

1: silicon substrate

12: gate oxide film

13a, 13b, 13c: gate electrode

14a: N-type drain region

14b: N-type LDD region,

14c: P type LDD region

15: N-type signal storage region of the photodiode

16: silicon oxide film

16b: silicon oxide film

17 silicon nitride film

18, 32: photoresist film

19: silicide block layer

20: gate sidewall insulating film

21, 21a, 21b: P ⁺ type surface shield area

22a: P ⁺ type source / drain area

22b: N ⁺ type source / drain area

23: Ti / TiN film

24a, 24b, 33a, 33b: Ti silicide film

25: first interlayer insulating film

26: Al wiring

27: second interlayer insulating film

28: Al light shielding film

29: surface protective film

30: opening

31a, 31b, 31c: Selective Growth Silicon Layer

34: photodiode

This invention uses the means shown below in order to achieve the said objective.

The first solid-state imaging device of the present invention is provided with a first insulating film formed on a first conductive semiconductor substrate, a read gate electrode selectively formed on the first insulating film, and formed on the surface of the semiconductor substrate at one end of the read gate electrode. A diffusion region of a second conductivity type, a signal accumulation region of a second conductivity type formed on a surface of the semiconductor substrate at the other end of the read gate electrode, a surface shield region of a first conductivity type formed on a surface of the signal accumulation region, and the signal And a silicide block layer covering at least a portion of the accumulation region, and a metal silicide layer formed on the diffusion region.

A second solid-state imaging device of the present invention is provided with a first insulating film formed on a semiconductor substrate of a first conductivity type, a read gate electrode selectively formed on the first insulating film, and formed on the surface of the semiconductor substrate at one end of the read gate electrode. A second conductivity type diffusion region, a second conductivity type signal accumulation region formed on the surface of the semiconductor substrate at the other end of the read gate electrode, and a surface of the first conductivity type formed by selective epitaxial growth on the signal accumulation region It includes a shield area.

The third solid-state imaging device of the present invention further includes a silicide block layer covering at least a portion of the signal accumulation region and a metal silicide layer formed on the diffusion region in the second solid-state imaging device.

The second and third solid-state imaging devices may further include an elevated source drain formed by selective epitaxial growth on the diffusion region.

In the first and third solid-state imaging devices, the metal silicide layer may be any one of a Ti silicide film, a Co silicide film, a Ni silicide film, and a W silicide film.

In the first and third solid-state imaging devices, the silicide block layer is preferably a pattern covering at least a portion of the signal accumulation region and at least a portion of the read gate electrode. The silicide block layer may be a pattern covering at least a portion of the signal accumulation region, at least a portion of the read gate electrode, and at least a portion of the diffusion region.

In the second and third solid-state imaging devices, it is preferable that the lower surface of the surface shield region is located at the same height as the lower surface of the read gate electrode.

In the third solid-state imaging device, a gate electrode formed to be spaced apart from the read gate electrode by a predetermined interval, an elevated source / drain region formed by selective epitaxial growth at both ends of the gate electrode, and on the elevated source / drain region It may further comprise a metal silicide layer formed on.

The manufacturing method of the 1st solid-state imaging device of this invention is a process of forming a 1st insulating film on a 1st conductivity type semiconductor substrate, the process of selectively forming an element isolation region which isolate | separates an element region in the said semiconductor substrate, and the said element Forming a gate electrode through the first insulating film on the device isolation region, and forming a gate electrode through the first insulating film on the region, and forming a second gate on the surface of the device region of one end of the read gate electrode. Forming a conductivity type diffusion region, forming a second conductivity type signal accumulation region on the surface of the other end element region of the read gate electrode, forming a second insulating film on the front surface, surface of the diffusion region Removing the second insulating film to expose a portion of the second insulating film to form a silicide block layer covering at least a portion of the signal accumulation region; Forming a surface shield region of a first conductivity type on the surface of the red region, removing the first and second insulating films on the diffusion region, exposing the surface of the diffusion region, and diffusion in which the surface is exposed Forming a metal silicide layer on the region.

The manufacturing method of the 2nd solid-state imaging device of this invention is a process of forming a 1st insulating film on a 1st conductivity type semiconductor substrate, the process of selectively forming an element isolation region which isolate | separates an element region in the said semiconductor substrate, and the said element Forming a read gate electrode on the region through the first insulating film, forming a diffusion region of a second conductivity type on a surface of the element region of one end of the read gate electrode, and an element region on the other end of the read gate electrode And forming a second conductive signal accumulation region on the surface of the semiconductor substrate, and selectively epitaxially growing a silicon layer of the signal accumulation region to form a surface shield region of the first conductivity type.

The manufacturing method of the 3rd solid-state imaging device of this invention is a process of forming a 1st insulating film on a 1st conductivity type semiconductor substrate, the process of selectively forming an element isolation region which isolate | separates an element region in the said semiconductor substrate, and the said element Forming a read gate electrode on the region through the first insulating film, forming a diffusion region of a second conductivity type on a surface of the element region of one end of the read gate electrode, and an element region on the other end of the read gate electrode Forming a second conductivity type signal accumulation region on the surface of the semiconductor substrate; forming a surface shield region of the first conductivity type by epitaxially growing a silicon layer of the signal accumulation region; forming a second insulating film on the entire surface At least one of the signal accumulation region by removing the second insulating film to expose a surface of the selective growth silicon layer on the diffusion region A covering selection in the process, and the diffusion of the surface of the exposed region to form a silicide block layer growth has a step of forming a metal silicide layer on a silicon layer.

In the method for manufacturing the second and third solid-state imaging devices, the surface shield region may be formed by selectively growing a silicon layer which is not ion implanted and then ion implanting and heat treating the selective growth silicon layer. The surface shield region may be formed by selectively growing a silicon layer implanted with ions.

In the manufacturing method of the said 1st, 3rd solid-state imaging device, after forming the said metal silicide layer, you may further include the process of removing the said block layer.

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiment, the example of the CMOS image sensor produced using the microtechnology of 0.25 micrometer or less is shown. Therefore, in place of the LOCOS used in the prior art, an element isolation region having a shallow trench isolation (STI) structure, which is advantageous for miniaturization, is used. In addition, in the drawing demonstrated below, area | region A has shown the pixel area, and area | region B has shown the peripheral circuit area | region.

(1st embodiment)

The first embodiment is characterized in that a silicide film is formed on the source and drain regions, and a silicide block layer is formed on the photodiode. The manufacturing method of the solid-state imaging device which concerns on such 1st Embodiment is demonstrated.

First, as shown in FIG. 1, by using a known technique, a gate insulating film (silicon oxide film) 12 is formed on a P-type silicon substrate 11, and an element having an STI structure in the silicon substrate 11 is formed. An isolation region (hereinafter referred to as STI) is selectively formed. Next, an Nwell is formed in the P-MOS transistor formation region in the B region, and a Pwell is formed in the N-MOS transistor formation region. Next, gate electrodes 13a, 13b, and 13c made of polysilicon are selectively formed on the silicon substrate 11. Here, in the region A, the gate electrode formed on the element region shows the read gate electrode 13a, and the gate electrode formed on the STI shows the reset or address gate electrode 13b. Further, in the region B, reference numeral 13c shows the gate electrode of the MOS field effect transistor.

Next, by using the photolithography method and the ion implantation method, an N-type drain region 14a is formed on the surface of the silicon substrate 11 at the end of the read gate electrode 13a in the A region, and the N-MOS in the B region. An N-type LDD (Lightly Doped Drain) region 14b is formed in the source / drain region of the transistor. Next, the P-type LDD region 14c is formed in the source / drain region of the P-MOS transistor in the B region. Next, an N-type signal accumulation region 15 of the photodiode is formed on the surface of the silicon substrate 11 at the end of the read gate electrode 13a in the A region. Here, for example, phosphorus ions are used as ions implanted at the time of forming the N-type drain region 14a, the N-type LDD region 14b, and the N-type signal accumulation region 15. In addition, for example, boron ions are used as ions implanted at the time of formation of the P-type LDD region 14c. The order of forming the diffusion layer regions 14a, 14b, 14c by the ion implantation method may be different from the present embodiment.

In the present embodiment, a space 11a is provided between the signal accumulation region 15 of the photodiode and the STI end portion (the boundary between the STI and the element region). This space 11a is formed in order to conduct the surface shield region mentioned later and the silicon substrate 11 to conduct. Therefore, it is not necessary to provide a large space between the signal accumulation region 15 and the STI end portion, and a space may be provided at least partially. In addition, when the micro-defect is substantially not present in the STI end part and the junction leakage current of the photodiode does not increase substantially, the signal accumulation area 15 may be extended to the STI end part.

Next, as shown in FIG. 2, a silicon oxide film 16 having a film thickness of, for example, 10 to 30 nm is formed on the entire surface by using a reduced pressure CVD (Chemica 1 Vapor Deposition) method or the like. On (16), for example, a silicon nitride film 17 having a film thickness of 50 to 100 nm is formed. Further, a silicon oxide film 16b having a film pressure of 50 to 100 nm is formed on the silicon oxide film 17 by using a reduced pressure CVD method or the like. Thereafter, the photoresist film 18 is selectively formed on the silicon oxide film 16b above the signal accumulation region 15 of the photodiode by the photolithography method.

Next, as shown in FIG. 3, after removing the silicon oxide film 16b as a dilute hydrofluoric acid wet etching liquid using this photoresist film 18 as a mask, silicon | silicone was used using the reactive ion etching (RIE) technique. Dry etching the nitride film 17 to form a gate sidewall insulating film (sidewall insulating film) 20 on the side of the gate electrodes 13a, 13b, 13c, and at the same time, silicide on the signal accumulation region 15 of the photodiode. The block layer 19 is formed. Thereafter, the photoresist film 18 is removed.

Next, as shown in FIG. 4, the P ⁺ type surface shield region 21 is formed on the surface of the signal accumulation region 15 of the photodiode in the A region by using the photolithography method, the ion implantation method, and the heat treatment method. Form. As a result, a buried photodiode 34 of type P ⁺ NP which accumulates signal charges according to the amount of incident light is formed. Here, the surface shield region 21 shields the Si / SiO ₂ interface on the surface of the photodiode 34, thereby preventing the depletion layer by the signal accumulation region 15 from spreading to the Si / SiO ₂ interface. Complete. Therefore, generation of the leakage current by the Si / SiO ₂ interface level can be suppressed by the surface shield region 21. On the other hand, while the P ⁺ type surface shield region 21 is formed, source and drain regions 22a and 22b are formed in the element region in the B region. Here, the formation of the source of the N-MOS region and the drain region (22a) there is carried out an ion implantation of N ⁺ type, the formation of the source of the P-MOS region, a drain region (22b) is conducted an ion implantation of P ⁺ type Lose.

Next, as shown in FIG. 5, the silicon oxide film 12 on the gate electrodes 13a, 13b, 13c and the element region not covered with the silicide block layer 19 using a hydrofluoric acid-based etching solution is used. 16 is removed to expose the surface of the gate electrodes 13a, 13b, 13c and the surface of the silicon substrate 11. Next, pre-crystallization ion implantation is performed as a pre-process of metal silicideation mentioned later. This pre-crystallization ion implantation is performed using As ions under conditions of an acceleration voltage of, for example, 15 to 50 kV, and a dose amount of, for example, 10 ¹⁴ to 10 ¹⁵ cm ^-2 . Thereafter, a Ti film having a film thickness of, for example, 20 to 30 nm is formed on the entire surface as a silicide metal film by sputtering or the like, and TiN having a film thickness of, for example, 10 to 20 nm is formed on the Ti film. To form a film. Reference numeral 23 in Fig. 5 shows a silicide metal film made of a Ti film and a TiN film. The silicide metal is not limited to Ti, and high melting point metals such as Co, Ni, and W may be used, for example.

Next, as shown in FIG. 6, RTA (Rapid Therma1 Anneaing: Rapid Heating Annealing) is performed under conditions of a temperature of 600 to 700 ° C and a time of 30 to 60 seconds in a nitrogen atmosphere. As a result, the gate electrodes 13a, 13b, 13c and the silicon substrate 11 in the region where the element region and the silicide metal film 23 are in direct contact with each other are in the gate electrodes 13a, 13b, 13c and the silicon substrate 11. Silicon in the silicide metal film 23 reacts and the metal is silicided. Thereafter, the unreacted silicide metal film 23 is peeled off using H ₂ SO ₄ or HCl + H ₂ O ₂ solution, and the temperature is 700 to 800 ° C and the time is 20 to 30 seconds. RTA heat treatment is performed. As a result, a Ti silicide film (TiSi ₂ film) 24b, 24a metal-silicided on the surface of the gate electrodes 13a, 13b, 13c not covered by the silicide block layer 19 and on the silicon substrate 11. Is formed.

Thereafter, the silicide block layer 19 (or only the silicon nitride film 17 portion constituting the silicide block layer 19) may be removed by a dry or wet etching method. The advantage of leaving the silicide block layer 19 on the photodiode 34 is that since the silicon nitride film 17 has an intermediate refractive index between the silicon and the silicon oxide film, the surface of the photodiode 34 is affected by the multiple interference effect of light. Is that the light reflectance decreases, and the sensitivity is improved. On the other hand, the advantage of etching away the silicide block layer 19 on the photodiode 34 is that the silicon nitride film 17 having a film stress about 10 times higher than that of the silicon oxide film does not exist immediately below the photodiode 34. Therefore, the photodiode leakage current caused by stress can be reduced. In the embodiment of the present invention, the case where the silicide block layer 19 is left is described below.

Next, as shown in FIG. 7, after forming the 1st interlayer insulation film 25 in the whole surface, this 1st interlayer insulation film 25 is planarized by CMP (Chemica1 Mechanica1 Po1ish) technique. On this planarized first interlayer insulating film 25, an Al wiring 26 serving as a signal line, a connection wiring in the A region, and a connection wiring in the B region is selectively formed. Next, a second interlayer insulating film 27 is formed on the entire surface, and the second interlayer insulating film 27 is planarized by the CMP technique. An Al light shielding film 28 is formed on the planarized second interlayer insulating film 27, and the Al light shielding film 28 above the photodiode 34 is selectively removed. As a result, an opening 30 for injecting light into the photodiode 34 is formed. In addition, the entire surface of the region B is covered by the Al light shielding film 28. Thereafter, a surface protective film 29 such as a silicon nitride film is formed on the entire surface.

In the solid-state imaging device formed as described above, the planar pattern of the silicide block layer 19 in the region A will be described below.

FIG. 8 is a top view of region C of FIG. 6. As shown in Fig. 8, a photodiode 34 adjacent to one end of the gate electrode 13a of the read transistor is formed, and the gate electrode 13b of the reset transistor or the address transistor spaced apart from the photodiode 34 is formed. ) Is formed. The drain region 14a adjacent to the other end of the gate electrode 13a of the read transistor is formed. A silicide block layer 19 is formed to cover the entire surface of the photodiodes 21 and 15 and partially cover both of the gate electrodes 13a and 13b.

9 to 11 show a modification of the silicide block layer pattern covering the entire surface of the photodiode 34.

9 illustrates a case where the silicide block layer 19 partially covers only one of the gate electrodes 13a and 13b. FIG. 10 shows a case where the silicide block layer 19 covers the gate electrodes 13a and 13b in both directions. FIG. 11 shows a case where the silicide block layer 19 partially covers one side of the gate electrodes 13a and 13b and crosses the other.

As shown in FIGS. 10 and 11, when the silicide block layer 19 covers the gate electrodes 13a and 13b, the area of the unsilicided gate electrodes 13a and 13b is large, so that the wiring resistance is increased. Will grow. This is because the resistance side in the case of metal silicide is usually about one order smaller when the metal silicided case is compared with the polysilicon wiring resistance in the case of no metal silicide case. Therefore, when driving the pixel signal at high speed (when the number of pixels or the frame frequency is high), it is preferable to use the patterns of the silicide block layer 19 as shown in Figs. .

12 to 15 show a modification of the silicide block layer pattern partially covering the photodiode 34, the present invention is effective even when using such a silicide block layer pattern. Rather, a portion of the surface of the photodiode 34 covered with a metal silicide film such as a TiSi ₂ film having a low light reflectance is effective for suppressing stray light. However, in the metal silicided photodiode portion, the junction leakage current increases, and there is a concern that the noise in the dark increases all the time. Of course, it is necessary to select an appropriate silicide block layer pattern from the balance between stray light suppression and low dark noise.

As shown in FIG. 16, the entire surface of the drain region 14a may be covered with the silicide block layer 19. In this case, the increase in the junction leakage current by the metal silicide of the drain region 14a is eliminated. For this reason, when the signal charge is transferred to the drain region 14a, the noise generated thereafter can be reduced.

Fig. 17 shows the surface light reflectance of the metal silicide film (typical TiSi ₂ film, CoSi ₂ film) and conventional silicon (Si) used in the present invention. In FIG. 17, the value of the light reflectance measured when the sample was installed in air | atmosphere and light was made to incident in 8 degree of incidence angle is shown.

As shown in Fig. 17, in the visible region having a wavelength of 300 to 700 nm, the light reflectance of TiSi ₂ and CoSi ₂ is clearly smaller than that of conventional silicon. In particular, in the case of CoSi ₂ , the light reflectance in the visible region can be made very small (30% or less).

As a result of the present invention performed by the present inventors and the like, when the TiSi ₂ film is used, the amount of generation of similar signals due to stray light in adjacent pixels can be reduced to about 60% of conventional silicon. In addition, when CoSi ₂ having a low reflectance was used, the amount of generation of similar signals due to stray light in adjacent pixels could be reduced to about 30% of conventional silicon. In addition, in the case of using a NiSi ₂ or WSi _2, to obtain the same effect as TiSi ₂ or CoSi _2.

According to the first embodiment, the Ti silicide film 24a having a low light reflectance is formed on the drain region 14a and the source / drain regions 22a and 22b. Therefore, since reflection of stray light can be prevented, generation of a similar signal (smear or blooming) by stray light can be sufficiently suppressed. In addition, because stray light reaches the peripheral circuit can be suppressed, it is possible to prevent malfunction of the transistor. In this manner, similar signals and malfunctions can be prevented, and the performance of the device can be improved.

In addition, a silicide block layer 19 is formed on the photodiode 34. When the silicide block layer 19 is left, it is possible to reduce the reflection component of light incident on the photodiode 34 from the upper side by about 10 to 30% by the multilayer thin film optical interference effect. Therefore, the conventional solid-state imaging device of about 1.2 times higher light sensitivity can be realized.

On the other hand, when the silicide block layer 19 is removed after the Ti silicide films 24a and 24b are formed, a sufficient amount to be supplied by the sintering process without being blocked by the silicon nitride film 17 of the silicide block layer 19. Of hydrogen atoms can reach the photodiode 34. Therefore, since a sufficient sintering effect is obtained, it is effective for reducing the leakage current of the photodiode 34. The sintering step is a step of forming a plasma nitride film containing a large amount of hydrogen in the vicinity of the final step, followed by heat treatment at 450 ° C. for about 30 minutes to diffuse hydrogen atoms to the silicon substrate. Inactivation has the effect of reducing junction leakage current.

In addition, by forming the silicide block layer 19, it is possible to prevent the silicide film having a very low light transmittance (about 20% or less) from being formed on the photodiode 34. Therefore, since sufficient incident light amount can be supplied to the photodiode 34, even when a CMOS image sensor is manufactured using a silicide process, a solid-state imaging device with high light sensitivity can be realized. In addition, since crystal defects due to suicide are not introduced into the photodiode 34, the junction leakage current of the photodiode 34 can be reduced. Therefore, it is possible to reduce the white defect image defect output resulting in a decrease in yield and the dark time spot output due to the variation of the leakage current resulting in image quality deterioration.

In addition, the silicide block layer 19 has a three-layer structure of the silicon oxide film 16, the silicon nitride film 17, and the silicon oxide film 16b. The following effects are obtained.

First, the effect of the silicon oxide film 16b is as follows. When a silicide annealing is performed by depositing a metal film such as a Ti / TiN film directly on the silicon nitride film 17, the surface of the silicon nitride film 17 is slightly, but the metal silicide is formed. As a result, there arises a problem that the amount of light directly incident on the port diode is reduced, but this problem can be solved by forming the silicon oxide film 16b on the silicon nitride film 17.

Next, the effect of the silicon nitride film 17 is as follows. Since the silicon nitride film 17 has a refractive index between the silicon and the silicon oxide film, the light reflectance on the surface of the photodiode can be reduced. As a result, the amount of light incident on the port diode is increased, and the sensitivity is improved.

In addition, the effect of the silicon oxide film 16 is as follows. The silicon nitride film 17 has a large film stress of about 10 times that of the silicon oxide film. Therefore, without the silicon oxide film 16, the silicon nitride film 17 is very close to the photodiode through the thin gate oxide film 12, increasing the leakage current due to stress. Here, the silicon oxide film 16 having a film thickness of 10 to 30 nm functions as a stress relaxation layer and can prevent an increase in photodiode leakage current due to the stress of the silicon nitride film 17.

In addition, although a manufacturing process using a P-type silicon substrate is shown in the first embodiment, of course, a P-type well may be formed in place of the P-type silicon substrate.

In addition, intermediate refractive index films, such as Ti and TiN films, may be provided on the upper and lower surfaces of the Al wiring 26 and the Al light shielding film 28. By providing this intermediate refractive index film, light reflection can be further controlled.

(2nd embodiment)

The second embodiment is characterized in that the surface shield region and the elevated source and drain are formed using the epitaxial growth method. In addition, in 2nd Embodiment, the method similar to the said 1st Embodiment is simplified, and it demonstrates only another method in detail. Hereinafter, the manufacturing method of the solid-state imaging device which concerns on 2nd Embodiment is demonstrated.

First, as shown in FIG. 18, by using a known technique, a gate insulating film (silicon oxide film) 12 is formed on the silicon substrate 11, and an element isolation region having an STI structure (in the silicon substrate 11) is formed. Hereinafter referred to as STI). Next, an Nwell is formed in the P-MOS transistor formation region in the B region, and a Pwell is formed in the N-MOS transistor formation region. Next, gate electrodes 13a and 13c made of polysilicon are selectively formed on the silicon substrate 11.

Next, as shown in FIG. 19, an N-type drain region 14a is formed on the surface of the silicon substrate 11 at the end of the gate electrode 13a in the A region by using the photolithography method and the ion implantation method. The N-type LDD region 14b is formed in the source / drain region of the N-MOS transistor region in the B region. Next, the P-type LDD region 14c is formed in the source / drain region of the P-MOS transistor region in the B region. Next, an N-type signal accumulation region 15 of the photodiode is formed on the surface of the silicon substrate 11 at the end of the gate electrode 13a in the A region.

Next, as shown in FIG. 20, a silicon oxide film (or silicon nitride film) is formed over the entire surface. This silicon oxide film is dry-etched using the RIE technique to form the gate sidewall insulating film 20 on the side surfaces of the gate electrodes 13a and 13c. Thereafter, the gate insulating film 12 is removed with a hydrofluoric acid etchant to expose the surface of the cleaned silicon substrate 11.

Next, as shown in FIG. 21, the undoped selective growth silicon layers 31a, 31b, and 31c are selected on the surfaces of the silicon substrate 11 and the gate electrodes 13a and 13c by selective epitaxial growth. To grow. Here, in order to selectively grow the selective growth silicon layers 31a, 31b, and 31c, for example, 50 Torr and a substrate temperature of 850 using a reduced pressure CVD method using a mixed gas of dichlorosilane, hydrogen, and hydrochloric acid as raw materials. What is necessary is just to carry out on condition of ° C. Further, the growth time is set so that the film thicknesses of the selective growth silicon layers 31a, 31b, 31c become a desired value in the range of 20 to 200 nm.

Although the example in which the selective growth silicon layer 31c is formed on the gate electrodes 13a and 13c is shown, if an insulating film such as a silicon oxide film is left on the gate electrodes 13a and 13c before the selective epitaxial growth, Naturally, no silicon layer is formed on the gate electrodes 13a and 13c. According to the spirit of the present invention, the silicon layer need not be formed on the gate electrodes 13a and 13c.

Next, as shown in FIG. 22, the photoresist film 32 is formed and patterned on the whole surface, and an opening is formed in the signal accumulation area 15 of a photodiode. Using the patterned photoresist film 32 as a mask, the selective growth silicon on the signal accumulation region 15 under conditions of an acceleration voltage of 30 keV and a dose of 4 x 10 ¹³ cm ^-2 , for example. Boron ions such as BF ₂ ions are implanted into the layer 31a.

Next, as shown in FIG. 23, the photoresist film 32 is peeled off and desired heat processing is performed. As a result, the selective growth silicon layer 31a is P ⁺ shaped (concentrations 10 ¹⁸ to 10 ²⁰ atoms / cm ³ ), so that the shield region 21a is formed on the surface of the signal accumulation region 15 of the photodiode. As a result, a P ⁺ NP type photodiode which accumulates the signal charge according to the incident light amount is formed.

Further, since the selective growth silicon layer 21a has a facet surface, the film thickness of the selective growth silicon layer 31a in contact with the gate sidewall insulating film 20 end or the STI end is thin. For this reason, when boron is ion-implanted (shown in FIG. 22), boron is ion-implanted deeper in the part (part A) in which the film thickness of the selective growth silicon layer 31a becomes thin. Accordingly, the surface shield region 21a is slightly formed in the portion A, and is formed deep under the surface of the silicon substrate 11. It goes without saying that the concentration profile shape of the surface shield region 21a shown in FIG. 23 can be arbitrarily set by adjusting the acceleration voltage and the dose amount of the ion implantation when the surface shield region 21a is formed.

FIG. 24A shows a cross-sectional view of the buried photodiode structure which is a part of region A of FIG. 24B and 24C show potential cross-sectional views at the time of low voltage reading (when the read gate electrode is ON), and FIG. 24C is read at a lower voltage than that of FIG. 24B. The case is illustrated. Here, FIG. 24B shows the case where the voltage is 3.3V, and FIG. 24C shows the case where the voltage is 2.5V.

As shown in Fig. 24A, the surface shield region 21a is formed using the selective growth silicon layer 31a as a matrix. For this reason, the upper surface of the surface shield region 21a is located above the lower surface of the gate electrode 13a, and the lower surface of the surface shield region 21a is located slightly below the lower surface of the gate electrode 13a. .

Therefore, the surface shield region 21a can be formed much shallower with respect to the lower surface of the read gate electrode 13a than in the conventional structure shown in FIG. 30 (a). As a result, as shown in Figs. 24B and 24C, when reading out the signal electrons accumulated in the signal accumulation region 15, the conventional method (Figs. 30B and 30C) is performed. The potential barrier, as shown, effectively disappears, leaving no residual charge.

According to the second embodiment, the surface shield region 21a is formed on the silicon substrate 11 by using the selective epitaxial growth method. Therefore, at the time of signal reading, the potential barrier existing at the end of the surface shield region 21a and the end of the read gate electrode 13a effectively disappears, so that residual charge is accumulated in the signal accumulation region 15 of the photodiode. It will not remain effectively. This realizes complete transmission of the signal electrons. As a result, in the case where the conventional buried photodiode structure is used, problems such as high afterimage, high noise and low sensitivity, which have been a problem in the case of low voltage reading, can be solved, and the performance of the device can be improved.

In addition, the selective growth silicon layer 31b is formed on the silicon substrate 11 by using the selective epitaxial growth method. Therefore, the source / drain region can be made an elevated source / drain. As a result, the generation of leakage current can be prevented in the pixel region, and the resistance can be reduced in the peripheral circuit region.

In addition, by forming an elevated source and drain in the peripheral circuit region, even when the N-type drain region 14a is shallowly formed in the silicon substrate 11, the junction leakage current after metal silicide formation can be sufficiently suppressed. As a result, the N-type drain region can be formed shallow in the pixel region. For this reason, the problem of the punchthrough between the signal accumulation region 15 and the drain region 14a generated when the length of the read gate electrode 13a is shortened can be suppressed. Therefore, since the read gate electrode length can be shortened, miniaturization of the pixel size can be realized.

In addition, in the second embodiment, the formation of the surface shield region 21a is performed by selective growth of the undoped silicon layer (shown in FIG. 21), boron ion implantation (shown in FIG. 22), and heat treatment. Although shown, it is not limited to this method.

For example, a P ⁺ type silicon layer implanted with boron may be selectively grown. When selectively growing the P ⁺ type silicon layer from the beginning, it is possible to omit the boron ion implantation or the heat treatment after the ion implantation. In this way, when the surface shield region 21a is formed, not only the same effect as in the second embodiment is obtained, but also the following effects are obtained.

First, since the defect by the boron ion implantation process is not introduced into the photodiode, the junction leakage current of the photodiode can be reduced. In addition, since boron is not injected deeper in the lower region of the facet surface, as shown in FIG. 25, the lower surface of the surface shield region is located at the same height as the lower surface of the gate electrode. That is, the lower surface of the surface shield region 21b can be formed more planar and shallower. For this reason, the potential barrier at the time of signal reading is further lowered, so that perfect transfer can be realized even under a low voltage read condition of 2 V or less.

(Third embodiment)

As in the first embodiment, the third embodiment is characterized in that a silicide film is formed on the source and drain regions, and a silicide block layer is formed on the photodiode. In addition, as in the second embodiment, the epitaxial growth method is used to form the surface shield region and the elevated source and drain. In addition, in 3rd Embodiment, description is abbreviate | omitted about the process similar to the said 2nd Embodiment, and only another process is demonstrated. Hereinafter, the manufacturing method of the solid-state imaging device which concerns on 3rd Embodiment is demonstrated.

First, as shown in FIGS. 18 to 23, as in the second embodiment, the epitaxially grown surface shield region 21a is formed on the surface of the signal accumulation region 15 of the photodiode.

Next, as shown in FIG. 26, a silicon oxide film 16 having a film thickness of, for example, 20 to 50 nm is formed on the entire surface by using a reduced pressure CVD method or the like, and on this silicon oxide film 16. For example, a silicon nitride film 17 having a film thickness of 50 to 100 nm is formed. Further, a silicon oxide film 16b having a film pressure of 50 to 100 nm is formed on the silicon nitride film 17 by using a reduced pressure CVD method or the like. Thereafter, a photoresist film (not shown) is formed above the signal accumulation region 15 of the photodiode by the photolithography method. Using the photoresist film as a mask, the silicon nitride film 17 and the silicon oxide film 16 are dry-etched by the RIE technique to form the silicide block layer 19 on the signal accumulation region 15 of the photodiode. This silicide block layer 19 prevents the suicide of the surface shield region 21a in the subsequent silicide process.

Next, as shown in FIG. 27, the conductivity type is the same as the signal accumulation region 15 under the condition that the acceleration voltage is, for example, 10 to 50 kV, and the dose amount is, for example, 10 ¹³ to 10 ¹⁵ cm ^-2 . Impurity ions, such as As ions, are injected into the front surface. As a result, at least the surface vicinity of the selective growth silicon layers 31b and 31c in the region not covered by the silicide block layer 19 is amorphous.

Next, as shown in FIG. 28, a Ti film (not shown) having a film thickness of, for example, 20 to 40 nm is formed on the entire surface by a sputtering method or the like, and, for example, 10 is formed on the Ti film. A TiN film (not shown) having a film thickness of from 30 nm is formed. Next, in a nitrogen atmosphere, annealing is performed for about 30 second on the temperature conditions in 700-800 degreeC. As a result, the silicon in the selective growth silicon layers 31b and 31c reacts with the Ti in the Ti film, thereby forming Ti silicide films 33a and 33b at the interface between the selective growth silicon layers 31b and 31c and the Ti film. . Thereafter, the TiN film and the unreacted Ti film are etched away using a mixture of sulfuric acid and hydrogen peroxide solution or the like. In this manner, the Ti silicide films 33a and 33b are formed on the selective growth silicon layers 31b and 31c not covered with the silicide block layer 19.

According to the said 3rd Embodiment, the effect similar to 1st Embodiment and 2nd Embodiment is acquired.

In addition, this invention can be variously modified and implemented in the range which does not deviate from the summary.

As described above, according to the present invention, it is possible to provide a solid-state imaging device and a manufacturing method thereof capable of improving the performance of the device.

Claims (17)

delete A first insulating film formed on the first conductive semiconductor substrate, A read gate electrode selectively formed on the first insulating film; A diffusion region of a second conductivity type different from the first conductivity type formed on the surface of the semiconductor substrate at one end of the read gate electrode; A signal accumulation region of a second conductivity type different from the first conductivity type formed on the surface of the semiconductor substrate at the other end of the read gate electrode; A surface shield region of a first conductivity type formed by selective epitaxial growth on the signal accumulation region Solid-state imaging device comprising a. The method of claim 2, A solid-state imaging device, wherein the first conductive semiconductor substrate is a well layer or an epitaxial layer. The method of claim 2, A silicide block layer covering at least a portion of the signal accumulation region; And And a metal silicide layer formed on said diffusion region. The method of claim 2, And an elevated source drain formed by selective epitaxial growth on the diffusion region. delete delete delete The method of claim 2, A lower surface of the surface shield region is located at the same height as the lower surface of the read gate electrode. The method of claim 4, wherein A gate electrode formed to be spaced apart from the read gate electrode at a predetermined interval; An elevation source and drain region formed by selective epitaxial growth on both ends of the gate electrode; And A metal silicide layer formed on the elevated source and drain regions Solid-state imaging device further comprises. delete Forming a first insulating film on the first conductive semiconductor substrate; Selectively forming an element isolation region for separating the element region in the semiconductor substrate; Forming a read gate electrode on the device region with the first insulating film interposed therebetween; Forming a diffusion region of a second conductivity type different from that of the first conductivity type on the surface of one end of the element region of the read gate electrode; Forming a signal accumulation region of a second conductivity type different from the first conductivity type on the surface of the element region at the other end of the read gate electrode; Selectively epitaxially growing a silicon layer of the signal accumulation region to form a surface shield region of a first conductivity type Method of manufacturing a solid-state imaging device comprising a. Forming a first insulating film on the first conductive semiconductor substrate, Selectively forming an element isolation region for separating the element region in the semiconductor substrate; Forming a read gate electrode on the device region with the first insulating film interposed therebetween; Forming a diffusion region of a second conductivity type different from that of the first conductivity type on the surface of one end of the element region of the read gate electrode; Forming a signal accumulation region of a second conductivity type different from the first conductivity type on the surface of the element region at the other end of the read gate electrode; Selectively epitaxially growing a silicon layer of the signal accumulation region to form a surface shield region of a first conductivity type; Forming a second insulating film on the entire surface; Removing the second insulating film to expose a surface of the selective growth silicon layer on the diffusion region, thereby forming a silicide block layer covering at least a portion of the signal accumulation region; Forming a metal silicide layer on the selective growth silicon layer on the diffusion region where the surface is exposed; Method of manufacturing a solid-state imaging device comprising a. The method according to claim 12 or 13, A method for manufacturing a solid-state imaging device, wherein the first conductive semiconductor substrate is a well layer or an epitaxial layer. The method according to claim 12 or 13, And the surface shield region is formed by selectively growing a silicon layer which is not ion implanted, followed by ion implantation and heat treatment to the selective growth silicon layer. The method according to claim 12 or 13, And said surface shield region is formed by selectively growing a silicon layer implanted with an ion. The method of claim 13, And after the metal silicide layer is formed, removing the block layer.