JP5567259B2 - Silicon wafer and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon wafer used for manufacturing a semiconductor device, and particularly to a silicon wafer having a high stress resistance and high-quality crystallinity in a surface layer portion serving as a device active region, and a manufacturing method thereof.

  Silicon wafers are required to have higher quality crystals as semiconductor devices become more highly integrated and more functional. Recently, the wafer manufacturing technology that has been regarded as important is related to the formation of a defect-free layer (Denuded Zone: hereinafter referred to as “DZ layer”) on the surface of the silicon wafer, and solid solution oxygen that affects the mechanical strength of the silicon wafer. Some are related to concentration control.

  For forming a high-quality DZ layer, an annealed wafer obtained by performing heat treatment at 1100 ° C. or higher and 1300 ° C. or lower in a non-oxidizing gas atmosphere on a silicon wafer (see, for example, Patent Document 1), or a silicon epitaxial layer on a silicon wafer There is an epitaxial wafer in which this is applied as a DZ layer (see, for example, Patent Document 2). In this DZ layer, COP (Crystal Originated Particle: hereinafter referred to as “COP”) or LSTD (Laser Scattering Tomography Defect) or the like on the wafer surface is effectively eliminated. In addition, generation of BMD (Bulk Micro Defect: hereinafter referred to as “BMD”), which is a precipitate of interstitial oxygen, is suppressed.

In addition, as a control of the dissolved oxygen concentration, when the annealing wafer is subjected to a heat treatment such as oxidation in device manufacturing, the dissolved oxygen concentration decreases from the surface in the thickness direction and has a minimum value. Yes (see, for example, Patent Document 3). With this structure, there is an effect of preventing oxygen precipitation in the device active region due to the presence of the region of the minimum value and improving the device manufacturing yield.
Further, a rapid thermal annealing (hereinafter referred to as “RTA”) is performed on the wafer after polishing (mirror polishing) in an oxidizing gas atmosphere without performing the above-described heat treatment in a non-oxidizing gas atmosphere. (For example, refer to Patent Document 4). With this method, the concentration of dissolved oxygen has a maximum value at the wafer surface layer.
Japanese Patent No. 3294722 JP 2006-188423 A JP-A-6-36979 JP 2000-31150 A

  However, the annealed wafer of Patent Document 1 and the epitaxial wafer of Patent Document 2 inevitably reduce the solid solution oxygen concentration at the wafer surface layer due to the manufacturing method, so that the mechanical strength is reduced on the wafer surface and dislocations are generated. Occurrence / proliferation is easily generated and propagated, and the manufacturing yield of semiconductor devices decreases. In addition, it has become impossible to expect to compensate for dissolved oxygen in the surface layer of the wafer during the device manufacturing process in order to lower the temperature and shorten the time of the device manufacturing process.

  On the other hand, when the annealed wafer of Patent Document 3 is subjected to additional heat treatment to increase the oxygen concentration on the wafer surface as compared with the annealed wafer, an effect of preventing the deterioration of the stress resistance on the surface occurs. However, in this example where the concentration of dissolved oxygen is extremely high on the surface and decreases in the thickness direction, it can be said that it is still insufficient in terms of ensuring the stress resistance in the device formation region. This is because the semiconductor device is formed in a region from the wafer surface to a certain depth, so that it is necessary that the concentration of dissolved oxygen in the surface layer portion that becomes the depth region or the device active region is high. .

When the RTA process is performed on the polished silicon wafer of Patent Document 4, since the distribution has a maximum value of the dissolved oxygen concentration in a certain range from the surface of the silicon wafer in the thickness direction, the high oxygen concentration Sufficient stress resistance due to the effect is secured. However, if COP and BMD exist in the wafer surface layer before the RTA process, they cannot be eliminated by the RTA process, which leads to a decrease in yield due to a semiconductor device leakage failure. For this reason, it is necessary to use a crystal with very little COP and BMD in the surface layer portion of the wafer as a wafer before RTA processing. As this crystal, for example, there is a so-called Neutral crystal in which the pulling conditions are controlled with high precision. However, since such a low-defect crystal has low crystal growth productivity and high cost, the cost of the crystal and the cost of the RTA treatment are combined. Then, it exceeds the yield improvement at the time of device manufacture by the technique of Patent Document 4, resulting in poor practicality.
Further, in this RTA-processed wafer, a large amount of dissolved oxygen exists inside the wafer surface layer portion, and when the heat treatment process of device manufacture is repeated, thermal diffusion flows into the surface layer portion and BMD precipitation is likely to occur. And the yield fall at the time of device manufacture becomes easy to occur.

  Therefore, in order to cope with a miniaturized device structure that increases the stress on the wafer surface more than before, or a device manufacturing process that is reduced in temperature and time, it is suitable for the surface layer of the wafer before the device manufacturing process is introduced. There has been a demand for a silicon wafer having a stable solid solution oxygen concentration distribution and having sufficient dislocation generation / proliferation suppression and dislocation pinning ability.

  Moreover, it is preferable that this silicon wafer is such that grow-in defects such as COP disappear in the wafer surface layer portion, the amount of BMD is suppressed, and BMD is hardly generated in the heat treatment process of device manufacturing. Further, it is desired that the silicon wafer can be easily manufactured and its cost is reduced.

  In view of the above circumstances, an object of the present invention is to provide a silicon wafer in which a surface layer portion serving as a device active region has high stress resistance and high-quality crystallinity, and a method for manufacturing the same.

  The silicon wafer of the present invention is a silicon wafer having two main surfaces facing each other, and the solid solution oxygen concentration continuously changes in the thickness direction, wherein the solid solution oxygen concentration is at least one of the main surfaces. A first region that increases from the value of the first region, and a second region that decreases from the maximum value of the first region, and a thickness central portion from the minimum value of the second region toward the thickness direction. It is characterized by changing so as to increase to the value of.

  In the silicon wafer of the present invention, the maximum value of the dissolved oxygen concentration in the first region is the largest value in the thickness direction, and the minimum value in the second region is the smallest value in the thickness direction. It is preferable that

Furthermore, the silicon wafer of the present invention preferably has a solid solution oxygen concentration value on the main surface of 1.0 × 10 ¹⁷ atoms / cm ³ or more and 8.0 × 10 ¹⁷ atoms / cm ³ or less.

In the silicon wafer of the present invention, the first region exists at a depth of 0.2 μm or more and 2.0 μm or less from the main surface, and the maximum value is 7.0 × 10 ¹⁷ atoms / cm ³ or more and 1.8. It is preferable to set it as x10 < ¹⁸ > atoms / cm < ³ > or less.

In the silicon wafer of the present invention, the second region exists at a depth of 12 μm or less from the main surface, the minimum value is 1.0 × 10 ¹⁷ atoms / cm ³ or more, and 1/5 of the maximum value. The following is preferable.

  The method for producing a silicon wafer according to the present invention includes a step of performing heat treatment on a silicon wafer at a temperature of 1100 ° C. to 1300 ° C. for 5 minutes to 120 minutes in a non-oxidizing gas atmosphere, and an oxygen-containing gas atmosphere. The step of raising the temperature at a rate of temperature rise of 10 ° C./sec (seconds) to 100 ° C./sec, the step of holding at a temperature of 1150 ° C. to 1350 ° C. after the temperature rise, and holding for 5 seconds to 60 sec. After the completion, a step of lowering the temperature at a temperature lowering rate of 1 ° C./sec or more and 100 ° C./sec or less is sequentially performed.

  According to the configuration of the present invention, the solid solution oxygen in the surface layer portion of the silicon wafer is adjusted to an appropriate concentration before the semiconductor device manufacturing process is introduced, and the surface layer portion serving as the device active region has high stress resistance and further high resistance. A silicon wafer having high-quality crystallinity is easily provided at low cost.

  Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a graph for explaining the distribution of the dissolved oxygen concentration of the silicon wafer according to this embodiment. FIG. 2 is a diagram showing an example of a temperature process for producing an annealed wafer and introducing oxygen into the surface layer portion. FIG. 3 is an explanatory view showing an example of a heat treatment process in introducing oxygen into the surface layer of the silicon wafer.

  The silicon wafer according to the present embodiment is a silicon wafer having two main surfaces facing each other and having a solid solution oxygen concentration continuously changing in the thickness direction thereof, wherein the solid solution oxygen concentration has at least one main surface. A first region that increases from the value in the first region and a second region that decreases from the maximum value of the first region, and a thickness center from the minimum value of the second region toward the thickness direction. It changes so that it may increase to the value of a part.

  Here, the two main surfaces that face each other are a mirror-finished surface that forms a semiconductor device and a back side opposite to the surface, and the thickness direction is perpendicular to the main surface and toward the center of the thickness. Point in direction. Moreover, although the thickness center part refers to the position of equal intervals from two main surfaces with respect to the thickness direction of a silicon wafer, it does not need to be exactly equal intervals. Substantially, the oxygen concentration in the depth direction from the wafer surface is measured by SIMS (Secondary Ion Mass Spectrometry), and it represents a region having a depth of 50 μm or more in which there is almost no change in the oxygen concentration. Further, the solid solution oxygen is oxygen existing between lattices formed by silicon atoms constituting the wafer base material, and the solid solution oxygen concentration is measured from the main surface of the silicon wafer to the thickness central portion by SIMS. Is measured.

As shown by the solid line (a) in FIG. 1, the solid solution oxygen concentration of the silicon wafer increases from one main surface in the thickness direction, passes through its maximum value, then decreases, and after passing through its minimum value. The distribution increases toward the inside of the wafer. Here, the first region is from the wafer surface to the depth having the maximum value, and the second region is from the depth having the maximum value to the depth having the minimum value. Further, the third region is defined from the minimum depth to the thickness central portion inside the wafer.
This distribution of the dissolved oxygen concentration can be easily obtained by subjecting the annealed wafer having the dissolved oxygen concentration distribution as shown by the broken line (b) in FIG. Similarly, a similar solute oxygen concentration distribution can be formed for an epitaxial layer which is a device formation region of an epitaxial wafer.

First, the operation and effect of the first region will be described. When the solid solution oxygen concentration increases from the wafer surface in the thickness direction, it is attracted to the stress field of dislocations generated on the wafer surface layer in the device manufacturing process, and the dislocations can be easily pinned. it can. This effect is prominent when the concentration of dissolved oxygen on the wafer surface is less than 1 × 10 ¹⁷ atoms / cm ^{3 as} in the case of an annealed wafer or an epitaxial wafer. In addition, since the dissolved oxygen is reduced on the wafer surface on which the finely structured semiconductor element is manufactured, the occurrence of BMD in the surface layer of the wafer, which deteriorates the characteristics of the semiconductor element, is effectively suppressed in the heat treatment process of device manufacturing. The
The pinning effect of dislocations in the present embodiment is that the concentration of solid solution oxygen is high toward the thickness direction as in the wafer described in Patent Document 3, which is shown as an example of the prior art in FIG. It appears much more prominently than the gradually falling shape. In addition, it is easier to control the suppression of BMD generation on the wafer surface than in the case of the one-dot chain line (c) in FIG.

  In the embodiment of the present invention in which the second region having the minimum value follows the first region having the maximum dissolved oxygen concentration, the concentration gradient of the dissolved oxygen due to the difference between the maximum value and the minimum value is large. Therefore, the heat diffusion flow amount of oxygen from the first region having the maximum value to the second region having the minimum value is increased by the heat treatment process of the device manufacturing, and precipitation of solid solution oxygen in the wafer surface layer portion is reduced. Acts as follows. Therefore, even if the maximum value of the oxygen concentration in the first region is high and the device is oversaturated in the heat treatment process for manufacturing the device, new BMD generation due to oxygen precipitation on the wafer surface layer portion is effectively suppressed.

  Further, the embodiment of the present invention is different in that it has a region having a high oxygen concentration in the vicinity of the wafer surface layer as compared with the oxygen concentration profile of the annealed wafer. This is because the annealed wafer has a low-defect region on the surface layer, but the oxygen concentration is low, resulting in insufficient wafer strength and a large number of dislocations. The present invention, which has an appropriate oxygen concentration region near the surface layer, compensates for this defect. However, it can be said that it is excellent in that a high-quality wafer having a low defect area on the surface layer can be realized.

  While the first and second regions act directly on the device formation region to give the desired effect on strength and precipitation, the dissolved oxygen concentration increases from the minimum value to the value at the center of the thickness of the silicon wafer The third region is set so that the dissolved oxygen concentration distribution other than the vicinity of the surface layer portion is the same as the state of the annealed wafer. If it is not the third region set in this way, there is a possibility that an action other than the effect obtained from the first and second regions may occur, and this is not preferable for the present invention to exert the effect reliably and stably.

  In the silicon wafer of this embodiment, the maximum value of the dissolved oxygen concentration in the first region is the largest value in the thickness direction, and the minimum value in the second region is the smallest value in the thickness direction. It is preferable that

  The position where the value of the solid solution oxygen concentration is higher than the maximum value of the solid solution oxygen concentration in the first region is the highest in the solid solution oxygen concentration value in the central portion in the thickness direction of the third region. It is a case. By increasing the maximum value of the first region above the solid solution oxygen concentration in the central portion, the tolerance to high stress locally generated on the wafer surface due to semiconductor element miniaturization or device manufacturing heat treatment is increased. be able to.

  The position where the solid solution oxygen concentration value is lower than the minimum value of the solid solution oxygen concentration in the second region is the case where the solid solution oxygen concentration value on the wafer surface is the lowest. In this case, the thermal diffusion amount of oxygen flowing from the first region during the heat treatment is larger on the wafer surface side than the minimum value of the second region. Then, in the heat treatment process for manufacturing the device, the dissolved oxygen in the first region diffuses outward from the wafer surface, and the dissolved oxygen in the wafer surface layer portion is reduced. Therefore, by making the minimum value of the second region smaller than the solid solution oxygen concentration on the wafer surface, the amount of thermal diffusion of oxygen becomes larger toward the minimum value of the second region. Thereby, the reduction of the dissolved oxygen in the wafer surface layer portion is effectively suppressed, and the effect of fixing dislocations in the device manufacturing process is sustained.

The silicon wafer of the present invention preferably has a solid solution oxygen concentration value on the main surface of 1.0 × 10 ¹⁷ atoms / cm ³ or more and 8.0 × 10 ¹⁷ atoms / cm ³ or less. If the value of the dissolved oxygen concentration on the surface of the silicon wafer is too low, dislocation such as slip is induced at the time when the first heat treatment is applied. Therefore, at least 1.0 × 10 ¹⁷ atoms / cm ³ or more is required. . However, if the concentration of dissolved oxygen is too high, the possibility of BMD generation increases, so that it is preferably 8.0 × 10 ¹⁷ atoms / cm ³ or less.

In the silicon wafer of the present invention, the first region exists at a depth of 0.2 μm or more and 2.0 μm or less from the main surface, and the maximum value is 7.0 × 10 ¹⁷ atoms / cm ³ or more and 1.8. X10 ¹⁸ atoms / cm ³ or less, preferably 1.0 μm or more and 2.0 μm or less, 1.0 × 10 ¹⁸ atoms / cm ³ or more and 1.8 × 10 ¹⁸ atoms / cm ³ or less Is more preferable.

The solid solution oxygen having a maximum value within 2 μm from the wafer surface toward the central portion in the thickness direction is attracted to and fixed by the stress field of the dislocation generated on the wafer surface in the device manufacturing process, and the dislocation is easily pinned. be able to. The effect of this solid solution oxygen becomes particularly prominent when the concentration of solid solution oxygen on the wafer surface is less than 1 × 10 ¹⁷ atoms / cm ^{3 as} in the case of an annealed wafer or an epitaxial wafer. In addition, since the concentration of dissolved oxygen is reduced on the wafer surface on which the semiconductor element having a fine structure is manufactured, the occurrence of BMD on the wafer surface that causes deterioration of the characteristics of the semiconductor element is effectively suppressed in the heat treatment process of device manufacturing. .

  In the first region, when the lower limit is 0.2 μm or more, even when the trench type element isolation with the shallowest depth of the semiconductor device is close to 0.2 μm, BMD deposition in the device active region can be easily avoided. It becomes like this. In addition, the upper limit is set to 2.0 μm or less because when the solid solution oxygen at the maximum value is attracted to the stress field of dislocations generated on the wafer surface, if the distance is too far from the surface, the rate of attraction is reduced. This is because the pinning effect is lowered, which is not preferable.

The maximum value of the dissolved oxygen concentration in the first region is preferably in the range of 7.0 × 10 ¹⁷ atoms / cm ^{3 to} 1.8 × 10 ¹⁸ atoms / cm ^{3, and} more preferably 1.0 × 10 10. ^{A range of 18} atoms / cm ³ or more and 1.8 × 10 ¹⁸ atoms / cm ³ or less is more preferable. Within this range, the concentration difference between the solute oxygen concentration on the main surface of the wafer and the maximum concentration can be easily and stably controlled. Then, the dissolved oxygen is attracted and fixed to the stress field of the dislocation generated on the wafer surface in the device manufacturing process, and the dislocation can be easily pinned. In the present embodiment, based on the knowledge of device circuit design in addition to the examples, the concentration difference is estimated to be at least 6.0 × 10 ¹⁷ atoms / cm ³ or more, and the lower limit of the maximum value is The minimum value of the main surface is 1.0 × 10 ¹⁷ atoms / cm ³ or more + 6.0 × 10 ¹⁷ atoms / cm ^3, which is 7.0 × 10 ¹⁷ atoms / cm ³ or more.

However, when the maximum value of dissolved oxygen exceeds 1.8 × 10 ¹⁸ atoms / cm ³ , oxygen precipitation is likely to occur on the surface layer of the silicon wafer in the device manufacturing process, and the size is as small as about 20 nm. The possibility of occurrence of BMD increases, which is not preferable.

In the silicon wafer of the present invention, the minimum value of the second region is preferably present at a depth of 2.4 μm or more and 12 μm or less from the main surface, and further present at a depth of 5.0 μm or more and 10 μm or less. Is more preferable. The minimum value of the dissolved oxygen concentration is preferably 7.0 × 10 ¹⁷ atoms / cm ³ or more and 1/5 or less of the maximum value.

  If the depth from the main surface of the minimum value in the second region is shallow, the oxygen concentration gradient becomes too steep, and if it is too deep, the oxygen concentration gradient becomes too gentle this time. The balance of the amount of oxygen flowing from the first region may be lost, which is not preferable.

Further, in the second region, the minimum value of the solid solution oxygen concentration is preferably 7.0 × 10 ¹⁶ atoms / cm ³ or more. If the minimum value of the oxygen concentration is too low, the oxygen concentration easily occurs in the heat treatment process of device manufacturing. This is because of the outward diffusion and dislocation fixing effect cannot be expected. The lower limit of 7.0 × 10 ¹⁷ atoms / cm ³ is determined in consideration of the range of the dissolved oxygen concentration of the silicon wafer actually used. However, when the minimum value of the dissolved oxygen exceeds 1/5 of the maximum value, it is expected that minute BMD is likely to be generated.

  As shown in FIG. 2, the method for producing a silicon wafer of the present invention includes a step of performing a heat treatment on a silicon wafer at a temperature of 1100 ° C. to 1300 ° C. for 5 minutes to 120 minutes in a non-oxidizing gas atmosphere. And a step of raising the temperature at a rate of temperature rise of 10 ° C./sec to 100 ° C./sec in an oxygen-containing gas atmosphere, and a step of holding at a temperature of 1150 ° C. to 1350 ° C. after the temperature rise for 5 sec to 60 sec And a step of lowering the temperature at a temperature lowering rate of 1 ° C./sec or more and 100 ° C./sec or less after the holding is completed.

  In the temperature process in the first half of FIG. 2, a silicon wafer manufactured from a silicon single crystal ingot pulled and grown by the CZ method is used at a temperature of 1100 ° C. to 1300 ° C. for 5 minutes to 120 minutes in a non-oxidizing gas atmosphere. The following heat treatment is performed, which is generally called an annealing process, and the manufactured wafer is often called an annealed wafer. In the annealing process, a batch type horizontal or vertical furnace is used, and as the atmospheric gas, a reducing gas, a rare gas, or a mixed gas of a reducing gas and a rare gas is used.

  The temperature and time maintained here are preferably from 1100 ° C. to 1300 ° C. and preferably from 5 minutes to 120 minutes, and more preferably from 1150 ° C. to 1200 ° C. for from 40 minutes to 60 minutes. The formation of the DZ layer is determined by the holding temperature and time. However, since the progress of BMD annihilation in the bulk is slow at low temperatures, a long holding time is required to extinguish the BMD. However, when the temperature is raised, the holding time can be shortened, but dislocations such as slips are generated during the heat treatment of the wafer, and the problem of thermal durability of the apparatus for increasing metal contamination occurs. With the above heat treatment temperature and time, the annealed wafer production is stable and highly practical.

The rate of temperature rise is from 0.5 ° C./min (min) to 15 ° C./min from the temperature rise start temperature to the holding temperature. The temperature lowering rate is 0.5 ° C./min to 10 ° C./min from the holding temperature to the temperature lowering completion temperature. If the temperature is raised or lowered too rapidly, dislocations may be generated due to the effect of thermal shock. However, if the temperature is too slow, productivity is remarkably lowered, which is not preferable. The reducing gas is generally H ₂ but may be a hydrogen compound gas such as NH ₃ gas or N ₂ H ₂ gas, and the rare gas may be helium, neon, or krypton gas in addition to argon.

Next, in the temperature process in the latter half of FIG. 2, the annealing wafer is subjected to a rapid heating / cooling heat treatment in an oxygen-containing gas atmosphere. It is put into a heat treatment furnace capable of rapid heating / cooling, and in the heat treatment furnace, for example, oxygen gas, oxygen diluted gas obtained by diluting oxygen gas with an inert gas such as rare gas or nitrogen gas, H ₂ O gas, NO _2. An oxygen-containing gas atmosphere such as NO is performed, for example, rapid heating / cooling heat treatment between room temperature and a predetermined heat treatment temperature is performed. Here, the inside of the heat treatment furnace may be in a reduced pressure state or a pressurized state of the oxygen-containing gas. As the heat treatment furnace, a rapid heating / cooling apparatus of a lamp heating system or a heater heating system such as an RTA apparatus is preferably used. In the present embodiment, for example, an epitaxial wafer other than the annealed wafer may be applied to the step of performing the rapid heating / cooling heat treatment.

  Here, the rate of temperature increase to the heat treatment temperature is preferably in the range of 10 ° C./sec to 100 ° C./sec. The heat treatment temperature is preferably 1150 ° C. or higher and 1350 ° C. or lower, and more preferably 1250 ° C. or higher and 1350 ° C. or lower. The reason for this will be described in the examples described later. Further, the holding time of the wafer at the heat treatment temperature is preferably in the range of 5 sec to 60 sec. The rate of temperature decrease from this heat treatment temperature to between room temperature and 900 ° C. is preferably in the range of 1 ° C./sec to 100 ° C./sec, and more preferably in the range of 50 ° C./sec to 100 ° C./sec.

In rapid lifting thermal process of the present embodiment, the heat treatment temperature T ₁ and its holding time t isothermal shown in FIG. 3 is set appropriately. Furthermore, the rapid heating rate and rapid cooling rate of between the heat treatment temperatures T ₁ to a predetermined temperature T ₀ is set. The concentration and distribution of the dissolved oxygen can be freely controlled by adjusting the heat treatment temperature T ₁ , the holding time t, and the temperature raising / lowering rate. Here, the heat treatment temperature T ₁ is set to a temperature in the range of 1150 ° C. or higher and 1350 ° C. or lower. The temperature T ₀ may be set to a temperature in the range of 400 ° C. to 600 ° C. for an annealed wafer, for example, and to a temperature in the range of 700 ° C. to 900 ° C. for a silicon epitaxial wafer. In this case, it is preferable that an annealing heat treatment furnace or silicon epitaxial growth apparatus and the heat treatment furnace capable of rapid heating / cooling constitute a so-called cluster tool structure system. Processing time compared with the rapid heating and cooling between the heat treatment temperatures T ₁ and room temperature is because significantly reduced the productivity is improved.

  In the rapid heating / cooling heat treatment, since the wafer is exposed to the oxidizing gas, its surface is slightly oxidized. For this reason, there is an advantage that the injection of lattice vacancies into the wafer surface layer portion and the freezing thereof are prevented during rapid cooling.

  The temperature rising rate is adjusted in the range of 10 ° C./sec or more and 100 ° C./sec or less. Here, if the rate of temperature increase is less than 10 ° C./sec, the processing time of the rapid heating / cooling heat treatment becomes long, which is not practical. On the other hand, when the temperature exceeds 100 ° C./sec, slipping of the wafer is likely to occur, so that special equipment for reducing the temperature difference in the wafer is required, resulting in an increase in manufacturing cost.

  The holding time t is adjusted in the range of 5 sec to 60 sec. Here, if the holding time t is less than 5 sec, it is difficult to obtain a stable reproducibility of the concentration and distribution of dissolved oxygen in the surface layer portion of the wafer, and if it exceeds 60 sec, the rapid heating / cooling heat treatment process becomes long, It is not preferable in terms of throughput.

The temperature lowering rate is adjusted in the range of 1 ° C./sec to 100 ° C./sec. This is because if the rate of temperature decrease is less than 1 ° C./sec, the solid solution oxygen diffuses outward from the wafer surface when the temperature falls to a predetermined temperature T _0, and the maximum value of the solid solution oxygen is difficult to obtain. Moreover, the time of the temperature-falling process becomes long and is not practical. On the other hand, when the temperature lowering rate exceeds 100 ° C./sec, the wafer slip easily occurs. Therefore, if it is this range, the solid solution oxygen concentration on the wafer surface will be reduced moderately, and BMD generation on the wafer surface in the heat treatment for device production can be effectively suppressed.

Here, in accordance with the higher the heat treatment temperature T _1, The depth position from the maximum value to become the wafer surface of the solid solution oxygen concentration indicated by the solid line (a) in FIG. 1 as the holding time t becomes longer increases. At the same time, the maximum value increases. When the temperature raising / lowering speed increases, the distribution of dissolved oxygen on the wafer surface portion becomes steeper. Conversely, as the temperature raising / lowering speed decreases, the distribution of dissolved oxygen on the wafer surface portion becomes gentler. In this way, the concentration of dissolved oxygen introduced to the wafer surface is freely controlled in the range of 1 × 10 ¹⁷ atoms / cm ^{3 to} 8.0 × 10 ¹⁷ atoms / cm ³ .

The predetermined temperature T ₀ may be room temperature. Further, the temperature increase rate and the temperature decrease rate may be the same or different. The atmosphere gas at the time of temperature rise may be an oxygen-containing gas or an inert gas.

  In this embodiment, dislocations are generated and propagated in the surface portion of a silicon wafer, which is a device active region, even in a semiconductor device that is highly stressed by microstructuring or a device manufacturing process in which a thermal process is reduced in temperature and time is shortened. And its propagation can be suppressed easily and stably. In addition, the wafer surface layer portion which becomes the device active region is controlled so as to reduce grow-in defects such as COP and BMD, and has high-quality crystallinity. For this reason, even if the device design standard is a semiconductor device with higher integration, higher performance, or higher functionality with a size of 32 nm or less, it is possible to eliminate the risk of a decrease in manufacturing yield.

  In addition, a desired silicon wafer can be easily manufactured by subjecting an annealed wafer or epitaxial wafer to a rapid heating / cooling heat treatment in an oxygen-containing gas atmosphere. For this reason, a silicon wafer having high stress resistance in the surface layer portion of the wafer and high crystallinity can be manufactured at low cost.

Next, the effects of the present invention will be specifically described with reference to examples. As a silicon wafer, a wafer having a 300 mm diameter mirror-polished main surface manufactured from a silicon single crystal ingot pulled and grown in the <100> direction by the CZ method (in this example, Polished Wafer: hereinafter referred to as “PW”) was used. . Here, the initial solid solution oxygen concentration [Oi] in the wafer is 1.2 × 10 ¹⁸ atoms / cm ^3, which is obtained from the conversion coefficient according to Old ASTM. The target silicon wafer is not limited to the diameter, resistivity, and conductivity type, and may be a wafer having an SOI (Silicon on Insulator) structure. Then, a wafer (in this example, an Ar Treatment wafer: hereinafter referred to as “AT wafer”) was prepared by subjecting this PW to heat treatment at 1200 ° C. for 60 minutes in a 100% argon atmosphere. Then, this AT wafer is subjected to rapid heating / cooling heat treatment under various conditions of the heat treatment process described with reference to FIG. 3 in a 100% oxygen gas atmosphere using a single wafer type RTA apparatus, and solute oxygen on the surface thereof Was introduced. Various wafers were prepared as comparative examples.

For these silicon wafers, the oxygen concentration by SIMS and its distribution were measured and shown in FIG. The measurement of SIMS was performed using IMS-6f manufactured by CAMECA, and the measurement conditions were a primary ion species Cs ⁺ and an acceleration energy of 14.5 keV. The silicon oxide film formed on the wafer surface has been removed. In addition, the measurement of the COP density on the wafer surface and the measurement of the dislocation extension using the nanoindentation method were performed, and the results were summarized in Table 1 to evaluate the wafer quality. Here, the COP density was measured by detecting a light scatterer (Light Point Defect: hereinafter referred to as “LPD”) on the wafer surface using a laser scattering surface inspection apparatus.

  In the measurement of dislocation extension, M.M. Akatsuka et al. Appl. Phys. Vol. 40, pp. A method similar to that shown in 1240 (2001) was used. In the formation of the Vickers indentation on the wafer surface, a load of 25 g was applied to the quadrangular pyramid indenter for 10 seconds, and then a heat treatment was performed at 900 ° C. for 30 minutes in a nitrogen gas atmosphere to generate punch-out dislocations and extend. And after giving seco etch, the Rosette size was measured with the optical microscope.

FIG. 5 is an explanatory view schematically showing the extension of punch-out dislocations in the (100) plane of the silicon wafer. Here, each loop-shaped punch-out dislocation is cut and appears on the wafer surface as a pair of etch pits. This punch-out dislocation 11 spreads in all directions in the heat treatment in order to release the residual stress introduced by the Vickers indentation. Therefore, L = (R ₁ + R ₂ ) / 2−S was calculated as Rosette size L, and the pinning ability of dislocations in the silicon wafer was evaluated. Here, R ₁ is the <011> direction of the punch-out dislocation after the heat treatment and the opposite direction, R ₂ is the direction of the orthogonal direction, and S is the diameter of the indentation 12 after the heat treatment.

(Example 1 to Example 3)
In Example 1, in the heat treatment process described with reference to FIG. 3, the rate of temperature increase from room temperature to the heat treatment temperature T _{1 of} 1250 ° C. is 50 ° C./sec, the holding time t = 60 sec, and the subsequent temperature decrease rate is 25 ° C./sec. It cooled to room temperature as sec. Similarly, in Example 2, the temperature raising / lowering conditions were the same as in Example 1, the heat treatment temperature T ₁ = 1300 ° C., and the holding time t = 30 sec. In Example 3, the temperature raising / lowering conditions were the same as in Example 1, and the heat treatment temperature T ₁ = 1350 ° C. and the holding time t = 15 sec.

(Comparative Examples 1 to 4)
Comparative Example 1 is PW, and Comparative Example 2 is obtained by subjecting PW to the rapid heating and cooling heat treatment similar to that described in Example 1. However, the holding time t = 30 sec. Comparative Example 3 is an AT wafer, and Comparative Example 4 is an AT wafer subjected to RTA treatment at 1250 ° C. for 60 seconds in a 100% Ar gas atmosphere. The wafer types shown in Table 1 are AT wafer + RTA in Ar. Indicated. Here, the comparative example 2 is rapid heating / cooling heat treatment similar to the case of the technique described in Patent Document 4.

As shown in FIG. 4, in the thickness direction distribution of the dissolved oxygen concentration in the surface layer portion of the silicon wafer of Example 1, the concentration having a maximum value of 1 × 10 ¹⁸ atoms / cm ^{3 at} a depth of 1 μm from the wafer surface. Distribution. Then, the dissolved oxygen concentration decreases toward the central portion in the thickness direction, and shows a minimum value in a depth region of about 7 μm from the wafer surface. The minimum value is about 2 × 10 ¹⁷ atoms / cm ³ , and the oxygen concentration monotonously increases toward the central portion in the thickness direction, and about 1 × 10 ¹⁸ atoms / cm ³ at a depth of 20 μm of the wafer surface. Become.

As shown in FIG. 4, in the case of Example 2, the concentration distribution has a maximum value of 1.3 × 10 ¹⁸ atoms / cm ³ at a depth of 1.2 μm from the wafer surface. The solid solution oxygen concentration gradually decreases toward the central portion in the thickness direction, and the solid solution oxygen concentration exhibits a minimum value at a depth of about 8.5 μm from the wafer surface. This minimum value is slightly less than 3 × 10 ¹⁷ atoms / cm ³ , and the concentration of dissolved oxygen gradually increases toward the center in the thickness direction, and 1 × 10 ¹⁸ atoms / cm at a depth of 20 μm from the wafer surface. It becomes about ³ .

As shown in FIG. 4, in the case of Example 3, the solid solution oxygen concentration distribution has a maximum value of 1.5 × 10 ¹⁸ atoms / cm ³ at a depth of 1.5 μm from the wafer surface. The solid solution oxygen concentration gradually decreases toward the central portion in the thickness direction, and the solid solution oxygen concentration shows a minimum value in a depth region of about 9 μm from the wafer surface. This minimum value is about 3 × 10 ¹⁷ atoms / cm ³ , and the solid solution oxygen concentration gradually increases toward the center in the thickness direction, and 1 × 10 ¹⁸ atoms / cm at a depth of 20 μm from the wafer surface. It becomes about ³ .

On the other hand, in the case of the PW of Comparative Example 1, the solid solution oxygen concentration is approximately constant 1.2 × 10 ¹⁸ atoms / cm ³ from the wafer surface to the central portion in the thickness direction. In the case of Comparative Example 2, the dissolved oxygen concentration has a distribution having a maximum value of the dissolved oxygen concentration in a certain range from the wafer surface toward the thickness direction. The solid solution oxygen concentration in the case of the AT wafer of Comparative Example 3 is 1 × 10 ¹⁶ atoms / cm ³ near the wafer surface, and is almost the same as that in Example 1 from a depth of about 7 μm from the wafer surface. It increases monotonously with the concentration and reaches about 1 × 10 ¹⁸ atoms / cm ³ at a depth of 20 μm. Although the solid solution oxygen concentration distribution in the case of Comparative Example 4 is not shown in the drawing, the concentration profile is the same as that in Comparative Example 3, and the solid solution oxygen concentration is slightly reduced at the wafer surface layer than in Comparative Example 3. ing.

In FIG. 4, spike-like peaks appear deeper than 10 μm from the wafer surface. These peaks indicate the presence of oxygen precipitates. However, the thickness of the DZ layer on the AT wafer was all about 10 μm, and the amount of BMD in the DZ layer was both below the detection limit of the infrared scattering tomograph (10 ⁷ pieces / cm ³ ). Moreover, the BMD amount in the bulk part was about 5 × 10 ⁸ pieces / cm ³ in each of Examples 1 to 3 and Comparative Examples 3 and 4.

  As shown in Table 1, the COP density and dislocation extension on the wafer surface for the evaluation of the quality of the wafer are shown as relative values based on the PW of Comparative Example 1. The COP density is the number of LPDs per unit area obtained by dividing the total number of detected LPDs of 0.065 μm or more in the wafer surface by the wafer area. The dislocation extension is an average value of Rosette size L obtained by performing dislocation extension using the indentation method 10 times.

  As can be seen from Table 1, the COP which is a grown-in defect is not different between the case of Examples 1 to 3 and the case of Comparative Example 3 and Comparative Example 4, and the aggregate of lattice vacancies by the rapid heating and cooling heat treatment of the AT wafer. It has been confirmed that the defects of the same will not change. On the other hand, in the case of Comparative Example 1 and Comparative Example 2, many COPs exist. Further, as can be seen from Table 1, in the case of Examples 1 to 3, the dislocation elongation is greatly reduced from the comparison with Comparative Examples 3 and 4 as compared with the case of the AT wafer, and slightly less than in the case of Comparative Example 2. However, it was found that the dislocation extension becomes small. As described above, it has been clarified that the pinning ability of dislocation is improved by subjecting the AT wafer to the rapid heating and cooling heat treatment and having the distribution of the dissolved oxygen concentration of the present invention.

Although high stress resistance and high-quality crystallinity in the wafer surface layer portion shown in Examples 1 to 3 are not shown, the heat treatment temperature T ₁ = 1150 ° C. and 1200 ° C. of the rapid heating / cooling heat treatment of the AT wafer is not shown. Has been confirmed to be obtained as well.

  From the above, in the silicon wafer described in this embodiment, it was confirmed that moderate solid solution oxygen was simply and effectively introduced into the surface layer portion of the annealed wafer, and the concentration distribution was adjusted and controlled. . And, using this silicon wafer introduced with solid solution oxygen, the pinning ability of dislocations formed on the surface layer part by solid solution oxygen was measured, and it was confirmed that the surface part that becomes the device active region shows high stress resistance. It was. Moreover, in the silicon wafer into which the above-mentioned solid solution oxygen was introduced, it was confirmed that the wafer surface portion has a very low COP density and high quality by suppressing the generation of new BMD.

It is a graph with which it uses for description of the solid solution oxygen concentration of the silicon wafer concerning embodiment of this invention. It is a figure which shows an example of the temperature process for annealing wafer manufacture of embodiment of this invention, and oxygen introduction | transduction to the surface part. It is explanatory drawing which shows an example of the heat processing in the oxygen introduction | transduction to the silicon wafer surface part of embodiment of this invention. It is a graph which shows the thickness direction distribution of the oxygen concentration of the silicon wafer in the Example of this invention. It is explanatory drawing which shows typically expansion | extension of the punch-out dislocation in the silicon wafer which gave the impression of the Example of this invention.

Explanation of symbols

11 Punch-out dislocation 12 Indentation

Claims (4)

A silicon wafer having two main surfaces facing each other and having a solid solution oxygen concentration continuously changing in a thickness direction of the silicon wafer, wherein the solid solution oxygen concentration is increased from a value on at least one of the main surfaces. And a second region that decreases from the maximum value of the first region, and increases from the minimum value of the second region to the value of the thickness center portion in the thickness direction. Change,
The first region exists at a depth of 1.0 μm or more and 2.0 μm or less from the main surface, and the maximum value is 1.0 × 10 ¹⁸ atoms / cm ³ or more and 1.8 × 10 ¹⁸ atoms / cm. A silicon wafer characterized by being ³ or less.   The maximum value of the dissolved oxygen concentration in the first region is the largest value in the thickness direction, and the minimum value in the second region is the smallest value in the thickness direction. 2. The silicon wafer according to 1. ^3. The silicon according to claim 1, wherein a value of a solid solution oxygen concentration on the main surface is 1.0 × 10 ¹⁷ atoms / cm ³ or more and 8.0 × 10 ¹⁷ atoms / cm ³ or less. Wafer. The second region exists at a depth of 12 μm or less from the main surface, and the minimum value is 1.0 × 10 ¹⁷ atoms / cm ³ or more and 1/5 or less of the maximum value. The silicon wafer as described in any one of Claim 1 to 3.

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