JP6907931B2 - 半導体モジュール - Google Patents
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- JP6907931B2 JP6907931B2 JP2017250549A JP2017250549A JP6907931B2 JP 6907931 B2 JP6907931 B2 JP 6907931B2 JP 2017250549 A JP2017250549 A JP 2017250549A JP 2017250549 A JP2017250549 A JP 2017250549A JP 6907931 B2 JP6907931 B2 JP 6907931B2
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- 239000004065 semiconductor Substances 0.000 title claims description 70
- 239000000758 substrate Substances 0.000 claims description 26
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 description 13
- 239000013256 coordination polymer Substances 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000009429 electrical wiring Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003985 ceramic capacitor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
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Description
[実施形態の説明]
最初に、本開示の技術の実施形態の内容を列記して説明する。
上記板状部材は、上記板状部材を貫通する貫通孔を有し、上記サージ電圧吸収素子は、上記貫通孔内に配置されていてもよい。これにより、サージ電圧吸収素子と板状部材との干渉を防止できる。
[実施形態の詳細]
本開示の技術の実施形態の具体例を、以下に図面を参照しつつ説明する。本発明はこれらの例示に限定されるものではなく、請求の範囲によって示され、請求の範囲内と均等の範囲内とでのすべての変更が含まれることが意図される。図面の説明においては同一要素には同一符号を付し、重複する説明を省略する。
Claims (7)
- 絶縁基板と、前記絶縁基板の表面上に形成された第1入力用配線パターン、第2入力用配線パターン、第1制御用配線パターン及び第2制御用配線パターンとを有する回路基板と、
第1主電極パッド、第2主電極パッド及び第1ゲート電極パッドを有する第1縦型トランジスタであって、前記第2主電極パッド及び前記第1ゲート電極パッドは前記第1主電極パッドと反対側に形成されており、前記第1主電極パッドが前記第1入力用配線パターンと対向し且つ前記第1入力用配線パターンに電気的に接続された状態で前記回路基板に搭載され、前記第1ゲート電極パッドは前記第1制御用配線パターンに電気的に接続される前記第1縦型トランジスタと、
第3主電極パッド、第4主電極パッド及び第2ゲート電極パッドを有する第2縦型トランジスタであって、前記第4主電極パッド及び前記第2ゲート電極パッドは前記第3主電極パッドと反対側に形成されており、前記第4主電極パッドが前記第2入力用配線パターンと対向し且つ前記第2入力用配線パターンに電気的に接続されるとともに、前記第2ゲート電極パッドが前記第2制御用配線パターンと対向し且つ前記第2制御用配線パターンに電気的に接続された状態で前記回路基板に搭載される前記第2縦型トランジスタと、
前記第1縦型トランジスタ及び前記第2縦型トランジスタ上に配置されており、裏面側導電領域を有する板状部材と、
前記第1入力用配線パターンと前記第2入力用配線パターンとの間を接続しておりサージ電圧を吸収するサージ電圧吸収素子と、を備え、
前記第2主電極パッドと前記第3主電極パッドとは、前記板状部材の前記裏面側導電領域によって互いに電気的に接続され、
前記板状部材に、前記第1入力用配線パターンの一部と前記第2入力用配線パターンの一部とが露出する貫通孔が形成されており、
前記サージ電圧吸収素子は、前記貫通孔内に配置されている、半導体モジュール。 - 前記第1入力用配線パターンにおける前記第1縦型トランジスタが搭載される第1トランジスタ搭載領域と、前記第2入力用配線パターンにおける前記第2縦型トランジスタが搭載される第2トランジスタ搭載領域とは対向配置されており、
前記第1トランジスタ搭載領域と前記第2トランジスタ搭載領域の互いに対向する対向縁部は平行であり、
前記サージ電圧吸収素子は、前記第1トランジスタ搭載領域と前記第2トランジスタ搭載領域それぞれの前記対向縁部の間を接続している、請求項1に記載の半導体モジュール。 - 絶縁基板と、前記絶縁基板の表面上に形成された第1入力用配線パターン、第2入力用配線パターン、第1制御用配線パターン及び第2制御用配線パターンとを有する回路基板と、
第1主電極パッド、第2主電極パッド及び第1ゲート電極パッドを有する第1縦型トランジスタであって、前記第2主電極パッド及び前記第1ゲート電極パッドは前記第1主電極パッドと反対側に形成されており、前記第1主電極パッドが前記第1入力用配線パターンと対向し且つ前記第1入力用配線パターンに電気的に接続された状態で前記回路基板に搭載され、前記第1ゲート電極パッドは前記第1制御用配線パターンに電気的に接続される前記第1縦型トランジスタと、
第3主電極パッド、第4主電極パッド及び第2ゲート電極パッドを有する第2縦型トランジスタであって、前記第4主電極パッド及び前記第2ゲート電極パッドは前記第3主電極パッドと反対側に形成されており、前記第4主電極パッドが前記第2入力用配線パターンと対向し且つ前記第2入力用配線パターンに電気的に接続されるとともに、前記第2ゲート電極パッドが前記第2制御用配線パターンと対向し且つ前記第2制御用配線パターンに電気的に接続された状態で前記回路基板に搭載される前記第2縦型トランジスタと、
前記第1縦型トランジスタ及び前記第2縦型トランジスタ上に配置されており、裏面側導電領域を有する板状部材と、を備え、
前記第2主電極パッドと前記第3主電極パッドとは、前記板状部材の前記裏面側導電領域によって互いに電気的に接続され、
前記板状部材は、切欠き部を有し、
前記板状部材は、前記切欠き部から前記第1ゲート電極パッドを露出するように、前記第1縦型トランジスタ上に配置されている、半導体モジュール。 - 前記第1入力用配線パターンと前記第2入力用配線パターンとの間を接続しておりサージ電圧を吸収するサージ電圧吸収素子を備える、請求項3に記載の半導体モジュール。
- 前記板状部材は、前記板状部材を貫通する貫通孔を有し、
前記サージ電圧吸収素子は、前記貫通孔内に配置されている、請求項4に記載の半導体モジュール。 - 前記第1入力用配線パターンにおける前記第1縦型トランジスタが搭載される第1トランジスタ搭載領域と、前記第2入力用配線パターンにおける前記第2縦型トランジスタが搭載される第2トランジスタ搭載領域とは対向配置されており、
前記第1トランジスタ搭載領域と前記第2トランジスタ搭載領域の互いに対向する対向縁部は平行であり、
前記サージ電圧吸収素子は、前記第1トランジスタ搭載領域と前記第2トランジスタ搭載領域それぞれの前記対向縁部の間を接続している、請求項1、請求項4または請求項5に記載の半導体モジュール。 - 前記回路基板は、前記絶縁基板上に出力用配線パターンを有し、
前記出力用配線パターンは、前記板状部材の前記裏面側導電領域と電気的に接続されている、請求項1から請求項6のいずれか1項に記載の半導体モジュール。
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