JP6886557B2 - 改善された金属コンタクトランディング構造 - Google Patents
改善された金属コンタクトランディング構造 Download PDFInfo
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- JP6886557B2 JP6886557B2 JP2020505328A JP2020505328A JP6886557B2 JP 6886557 B2 JP6886557 B2 JP 6886557B2 JP 2020505328 A JP2020505328 A JP 2020505328A JP 2020505328 A JP2020505328 A JP 2020505328A JP 6886557 B2 JP6886557 B2 JP 6886557B2
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- nitride
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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Description
Claims (15)
- 半導体構造を形成する方法であって、
処理チャンバの遠隔プラズマ領域でフッ素含有前駆体のプラズマを形成すること;
半導体基板を前記プラズマの放出物と接触させることであって、前記半導体基板が前記処理チャンバの処理領域に収容される、接触させること;
露出した窒化物材料を前記プラズマの放出物で選択的に洗浄すること;及び
その後、前記洗浄した窒化物材料上にキャップ材料を堆積させることであって、該キャップ材料が誘電体材料の露出領域に対して前記窒化物材料上に選択的に堆積される、堆積させること
を含む、半導体構造を形成する方法。 - エッチングが第1の処理チャンバ内で行われ、堆積が第2の処理チャンバ内で行われる、請求項1に記載の半導体構造を形成する方法。
- 前記第1の処理チャンバから前記第2の処理チャンバへ前記半導体基板を移送することをさらに含み、前記移送が真空破壊することなく行われる、請求項2に記載の半導体構造を形成する方法。
- 前記窒化物材料及び前記キャップ材料を選択的にエッチングして間隙を形成することをさらに含む、請求項1に記載の半導体構造を形成する方法。
- 前記エッチングが湿式エッチング又はプラズマ強化エッチングを含む、請求項4に記載の半導体構造を形成する方法。
- 前記間隙内に金属材料を形成することをさらに含み、前記金属材料が窒化チタン又はタングステンを含む、請求項4に記載の半導体構造を形成する方法。
- 前記キャップ材料が窒化ケイ素を含む、請求項1に記載の半導体構造を形成する方法。
- 前記誘電体材料が酸化ケイ素を含む、請求項1に記載の半導体構造を形成する方法。
- 前記堆積が、約2:1以上の前記窒化物材料の前記誘電体材料に対する選択性で行われる、請求項1に記載の半導体構造を形成する方法。
- 前記キャップ材料を選択的に堆積させることが、前記誘電体材料上の前記キャップ材料の成長を抑制することを含む、請求項1に記載の半導体構造を形成する方法。
- 前記基板が、窒化物材料と誘電体材料の交互の層を含み、前記キャップ材料が、別々のキャップ材料構成間の間隔を維持するように形成される、請求項1に記載の半導体構造を形成する方法。
- 半導体構造を形成する方法であって、
処理チャンバの遠隔プラズマ領域でフッ素含有前駆体のプラズマを形成すること;
半導体基板を前記プラズマの放出物と接触させることであって、前記半導体基板が前記処理チャンバの処理領域に収容される、接触させること;
前記半導体基板上の誘電体材料の露出領域に近接して配置された窒化物材料の露出領域を選択的に洗浄すること;及び
その後、前記窒化物材料上にキャップ材料を形成することであって、該キャップ材料が、前記誘電体材料の露出領域に対して前記窒化物材料の上に選択的に形成される、形成すること
を含む、方法。 - 前記基板が、前記窒化物材料の第1の露出領域と、前記誘電体材料の露出領域によって垂直方向に分離された前記窒化物材料の第2の露出領域とを含み、前記誘電体材料が酸化ケイ素を含み、かつ前記キャップ材料が窒化ケイ素を含む、請求項12に記載の半導体構造を形成する方法。
- 前記窒化物材料の各露出領域が、露出した上面と、前記上面に対して垂直な露出した側壁とを含み、前記キャップ材料が、第1の窒化物材料及び第2の窒化物材料の前記露出した上面及び前記露出した側壁の上に形成され、前記第1の窒化物材料の上に形成されたキャップ材料が、形成後に前記第2の窒化物材料の上に形成された前記キャップ材料と接触していない、請求項13に記載の半導体構造を形成する方法。
- 第1の窒化物材料、第2の窒化物材料、及びキャップ材料を前記半導体基板から除去することをさらに含む、請求項12に記載の半導体構造を形成する方法。
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