JP6872132B2 - 半導体記憶素子、半導体装置、電子機器、および半導体記憶素子の製造方法 - Google Patents
半導体記憶素子、半導体装置、電子機器、および半導体記憶素子の製造方法 Download PDFInfo
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- JP6872132B2 JP6872132B2 JP2018504043A JP2018504043A JP6872132B2 JP 6872132 B2 JP6872132 B2 JP 6872132B2 JP 2018504043 A JP2018504043 A JP 2018504043A JP 2018504043 A JP2018504043 A JP 2018504043A JP 6872132 B2 JP6872132 B2 JP 6872132B2
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Description
Access Memory)が用いられるが、近年、コストおよび消費電力の低減のために、Dynamic RAM(DRAM)、Magnetic RAM(MRAM)、またはFerroelectric RAM(FeRAM)を用いることが検討されている。
1.第1の実施形態
1.1.半導体記憶素子の平面構造
1.2.半導体記憶素子の積層構造
1.3.半導体記憶素子の製造方法
1.4.変形例
2.第2の実施形態
2.1.半導体装置の平面構造
2.2.半導体装置の積層構造
2.3.半導体装置の製造方法
3.まとめ
[1.1.半導体記憶素子の平面構造]
まず、図1を参照して、本開示の第1の実施形態に係る半導体記憶素子の平面構造について説明する。図1は、本実施形態に係る半導体記憶素子1の平面構造を示す平面図である。
続いて、図2を参照して、本実施形態に係る半導体記憶素子1の積層構造について説明する。図2は、本実施形態に係る半導体記憶素子1の積層構造を示す断面図である。なお、図2のAで示す断面は、図1のAA線にて切断した断面を示しており、図2のBで示す断面は、図1のBB線にて切断した断面を示している。
次に、図3〜図10を参照して、本実施形態に係る半導体記憶素子1の製造方法について説明する。図3〜図10は、本実施形態に係る半導体記憶素子1の各製造工程を説明する断面図である。
Annealing)を行うことにより、イオン注入した不純物を活性化させる。なお、不純物の意図しない領域への拡散を抑制するために、スパイクRTAにて不純物の活性化を行うことも可能である。
続いて、図11〜図13を参照して、本実施形態の変形例に係る半導体記憶素子の構造および製造方法について説明する。図11は、本変形例に係る半導体記憶素子の積層構造を示す断面図である。なお、図11のAで示す断面は、図1のAA線にて切断した断面を示しており、図11のBで示す断面は、図1のBB線にて切断した断面を示している。
Annealing)を行うことにより、イオン注入した不純物を活性化させる。なお、不純物の意図しない領域への拡散を抑制するために、スパイクRTAにて不純物の活性化を行うことも可能である。
次に、図14を参照して、本開示の第2の実施形態に係る半導体装置の平面構造について説明する。図14は、本実施形態に係る半導体装置100の平面構造を示す平面図である。
続いて、図15を参照して、本実施形態に係る半導体装置100の積層構造について説明する。図15は、本実施形態に係る半導体装置100に設けられる電界効果トランジスタの積層構造を示す断面図である。なお、図15のAで示す断面は、記憶装置10に設けられる電界効果トランジスタを切断した断面を示しており、図15のBで示す断面は、論理回路200等に設けられる電界効果トランジスタ2を切断した断面を示している。
次に、図16〜図21を参照して、本実施形態に係る半導体装置100の製造方法について説明する。図16〜図21は、本実施形態に係る半導体装置100の各製造工程を説明する断面図である。なお、図16〜図21では、図15と同様に、記憶装置10に設けられる電界効果トランジスタ、および論理回路200等に設けられる電界効果トランジスタ2についてのみ示す。
以上にて説明したように、本開示の第1の実施形態に係る半導体記憶素子1は、素子の内部に設けられたコンタクトプラグ52にて第1半導体層42の電位を制御し、ゲート絶縁膜22の残留分極を制御することができる。これによれば、第1の実施形態に係る半導体記憶素子1は、より高速で動作することが可能となる。また、第1の実施形態に係る半導体記憶素子1は、素子ごとに設けられたコンタクトプラグ52にてゲート絶縁膜22の残留分極を制御することができるため、素子ごとの干渉をなくし、独立して動作することが可能となる。
(1)
第1導電型である第1半導体層と、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層と、
前記第1半導体層の上に設けられたゲート電極と、
前記第1半導体層と、前記ゲート電極との間に設けられたゲート絶縁膜と、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域と、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域と、
前記ソース領域および前記第1半導体層の両方と電気的に接続するビット線と、
を備える、半導体記憶素子。
(2)
他の素子との間に設けられ、前記他の素子を電気的に離隔する絶縁性の素子分離層をさらに備える、前記(1)に記載の半導体記憶素子。
(3)
前記素子分離層は、前記第1半導体層よりも深い領域まで設けられ、前記第2半導体層は、前記素子分離層よりも深い領域まで設けられる、前記(2)に記載の半導体記憶素子。
(4)
前記ビット線は、前記素子分離層と、前記第1半導体層との境界に設けられたコンタクトプラグを介して、前記ソース領域および前記第1半導体層の両方と接続する、前記(2)または(3)に記載の半導体記憶素子。
(5)
前記コンタクトプラグは、前記第2半導体層に達しない深さまで設けられる、前記(4)に記載の半導体記憶素子。
(6)
前記ビット線は、前記ソース領域から前記第1半導体層の側面に亘って設けられたコンタクト領域を介して、前記ソース領域および前記第1半導体層の両方と接続する、前記(1)〜(3)のいずれか一項に記載の半導体記憶素子。
(7)
前記ゲート絶縁膜の少なくとも一部は、強誘電体材料である、前記(1)〜(6)のいずれか一項に記載の半導体記憶素子。
(8)
前記ゲート電極、および前記第1半導体層の上に設けられ、圧縮応力または引張応力を与えるライナー層をさらに備える、前記(1)〜(7)のいずれか一項に記載の半導体記憶素子。
(9)
前記圧縮応力または引張応力の大きさは、1GPa以上である、前記(8)に記載の半導体記憶素子。
(10)
第1導電型である第1半導体層、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層、
前記第1半導体層の上に設けられたゲート電極、
前記第1半導体層と、前記ゲート電極との間に設けられたゲート絶縁膜、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域、
前記ソース領域および前記第1半導体層の両方と電気的に接続するビット線、
を備える半導体記憶素子がマトリクス状に配置された記憶装置と、
を含む、半導体装置。
(11)
前記記憶装置と同一の基板の上に設けられた論理回路をさらに含む、前記(10)に記載の半導体装置。
(12)
前記論理回路は、支持基板上に絶縁層および半導体層を順に積層した領域の上に設けられる、前記(11)に記載の半導体装置。
(13)
第1導電型である第1半導体層、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層、
前記第1半導体層の上に設けられたゲート電極、
前記第1半導体層と、前記ゲート電極との間に設けられたゲート絶縁膜、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域、
前記ソース領域および前記第1半導体層の両方と電気的に接続するビット線、
を備える半導体記憶素子がマトリクス状に配置された記憶装置と、
を含む、電子機器。
(14)
第1導電型である第1半導体層、および前記第1半導体層の下に設けられ、第2導電型である第2半導体層を形成する工程と、
前記第1半導体層の上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上にゲート電極を形成する工程と、
前記ゲート電極の一方の側の前記第1半導体層に、第2導電型であるドレイン領域を形成し、前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に、第2導電型であるソース領域を形成する工程と、
前記ソース領域および前記第1半導体層の両方と電気的に接続するビット線を形成する工程と、
を含む、半導体記憶素子の製造方法。
(15)
前記第1半導体層および前記第2半導体層を形成する前に、前記半導体記憶素子を他の素子と電気的に離隔する絶縁性の素子分離層を形成する工程をさらに含む、前記(14)に記載の半導体記憶素子の製造方法。
(16)
前記素子分離層と、前記第1半導体層との境界にコンタクトプラグを形成することで、前記ソース領域および前記第1半導体層の両方と、前記ビット線とを電気的に接続する、前記(15)に記載の半導体記憶素子の製造方法。
(17)
前記素子分離層をエッチングして、前記第1半導体層および前記ソース領域の側面を露出させ、前記ソース領域から前記第1半導体層の側面に亘ってコンタクト領域を形成することで、前記ソース領域および前記第1半導体層の両方と、前記ビット線とを電気的に接続する、前記(15)に記載の半導体記憶素子の製造方法。
(18)
前記第1半導体層および前記第2半導体層を形成する前に、支持基板上に順に積層された絶縁層および半導体層を除去する工程をさらに含む、前記(14)〜(17)のいずれか一項に記載の半導体記憶素子の製造方法。
10 記憶装置
21 ゲート電極
22 ゲート絶縁膜
31 ドレイン領域
32 ソース領域
21S、31S、32S コンタクト領域
31E、32E エクステンション領域
40 半導体基板
41 第2半導体層
42 第1半導体層
43 サイドウォール絶縁膜
44 ライナー層
45 平坦化膜
51、52、56 コンタクトプラグ
53 データ線
54 ビット線
55 ワード線
61 素子分離層
91 埋込絶縁層
92 第3半導体層
100 半導体装置
200 論理回路
Claims (18)
- 第1導電型である第1半導体層と、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層と、
前記第1半導体層の上に設けられたゲート電極と、
前記第1半導体層と、前記ゲート電極との間に設けられ、少なくとも一部が強誘電体材料により形成されるゲート絶縁膜と、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域と、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域と、
前記ソース領域および前記第1半導体層の両方と電気的に接続し、前記第1半導体層と前記ゲート電極との間で前記ゲート絶縁膜に電界を印加し、前記ゲート絶縁膜の分極方向を制御するビット線と、
を備える、半導体記憶素子。 - 他の半導体記憶素子との間に設けられ、前記他の半導体記憶素子を電気的に離隔する絶縁性の素子分離層をさらに備える、請求項1に記載の半導体記憶素子。
- 前記素子分離層は、前記第1半導体層よりも深い領域まで設けられ、前記第2半導体層は、前記素子分離層よりも深い領域まで設けられる、請求項2に記載の半導体記憶素子。
- 前記ビット線は、前記素子分離層と、前記第1半導体層との境界に設けられたコンタクトプラグを介して、前記ソース領域および前記第1半導体層の両方と接続する、請求項2または3に記載の半導体記憶素子。
- 前記コンタクトプラグは、前記第2半導体層に達しない深さまで設けられる、請求項4に記載の半導体記憶素子。
- 前記ビット線は、前記ソース領域から前記第1半導体層の側面に亘って設けられたコンタクト領域を介して、前記ソース領域および前記第1半導体層の両方と接続する、請求項1〜3のいずれか一項に記載の半導体記憶素子。
- 前記ゲート絶縁膜の少なくとも一部は、強誘電体材料である、請求項1〜6のいずれか一項に記載の半導体記憶素子。
- 前記ゲート電極、および前記第1半導体層の上に設けられ、圧縮応力または引張応力を与えるライナー層をさらに備える、請求項1〜7のいずれか一項に記載の半導体記憶素子。
- 前記ゲート電極は、前記ゲート絶縁膜に分極方向が反転しない電圧を印加し、前記第1半導体層にチャネル領域を形成し、前記ドレイン領域から前記ソース領域への電流の流路を形成する、請求項1〜8のいずれか一項に記載の半導体記憶素子。
- 第1導電型である第1半導体層、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層、
前記第1半導体層の上に設けられたゲート電極、
前記第1半導体層と、前記ゲート電極との間に設けられ、少なくとも一部が強誘電体材料により形成されるゲート絶縁膜、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域、
前記ソース領域および前記第1半導体層の両方と電気的に接続し、前記第1半導体層と前記ゲート電極との間で前記ゲート絶縁膜に電界を印加し、前記ゲート絶縁膜の分極方向を制御するビット線、
を備える半導体記憶素子がマトリクス状に配置された記憶装置と、
を含む、半導体装置。 - 前記記憶装置と同一の基板の上に設けられた論理回路をさらに含む、請求項10に記載の半導体装置。
- 前記論理回路は、支持基板上に絶縁層および半導体層を順に積層した領域の上に設けられる、請求項11に記載の半導体装置。
- 第1導電型である第1半導体層、
前記第1半導体層の下に設けられ、第2導電型である第2半導体層、
前記第1半導体層の上に設けられたゲート電極、
前記第1半導体層と、前記ゲート電極との間に設けられ、少なくとも一部が強誘電体材料により形成されるゲート絶縁膜、
前記ゲート電極の一方の側の前記第1半導体層に設けられ、第2導電型であるドレイン領域、
前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に設けられ、第2導電型であるソース領域、
前記ソース領域および前記第1半導体層の両方と電気的に接続し、前記第1半導体層と前記ゲート電極との間で前記ゲート絶縁膜に電界を印加し、前記ゲート絶縁膜の分極方向を制御するビット線、
を備える半導体記憶素子がマトリクス状に配置された記憶装置と、
を含む、電子機器。 - 第1導電型である第1半導体層、および前記第1半導体層の下に設けられ、第2導電型である第2半導体層を形成する工程と、
前記第1半導体層の上に、少なくとも一部が強誘電体材料により形成されるゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の上にゲート電極を形成する工程と、
前記ゲート電極の一方の側の前記第1半導体層に、第2導電型であるドレイン領域を形成し、前記ゲート電極を挟んで前記一方の側と対向する他方の側の前記第1半導体層に、第2導電型であるソース領域を形成する工程と、
前記ソース領域および前記第1半導体層の両方と電気的に接続し、前記第1半導体層と前記ゲート電極との間で前記ゲート絶縁膜に電界を印加し、前記ゲート絶縁膜の分極方向を制御するビット線を形成する工程と、
を含む、半導体記憶素子の製造方法。 - 前記第1半導体層および前記第2半導体層を形成する前に、前記半導体記憶素子を他の半導体記憶素子と電気的に離隔する絶縁性の素子分離層を形成する工程をさらに含む、請求項14に記載の半導体記憶素子の製造方法。
- 前記素子分離層と、前記第1半導体層との境界にコンタクトプラグを形成することで、前記ソース領域および前記第1半導体層の両方と、前記ビット線とを電気的に接続する、請求項15に記載の半導体記憶素子の製造方法。
- 前記素子分離層をエッチングして、前記第1半導体層および前記ソース領域の側面を露出させ、前記ソース領域から前記第1半導体層の側面に亘ってコンタクト領域を形成することで、前記ソース領域および前記第1半導体層の両方と、前記ビット線とを電気的に接続する、請求項15に記載の半導体記憶素子の製造方法。
- 前記第1半導体層および前記第2半導体層を形成する前に、支持基板上に順に積層された絶縁層および半導体層を除去する工程をさらに含む、請求項14〜17のいずれか一項に記載の半導体記憶素子の製造方法。
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