JP6852283B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6852283B2 JP6852283B2 JP2016104276A JP2016104276A JP6852283B2 JP 6852283 B2 JP6852283 B2 JP 6852283B2 JP 2016104276 A JP2016104276 A JP 2016104276A JP 2016104276 A JP2016104276 A JP 2016104276A JP 6852283 B2 JP6852283 B2 JP 6852283B2
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- semiconductor device
- metal oxide
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- oxide film
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- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
Description
最初に、電子供給層にInAlNを用いた半導体装置において、ドレイン電流が低下することについて、図1に基づき説明する。
次に、第1の実施の形態における半導体装置について、図2に基づき説明する。
次に、本実施の形態における半導体装置の製造方法について、図11及び図12に基づき説明する。
(半導体装置)
次に、第2の実施の形態における半導体装置について、図13に基づき説明する。
次に、本実施の形態における半導体装置の製造方法について、図14及び図15に基づき説明する。
(半導体装置)
次に、第3の実施の形態における半導体装置について、図16に基づき説明する。
次に、本実施の形態における半導体装置の製造方法について、図17及び図18に基づき説明する。
(半導体装置)
次に、第4の実施の形態における半導体装置について、図19に基づき説明する。
次に、本実施の形態における半導体装置の製造方法について、図20及び図21に基づき説明する。
次に、第5の実施の形態について説明する。本実施の形態は、半導体デバイス、電源装置及び高周波増幅器である。
(付記1)
基板の上に、窒化物半導体により形成された第1の半導体層と、
前記第1の半導体層の上に、窒化物半導体により形成された第2の半導体層と、
前記第2の半導体層の上に形成されたソース電極及びドレイン電極と、
前記ソース電極と前記ドレイン電極との間において、前記第2の半導体層の上に形成された金属酸化膜と、
前記金属酸化膜の上に形成されたゲート電極と、
を有し、
前記金属酸化膜は、AlOxとInOxとを含むものであって、
前記金属酸化膜におけるAlOx/InOxは、3以上であることを特徴とする半導体装置。
(付記2)
前記金属酸化膜におけるAlOx/InOxは、10以上であることを特徴とする付記1に記載の半導体装置。
(付記3)
前記第2の半導体層は、InAlNまたはInAlGaNを含む材料により形成されていることを特徴とする付記1または2に記載の半導体装置。
(付記4)
基板の上に、窒化物半導体により形成された第1の半導体層と、
前記第1の半導体層の上に、窒化物半導体により形成された第2の半導体層と、
前記第2の半導体層の上に形成されたソース電極及びドレイン電極と、
前記ソース電極と前記ドレイン電極との間において、前記第2の半導体層の上に形成された金属酸化膜と、
前記金属酸化膜の上に形成されたゲート電極と、
を有し、
前記第2の半導体層は、InAlNまたはInAlGaNを含む材料により形成されており、
前記金属酸化膜におけるAlOx/InOxの値は、前記第2の半導体層におけるAl/Inの値よりも大きいことを特徴とする半導体装置。
(付記5)
前記金属酸化膜の膜厚は、1nm以上、3nm以下であることを特徴とする付記1から4のいずれかに記載の半導体装置。
(付記6)
前記金属酸化膜は、前記ゲート電極の直下における膜厚が、前記ゲート電極の直下以外の領域における膜厚よりも厚いことを特徴とする付記1から4のいずれかに記載の半導体装置。
(付記7)
前記第2の半導体層には、前記ゲート電極が形成される領域に、前記第2の半導体層の一部が除去されたゲートリセスが形成されており、
前記ゲートリセスの底面及び側面には、前記金属酸化膜が形成されており、
前記ゲート電極は、前記ゲートリセスに形成されていることを特徴とする付記1から6のいずれかに記載の半導体装置。
(付記8)
前記金属酸化膜の上には、前記ゲート電極が形成されている領域を除き、絶縁膜が形成されていることを特徴とする付記1から7のいずれかに記載の半導体装置。
(付記9)
前記金属酸化膜の上には、絶縁膜が形成されており、
前記ゲート電極は、前記絶縁膜の上に形成されていることを特徴とする付記1から7のいずれかに記載の半導体装置。
(付記10)
前記第1の半導体層は、GaNを含む材料により形成されていることを特徴とする付記1から9のいずれかに記載の半導体装置。
(付記11)
基板の上に、窒化物半導体により第1の半導体層を形成する工程と、
前記第1の半導体層の上に、窒化物半導体により第2の半導体層を形成する工程と、
前記第2の半導体層の上に、ソース電極及びドレイン電極を形成する工程と、
前記ソース電極と前記ドレイン電極との間における前記第2の半導体層の表面を水蒸気により酸化することにより金属酸化膜を形成する工程と、
前記金属酸化膜の上に、ゲート電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
(付記12)
前記金属酸化膜は、前記第2の半導体層の表面を300℃以上、800℃以下の温度の水蒸気により酸化することにより形成するものであることを特徴とする付記11に記載の半導体装置の製造方法。
(付記13)
前記金属酸化膜は、前記第2の半導体層の表面を300℃以上、500℃以下の温度の水蒸気により酸化することにより形成するものであることを特徴とする付記11に記載の半導体装置の製造方法。
(付記14)
前記金属酸化膜を形成した後、前記金属酸化膜の上に前記ゲート電極が形成される領域に開口部を有する絶縁膜を形成する工程を有し、
前記ゲート電極は、前記絶縁膜の開口部における前記金属酸化膜の上に形成することを特徴とする付記11から13のいずれかに記載の半導体装置の製造方法。
(付記15)
前記第2の半導体層を形成した後、前記第2の半導体層における前記ゲート電極が形成される領域の一部を除去することにより、ゲートリセスを形成する工程を有し、
前記ゲートリセスを形成した後、前記第2の半導体層を水蒸気により酸化することにより金属酸化膜を形成し、
前記ゲートリセスが形成されている領域にゲート電極を形成することを特徴とする付記11から14のいずれかに記載の半導体装置の製造方法。
(付記16)
基板の上に、窒化物半導体により第1の半導体層を形成する工程と、
前記第1の半導体層の上に、窒化物半導体により第2の半導体層を形成する工程と、
前記第2の半導体層の上に、ソース電極及びドレイン電極を形成する工程と、
前記ソース電極と前記ドレイン電極との間における前記第2の半導体層の表面を水蒸気により酸化することにより第1の酸化領域を形成する工程と、
前記第1の酸化領域の上に、前記ゲート電極が形成される領域に開口部を有する絶縁膜を形成する工程と、
前記開口部が形成されている領域において、前記第2の半導体層を水蒸気により酸化することにより、前記第1の酸化領域よりも深くに第2の酸化領域を形成し、前記第1の酸化領域と前記第2の酸化領域とにより金属酸化膜を形成する工程と、
前記絶縁膜の開口部における前記金属酸化膜の上に、ゲート電極を形成する工程と、
有することを特徴とする半導体装置の製造方法。
(付記17)
前記第1の酸化領域を形成する際には、前記水蒸気の温度は、300℃以上、500℃以下であり、
前記第2の酸化領域を形成する際には、前記水蒸気の温度は、500℃を超え、800℃以下であることを特徴とする付記16に記載の半導体装置の製造方法。
(付記18)
前記第2の半導体層は、InAlNまたはInAlGaNを含む材料により形成されていることを特徴とする付記11から17のいずれかに記載の半導体装置の製造方法。
(付記19)
付記1から10のいずれかに記載の半導体装置を有することを特徴とする電源装置。
(付記20)
付記1から10のいずれかに記載の半導体装置を有することを特徴とする増幅器。
21 電子走行層(第1の半導体層)
21a 2DEG
22 スペーサ層
23 電子供給層(第2の半導体層)
24 金属酸化膜
31 ゲート電極
32 ソース電極
33 ドレイン電極
40 保護膜
Claims (1)
- 基板の上に、窒化物半導体により第1の半導体層を形成する工程と、
前記第1の半導体層の上に、窒化物半導体により第2の半導体層を形成する工程と、
前記第2の半導体層の上に、ソース電極及びドレイン電極を形成する工程と、
前記ソース電極と前記ドレイン電極との間における前記第2の半導体層の表面を水蒸気により酸化することにより第1の酸化領域を形成する工程と、
前記第1の酸化領域の上に、ゲート電極が形成される領域に開口部を有する絶縁膜を形成する工程と、
前記開口部が形成されている領域において、前記第2の半導体層を水蒸気により酸化することにより、前記第1の酸化領域よりも深くに第2の酸化領域を形成し、前記第1の酸化領域と前記第2の酸化領域とにより金属酸化膜を形成する工程と、
前記絶縁膜の開口部における前記金属酸化膜の上に、前記ゲート電極を形成する工程と、
を有することを特徴とする半導体装置の製造方法。
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