JP6838893B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP6838893B2
JP6838893B2 JP2016164540A JP2016164540A JP6838893B2 JP 6838893 B2 JP6838893 B2 JP 6838893B2 JP 2016164540 A JP2016164540 A JP 2016164540A JP 2016164540 A JP2016164540 A JP 2016164540A JP 6838893 B2 JP6838893 B2 JP 6838893B2
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Prior art keywords
opening
mask
semiconductor substrate
insulating film
film
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JP2016164540A
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English (en)
Japanese (ja)
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JP2018032757A (ja
JP2018032757A5 (https=
Inventor
秀将 大重
秀将 大重
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Canon Inc
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Canon Inc
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Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2016164540A priority Critical patent/JP6838893B2/ja
Priority to US15/664,057 priority patent/US10607886B2/en
Publication of JP2018032757A publication Critical patent/JP2018032757A/ja
Publication of JP2018032757A5 publication Critical patent/JP2018032757A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2016164540A 2016-08-25 2016-08-25 半導体装置及びその製造方法 Active JP6838893B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016164540A JP6838893B2 (ja) 2016-08-25 2016-08-25 半導体装置及びその製造方法
US15/664,057 US10607886B2 (en) 2016-08-25 2017-07-31 Semiconductor device with conductive member in tapered through-hole in semiconductor substrate and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016164540A JP6838893B2 (ja) 2016-08-25 2016-08-25 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2018032757A JP2018032757A (ja) 2018-03-01
JP2018032757A5 JP2018032757A5 (https=) 2020-09-17
JP6838893B2 true JP6838893B2 (ja) 2021-03-03

Family

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JP2016164540A Active JP6838893B2 (ja) 2016-08-25 2016-08-25 半導体装置及びその製造方法

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US (1) US10607886B2 (https=)
JP (1) JP6838893B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727216B1 (en) 2019-05-10 2020-07-28 Sandisk Technologies Llc Method for removing a bulk substrate from a bonded assembly of wafers
EP3912189B1 (en) * 2019-08-02 2023-08-02 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices and fabricating methods thereof
CN113539946B (zh) 2020-04-16 2023-07-07 长鑫存储技术有限公司 半导体结构及其形成方法
US12396272B2 (en) * 2021-01-18 2025-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Stilted pad structure

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4325182A (en) * 1980-08-25 1982-04-20 General Electric Company Fast isolation diffusion
JPS5831531A (ja) * 1981-08-19 1983-02-24 Hitachi Ltd エツチング方法
JPH11307627A (ja) * 1997-08-01 1999-11-05 Nippon Steel Corp 半導体装置及びその製造方法
JP5259197B2 (ja) * 2008-01-09 2013-08-07 ソニー株式会社 半導体装置及びその製造方法
JP2012059881A (ja) 2010-09-08 2012-03-22 Toshiba Corp 撮像素子、撮像モジュール及び撮像素子の製造方法
JP2012164711A (ja) 2011-02-03 2012-08-30 Renesas Electronics Corp 半導体装置及びその製造方法
JP5810921B2 (ja) 2012-01-06 2015-11-11 凸版印刷株式会社 半導体装置の製造方法
JP5984134B2 (ja) * 2012-05-15 2016-09-06 ローム株式会社 半導体装置およびその製造方法、電子部品
JP6002008B2 (ja) 2012-11-19 2016-10-05 富士電機株式会社 半導体装置の製造方法
JP2015002299A (ja) 2013-06-17 2015-01-05 株式会社ザイキューブ 漏斗状の貫通電極およびその製造方法
KR102411064B1 (ko) * 2015-03-10 2022-06-21 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그의 제조방법
JP2016001759A (ja) * 2015-09-16 2016-01-07 凸版印刷株式会社 半導体装置

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US10607886B2 (en) 2020-03-31
US20180061710A1 (en) 2018-03-01

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