JP6812572B2 - 半導体ウェハの表面上への層の堆積の間に配向ノッチを有する半導体ウェハを保持するためのサセプタおよびサセプタを用いることによって層を堆積する方法 - Google Patents
半導体ウェハの表面上への層の堆積の間に配向ノッチを有する半導体ウェハを保持するためのサセプタおよびサセプタを用いることによって層を堆積する方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 79
- 238000000034 method Methods 0.000 title claims description 12
- 238000000151 deposition Methods 0.000 title claims description 6
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 70
- 239000013078 crystal Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910002804 graphite Inorganic materials 0.000 description 4
- 239000010439 graphite Substances 0.000 description 4
- 238000012876 topography Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68785—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/458—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
- C23C16/4582—Rigid and flat substrates, e.g. plates or discs
- C23C16/4583—Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
- C23C16/4585—Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge clamping, e.g. clamping ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68735—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by edge profile or support profile
Description
US2008/0118712A1は、サセプタリングと、サセプタベースとを備える、サセプタを開示している。サセプタリングは、半導体ウェハの裏面の縁部領域に半導体ウェハを配置するための出っ張りを有し、半導体ウェハの表面上に層を堆積する目的のためにサセプタベース上に配置される。配置された半導体ウェハは、サセプタのポケットに位置する。サセプタリングの中央部と外側限界の内側縁部との間の半径は、ポケットの半径を規定する。サセプタリングおよびサセプタベースは、2部品のユニットを形成する。
図1は、サセプタベース7、サセプタリング6および配向ノッチ3を有する半導体ウェハ2の相対配置を示す。使用の間、サセプタリング6はサセプタベース7上にあり、半導体ウェハ2はサセプタリング6の配置領域8上にある。サセプタベース7およびサセプタリング6の直径は同じであってもよい。しかしながら、サセプタベース7の直径は、サセプタリング6の直径よりも大きくてもよい。図から逸脱するものとして、サセプタリング6およびサセプタベース7は、1部品のユニットを形成してもよい。
a)半導体ウェハが配置領域上にある状況において、サセプタの4つの位置のうちの3つの他の位置における、半導体ウェハの外側縁部とサセプタリングの外側限界の内側縁部との間の距離Aは、サセプタのノッチ位置におけるものよりも大きく、サセプタのさらに別の4つの位置におけるものよりも大きい;
b)サセプタの4つの位置のうちの3つの他の位置における、サセプタリングの配置領域の径方向幅Wは、サセプタのノッチ位置におけるものよりも大きく、サセプタのさらに別の4つの位置におけるものよりも大きい;
c)サセプタの4つの位置のうちの3つの他の位置における、サセプタリングの外側限界の高さHは、サセプタのノッチ位置におけるものよりも小さく、サセプタのさらに別の4つの位置におけるものよりも小さい;
d)サセプタの4つの位置のうちの3つの他の位置における、サセプタの厚さDは、サセプタのノッチ位置におけるものよりも大きく、サセプタのさらに別の4つの位置におけるものよりも大きい;
e)サセプタの4つの位置のうちの3つの他の位置における、サセプタリングの外側限界の径方向幅Bは、サセプタのノッチ位置におけるものよりも大きく、サセプタのさらに別の4つの位置におけるものよりも大きい;
f)サセプタリングの外側限界は、外側限界の内側縁部から外側限界の外側縁部まで、サセプタの4つの位置のうちの3つの他の位置において高さH1でとどまり、サセプタのノッチ位置およびサセプタのさらに別の4つの位置において、高さH2から高さH1まで減少する。
<100>配向および300mmの直径を有する単結晶シリコンの半導体ウェハが、単一ウェハ反応器において、シリコンのエピタキシャル層でコーティングされた。エピタキシャル層の厚さは、2μmであった。サセプタは、第6の実施形態にしたがって形成された。半導体ウェハは、<110>方向をマークする配向ノッチを有し、配向ノッチおよびサセプタのノッチ位置が半導体ウェハの中央部に向かう線上に配置されるように、サセプタ上へ配置された。加えて、ノッチ位置におけるサセプタ上には、内向きの配置領域の突起および内向きの外側限界の突起の両方が存在した。
2 半導体ウェハ
3 半導体ウェハの配向ノッチ
4 層
5 半導体ウェハの外側縁部
6 サセプタリング
7 サセプタベース
8 サセプタリングの配置領域
9 配置領域の内側縁部
10 サセプタリングの外側限界
11 外側限界の内側縁部
12 外側限界の外側縁部
13 配置領域の突起
14 外側限界の突起
Claims (8)
- 半導体ウェハの表面上への層の堆積する間に、配向ノッチを有する前記半導体ウェハを保持するためのサセプタであって、
サセプタリングと、サセプタベースと、を備え、
前記サセプタリングは、前記半導体ウェハの裏面の縁部領域に前記半導体ウェハを配置するための配置領域と、前記配置領域に隣接する前記サセプタリングの段差形状の外側限界とを備え、
前記サセプタは、4つの位置を有し、前記4つの位置において、前記サセプタの構造がさらに別の4つの位置における前記サセプタの構造と異なり、
前記4つの位置の1つから前記4つの位置の隣のものまでの間隔は90°であり、前記4つの位置の1つから隣のさらに別の位置までの間隔は45°であり、
前記4つの位置の1つは、ノッチ位置であり、前記ノッチ位置において、前記サセプタの構造は、前記サセプタの前記4つの位置のうちの3つの他の位置における前記サセプタの構造と異なり、
前記サセプタの前記ノッチ位置に、内向きの前記配置領域の突起および内向きの前記外側限界の突起が存在する、サセプタ。 - 半導体ウェハが前記配置領域上にある状況において、前記サセプタの前記4つの位置のうちの前記3つの他の位置における、前記半導体ウェハの外側縁部と前記サセプタリングの前記外側限界の内側縁部との間に存在する距離Aは、前記サセプタの前記ノッチ位置におけるものよりも小さく、前記サセプタの前記さらに別の4つの位置におけるものよりも小さい、請求項1に記載のサセプタ。
- 前記サセプタの前記4つの位置のうちの前記3つの他の位置における、前記サセプタリングの前記配置領域の径方向幅Wは、前記サセプタの前記ノッチ位置におけるものよりも小さく、前記サセプタの前記さらに別の4つの位置におけるものよりも小さい、請求項1に記載のサセプタ。
- 前記サセプタの前記4つの位置のうちの前記3つの他の位置における、前記サセプタリングの前記外側限界の高さHは、前記サセプタの前記ノッチ位置におけるものよりも大きく、前記サセプタの前記さらに別の4つの位置におけるものよりも大きい、請求項1に記載のサセプタ。
- 前記サセプタの前記4つの位置のうちの前記3つの他の位置における,前記サセプタの厚さDは、前記サセプタの前記ノッチ位置におけるものよりも小さく、前記サセプタの前記さらに別の4つの位置におけるものよりも小さい、請求項1に記載のサセプタ。
- 前記サセプタの前記4つの位置のうちの前記3つの他の位置における、前記サセプタリングの前記外側限界の径方向幅Bは、前記サセプタの前記ノッチ位置におけるものよりも小さく、前記サセプタの前記さらに別の4つの位置におけるものよりも小さい、請求項1に記載のサセプタ。
- 前記サセプタリングの前記外側限界は、前記サセプタの前記4つの位置のうちの前記3つの他の位置において、前記外側限界の内側縁部から前記外側限界の外側縁部まで、高さH2から高さH1まで減少し、前記サセプタの前記ノッチ位置および前記サセプタの前記さらに別の4つの位置において、前記H1でとどまる、請求項1に記載のサセプタ。
- 配向ノッチを有する半導体ウェハの表面上に層を堆積する方法であって、前記半導体ウェハは、<100>配向を有し、
前記配向ノッチおよび前記サセプタの前記ノッチ位置が前記半導体ウェハの中央部に向かう線上に配置されるように、請求項1から請求項7のいずれか1項に記載のサセプタリング上に、前記半導体ウェハを配置することと、
単一ウェハ反応器において前記半導体ウェハの前記表面をコーティングすることと、を含む、方法。
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DE102017206671.7A DE102017206671A1 (de) | 2017-04-20 | 2017-04-20 | Suszeptor zum Halten einer Halbleiterscheibe mit Orientierungskerbe während des Abscheidens einer Schicht auf einer Vorderseite der Halbleiterscheibe und Verfahren zum Abscheiden der Schicht unter Verwendung des Suszeptors |
DE102017206671.7 | 2017-04-20 | ||
PCT/EP2018/059726 WO2018192902A1 (de) | 2017-04-20 | 2018-04-17 | Suszeptor zum halten einer halbleiterscheibe mit orientierungskerbe sowie abscheideverfahren |
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DE112007000345T8 (de) * | 2006-02-09 | 2009-07-16 | Sumco Techxiv Corp., Omura | Suszeptor und Einrichtung zur Herstellung eines Epitaxie-Wafers |
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JP4868522B2 (ja) * | 2006-03-30 | 2012-02-01 | Sumco Techxiv株式会社 | エピタキシャルウェーハの製造方法及び製造装置 |
DE102006055038B4 (de) * | 2006-11-22 | 2012-12-27 | Siltronic Ag | Epitaxierte Halbleiterscheibe sowie Vorrichtung und Verfahren zur Herstellung einer epitaxierten Halbleiterscheibe |
JP5444607B2 (ja) * | 2007-10-31 | 2014-03-19 | 株式会社Sumco | エピタキシャル膜形成装置用のサセプタ、エピタキシャル膜形成装置、エピタキシャルウェーハの製造方法 |
DE102008023054B4 (de) * | 2008-05-09 | 2011-12-22 | Siltronic Ag | Verfahren zur Herstellung einer epitaxierten Halbleiterscheibe |
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DE102011007682A1 (de) | 2011-04-19 | 2012-10-25 | Siltronic Ag | Suszeptor zum Abstützen einer Halbleiterscheibe und Verfahren zum Abscheiden einer Schicht auf einer Vorderseite einer Halbleiterscheibe |
KR20120123207A (ko) * | 2011-04-19 | 2012-11-08 | 실트로닉 아게 | 반도체 웨이퍼를 지지하는 서셉터 및 반도체 웨이퍼의 전면 상에 층을 증착하는 방법 |
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US20130263779A1 (en) | 2012-04-10 | 2013-10-10 | Memc Electronic Materials, Inc. | Susceptor For Improved Epitaxial Wafer Flatness |
KR101496572B1 (ko) * | 2012-10-16 | 2015-02-26 | 주식회사 엘지실트론 | 에피택셜 성장용 서셉터 및 에피택셜 성장방법 |
DE102015220924B4 (de) * | 2015-10-27 | 2018-09-27 | Siltronic Ag | Suszeptor zum Halten einer Halbleiterscheibe mit Orientierungskerbe, Verfahren zum Abscheiden einer Schicht auf einer Halbleiterscheibe und Halbleiterscheibe |
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KR20190139976A (ko) | 2019-12-18 |
JP2020518129A (ja) | 2020-06-18 |
EP3613072B1 (de) | 2022-07-27 |
SG11201907680VA (en) | 2019-09-27 |
CN110546752B (zh) | 2023-07-14 |
EP3613072A1 (de) | 2020-02-26 |
KR102335880B1 (ko) | 2021-12-03 |
WO2018192902A1 (de) | 2018-10-25 |
TWI677601B (zh) | 2019-11-21 |
US20200365443A1 (en) | 2020-11-19 |
TW201839187A (zh) | 2018-11-01 |
DE102017206671A1 (de) | 2018-10-25 |
CN110546752A (zh) | 2019-12-06 |
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