JP6727365B1 - 半導体記憶装置 - Google Patents
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/54—Arrangements for designing test circuits, e.g. design for test [DFT] tools
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
- G06F2212/1036—Life time enhancement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7205—Cleaning, compaction, garbage collection, erase control
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7207—Details relating to flash memory management management of metadata or control data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
さらに本発明は、プログラム数を抑制しつつスペア領域を有効に利用することができる半導体記憶装置を提供することを目的とする。
110:メモリセルアレイ
120:入力バッファ
130:アドレスレジスタ
140:コントローラ
142:SRAM
144:RRAM
150:ワード線選択回路
160:ページバッファ/センス回路
170:列選択回路
200:レギュラー領域
210:スペア領域
Claims (8)
- 複数のブロックを含むNAND型のメモリセルアレイと、
論理アドレス情報を物理アドレス情報に変換するための変換情報を保持する第1の保持手段と、
消去すべきブロックを識別するための物理アドレス情報を保持する第2の保持手段と、
プログラム/消去回数に基づき選択された消去済みの使用可能なブロックを識別するための物理アドレス情報を保持する第3の保持手段と、
前記メモリセルアレイのブロックを消去する消去手段と、
制御手段とを有し、
前記制御手段は、
外部から消去コマンドおよび論理アドレス情報を受け取ったとき、前記変換情報に基づき前記論理アドレスを第1の物理アドレス情報に変換し、
前記第2の保持手段で保持された第2の物理アドレス情報が第1の物理アドレス情報に一致しない場合には、第2の物理アドレス情報に該当するブロックを前記消去手段に消去させ、
さらに前記第3の保持手段で保持された第3の物理アドレス情報が前記論理アドレス情報に対応するように前記第1の保持手段の変換情報を更新する、半導体記憶装置。 - 前記制御手段は、第1の物理アドレス情報を前記第2の保持手段に追加し、第3の物理アドレス情報を前記第3の保持手段から削除する、請求項1に記載の半導体記憶装置。
- 半導体記憶装置はさらに、前記メモリセルアレイの選択ページにデータをプログラムするためのプログラム手段を含み、
前記制御手段は、前記プログラム手段に、第3の物理アドレス情報に該当するブロックの選択されたページのスペア領域に前記論理アドレス情報と当該ブロックが使用中になったことを示すステータスとをプログラムさせる、請求項1に記載の半導体記憶装置。 - 前記制御手段は、前記プログラム手段に、第1の物理アドレス情報に該当するブロックの選択されたページのスペア領域に当該ブロックが消去すべきブロックになったことを示すステータスをプログラムさせる、請求項3に記載の半導体記憶装置。
- メモリセルアレイの決められた領域にブロックのステータスに関する情報がプログラムされ、
前記制御手段は、前記ステータスに関する情報に基づき前記第1、第2、第3の保持手段で保持される情報を生成する、請求項1ないし4いずれか1つに記載の半導体記憶装置。 - 前記制御手段は、電源投入時に前記メモリセルアレイから前記ステータスに関する情報を読み出す、請求項5に記載の半導体記憶装置。
- 半導体記憶装置はさらに、消去動作時に各ブロックのステータスに関する情報を保持する第4の保持手段を含み、
前記制御手段は、プログラム動作時に、前記第4の保持手段に保持されたステータスに関する情報をメモリセルアレイの該当するスペア領域にプログラムさせる、請求項1ないし6いずれか1つに記載の半導体記憶装置。 - 前記第4の保持手段は、不揮発性メモリにステータスに関する情報を保持する、請求項7に記載の半導体記憶装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019060533A JP6727365B1 (ja) | 2019-03-27 | 2019-03-27 | 半導体記憶装置 |
TW108144904A TWI706249B (zh) | 2019-03-27 | 2019-12-09 | 半導體儲存裝置 |
CN201911357506.7A CN111768808B (zh) | 2019-03-27 | 2019-12-25 | 半导体存储装置 |
US16/742,872 US11221945B2 (en) | 2019-03-27 | 2020-01-14 | Semiconductor memory device |
KR1020200013719A KR102294042B1 (ko) | 2019-03-27 | 2020-02-05 | 반도체 메모리 장치 |
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JP2019060533A JP6727365B1 (ja) | 2019-03-27 | 2019-03-27 | 半導体記憶装置 |
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JP6727365B1 true JP6727365B1 (ja) | 2020-07-22 |
JP2020160871A JP2020160871A (ja) | 2020-10-01 |
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US (1) | US11221945B2 (ja) |
JP (1) | JP6727365B1 (ja) |
KR (1) | KR102294042B1 (ja) |
CN (1) | CN111768808B (ja) |
TW (1) | TWI706249B (ja) |
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US11416405B1 (en) | 2020-02-07 | 2022-08-16 | Marvell Asia Pte Ltd | System and method for mapping memory addresses to locations in set-associative caches |
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KR102233808B1 (ko) * | 2014-03-14 | 2021-03-30 | 삼성전자주식회사 | 저장 장치 및 그것의 테이블 관리 방법 |
JP5734492B1 (ja) * | 2014-05-08 | 2015-06-17 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
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2019
- 2019-03-27 JP JP2019060533A patent/JP6727365B1/ja active Active
- 2019-12-09 TW TW108144904A patent/TWI706249B/zh active
- 2019-12-25 CN CN201911357506.7A patent/CN111768808B/zh active Active
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2020
- 2020-01-14 US US16/742,872 patent/US11221945B2/en active Active
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KR20200116019A (ko) | 2020-10-08 |
KR102294042B1 (ko) | 2021-08-26 |
CN111768808A (zh) | 2020-10-13 |
US11221945B2 (en) | 2022-01-11 |
CN111768808B (zh) | 2022-06-07 |
TWI706249B (zh) | 2020-10-01 |
TW202036302A (zh) | 2020-10-01 |
JP2020160871A (ja) | 2020-10-01 |
US20200310960A1 (en) | 2020-10-01 |
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