JP6716737B2 - Transistor - Google Patents

Description

The present invention relates to an object, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture or composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one mode of a semiconductor device. Further, the arithmetic device, the storage device, the imaging device, the electro-optical device, the power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and the electronic device may include a semiconductor device.

The physical properties of oxides containing indium and zinc are interesting and many have been studied (
Non-Patent Documents 1 and 2). In Non-Patent Document 1, In _1-x Ga _1+x O ₃ (ZnO).
It is stated that there is a homologous phase represented by _m (x is a number satisfying -1≤x≤1, and m is a natural number). In addition, the solid solution region of the homologous phase (solid solution r
ange) is described. For _{example, In 2 O 3, Ga 2} O 3, and a powder of ZnO were mixed, when fired at 1350 ° C., solid solution region of homologous phase in the case of m = 1 is, x
Is from -0.33 to 0.08, and x is from -0.68 to 0.32 in the solid solution region of the homologous phase when m=2.

Further, as a compound having a spinel type crystal structure, a compound represented by AB ₂ O ₄ (A and B are metals) is known. Non-Patent Document 1 shows an example of In _x Zn _y Ga _z O _w , where x, y and z are compositions near ZnGa ₂ O ₄ , that is, x, y and z are (x, y).
, Z)=(0, 1, 2), spinel type crystal structures are likely to be formed or mixed.

In addition, a technique for forming a transistor using a semiconductor material has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique of manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2).

Further, in recent years, as electronic devices have become higher in performance, smaller in size, and lighter in weight, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density.

JP, 2007-123861, A JP, 2007-96055, A

M. Nakamura, N.; Kimizuka, and T.M. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350[deg.] C.", J. Am. Solid State Chem. , 1991, Vol. 93, pp. 298-315 M. Nespolo, A.; Sato, T.; Osawa, and H.; Ohashi, “Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. Res. Technol. , 2000 Vol. 35, pp 151-165

One object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics.

Another object is to provide a highly reliable semiconductor device.

Another object is to provide a favorable transistor with less variation in characteristics. Another object is to provide a semiconductor device including a memory element with favorable retention characteristics. Another object is to provide a semiconductor device suitable for miniaturization. Another object is to provide a semiconductor device with a reduced circuit area. Another object is to provide a semiconductor device having a novel structure.

Note that the description of these problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. The problems other than these are obvious from the description of the specification, drawings, claims, etc.
Problems other than these can be extracted from the drawings, claims and the like.

One embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, or tin. The ratio of the numbers of atoms of indium, indium, element M and zinc is indium:element M.
:Zinc=x:y:z is satisfied, and x, y and z are the first coordinates (x:y:z=8:14) in the equilibrium diagram having three elements of indium, element M and zinc as vertices. : 7), second coordinates (x:y:z=2:4:3), third coordinates (x:y:z=2:5:7), and fourth coordinates (x: y:z=51:149:300) and the fifth coordinate (x:y:z=46:288)
: 833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z=
0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment, and the ratio of the number of atoms in the range is And the range includes the first coordinate to the sixth coordinate, does not include the seventh coordinate and the eighth coordinate, and uses an electron beam having a half-value width of the probe diameter of 1 nm. When a plurality of electron diffraction patterns are observed by irradiating the electron beam while moving the position of the oxide semiconductor film and the position of the electron beam relative to the formation surface of the The pattern has 50 or more electron diffraction patterns observed at different positions, and has a ratio of the first electron diffraction pattern to the 50 or more electron diffraction patterns and a second electron diffraction pattern. The sum of the proportions is 100%, and the first
The electron diffraction pattern of has an observation point having no symmetry or a plurality of observation points arranged so as to draw a circle, and the second electron diffraction pattern has an observation point located at the apex of the hexagon. The oxide semiconductor film has.

Alternatively, according to one embodiment of the present invention, the position of the oxide semiconductor film and the position of the electron beam are relative to the formation surface of the oxide semiconductor film by using an electron beam having a half-width of the probe diameter of 1 nm. When a plurality of electron diffraction patterns are observed by irradiating an electron beam while moving the same, the plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at different positions. The sum of the proportion having the first electron diffraction pattern and the proportion having the second electron diffraction pattern is 100%, and the proportion having the first electron diffraction pattern is 50%. As described above, the first electron diffraction pattern has observation points having no symmetry or a plurality of observation points arranged so as to draw a circle, and the second electron diffraction pattern has a hexagonal vertex. The oxide semiconductor film has an observation point located at.

Alternatively, according to one embodiment of the present invention, In:M(Al, Ga, Y, or Sn):Zn=x:y.
: Z is an oxide semiconductor film represented by the atomic ratio, and has coordinates x:y:z=1:0:0, coordinates x:y:z=0:1:0, and coordinates x:y. In the equilibrium state diagram with vertices :z=0:0:1, the first coordinates (x:y:z=8:14:7) and the second coordinates (x:y:z=2). :
4:3), the third coordinate (x:y:z=2:5:7), and the fourth coordinate (x:y:z=51).
149:300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate ( x:y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment. And the position of the oxide semiconductor film and the position of the electron beam having a half-value width of the probe diameter of 1 nm are relatively moved with respect to the formation surface of the oxide semiconductor film. Observing the above electron diffraction patterns, 50 or more electron diffraction patterns have at least an asymmetric electron diffraction pattern having a plurality of spots and an electron diffraction pattern having a plurality of spots arranged in a circle. And an electron diffraction pattern having spots arranged at the vertices of a hexagon, and the range includes the first coordinate to the sixth coordinate,
And an eighth coordinate are not included.

In the above structure, the oxide semiconductor film contains indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, or tin. , The number of atoms of element M and zinc is indium:element M.
:Zinc=x:y:z is satisfied, and x, y and z are the first coordinates (x:y:z=8:14) in the equilibrium diagram having three elements of indium, element M and zinc as vertices. : 7), second coordinates (x:y:z=2:4:3), third coordinates (x:y:z=2:5:7), and fourth coordinates (x: y:z=51:149:300) and the fifth coordinate (x:y:z=46:288)
: 833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z=
0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment, and the ratio of the number of atoms in the range is included. However, it is preferable that the range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, the oxide semiconductor film having a plurality of crystal parts arranged at random and a plurality of crystals. The average of the diameters of the portions in the longitudinal direction is 1 nm or more and 3 nm or less in the oxide semiconductor film.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, or tin. And the ratio of the numbers of atoms of indium, element M and zinc satisfies indium:element M:zinc=x:y:z, and x, y and z have three elements of indium, element M and zinc as apexes. In the equilibrium diagram, the first coordinate (x:y:z=8:14:7)
And the second coordinate (x:y:z=2:4:3) and the third coordinate (x:y:z=2:5:7).
And the fourth coordinate (x:y:z=51:149:300) and the fifth coordinate (x:y:z=4).
6:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x
:Y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate in the order of being connected by a line segment. And the range includes the first coordinate to the sixth coordinate, does not include the seventh coordinate and the eighth coordinate, and the density of the oxide semiconductor film has a single atomic number ratio. The oxide semiconductor film has a crystal density of 90% or more.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, or tin. The oxide semiconductor film has a plurality of randomly arranged crystal parts, the plurality of crystal parts have no orientation, and the crystal parts have a longitudinal diameter of 1 nm or more and 3 n or more.
The density of the oxide semiconductor film is 9 times that of a single crystal having the same atomic ratio.
The oxide semiconductor film is 0% or more.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, the oxide semiconductor film having a plurality of crystal parts, and the plurality of crystal parts having an orientation property. the no, the average longitudinal diameter of the plurality of crystal parts is at 1nm or more 3nm or less, the density of the oxide semiconductor film is 5.7 g / cm ³ or more 6.49 g / cm ³ or less oxide It is a semiconductor film. In the above structure, the density of the oxide semiconductor film is preferably 90% or more of the density of a single crystal having the same atomic number ratio.

Alternatively, one embodiment of the present invention is an oxide semiconductor film which contains indium, gallium, and zinc, and the oxide semiconductor film has a plurality of crystal parts which are randomly arranged and a plurality of crystal parts. Has no orientation, and the average A [nm] of the diameters of the plurality of crystal parts in the longitudinal direction is 1 nm or more and 3
nm or less, and the electron beam energy is 1×10 ⁷ [e ⁻ /nm ² ] or more and 4×10 ⁸ [
e ^- / nm ^2] after being irradiated below, the average B in the longitudinal direction of the diameter of the crystal unit [nm] is, A ×
The oxide semiconductor film is larger than 0.7 and smaller than A×1.3.

In the above structure, the oxide semiconductor film is formed by a sputtering method, and a target used for the sputtering method has indium, an element M, and zinc, and the target has indium, the element M, and an atom of zinc. The numerical ratio is indium:element M:zinc=
a:b:c are satisfied, and a, b, and c are the first coordinates (a:b:c=8:14:) in the equilibrium diagram in which the three elements of indium, element M, and zinc are vertices. 7), second coordinates (a:b:c=2:4:3), third coordinates (a:b:c=1:2:5.1), and fourth coordinates (a :B:c=1:0:1.7), the fifth coordinate (a:b:c=8:0:1), and the sixth coordinate (a:b:c=6:2:1). ) And the first coordinate have a ratio of the number of atoms in the range sequentially connected by a line segment, and the range preferably includes the first coordinate to the sixth coordinate.

Alternatively, one embodiment of the present invention is a semiconductor device including any of the above oxide semiconductor films.
Further, in the above structure, the oxide semiconductor includes a first conductive layer, a first insulating film in contact with an upper surface and a side surface of the first conductive layer, and a pair of electrodes in contact with an upper surface of the oxide semiconductor film. The membrane is the first
It is preferable to have a region in contact with the upper surface of the insulating film. In the above structure, the first conductive layer, the first insulating film in contact with the upper surface and the side surface of the first conductive layer, the second insulating film in contact with the upper surface of the oxide semiconductor film, and the oxide semiconductor film The oxide semiconductor film preferably has a pair of electrodes in contact with the top surface and the top surface and side surfaces of the second insulating film, and the oxide semiconductor film preferably has a region in contact with the top surface of the first insulating film. In the above structure, it is preferable to have a second oxide film which is in contact with the upper surface of the oxide semiconductor film. Further, in the above structure, the electron affinity of the oxide included in the oxide semiconductor film is preferably higher than the electron affinity of the oxide included in the second oxide film. In the above structure, the second oxide film contains indium, the element M, and zinc, and the element M
Is an element selected from at least one of aluminum, gallium, yttrium, or tin, and the ratio of the numbers of atoms of indium, element M, and zinc contained in the second oxide film is indium:element M:zinc= It is represented by x ₂ :y ₂ :z ₂ , and (x ₂ :y ₂ :z ₂ ) is the first coordinate (8: 8) in the equilibrium diagram having the three elements of indium, element M and zinc as vertices. 1
4:7), the second coordinate (2:4:3), the third coordinate (2:5:7), and the fourth coordinate (
51:149:300), the fifth coordinate (1:4:10), and the sixth coordinate (1:1:4).
And a seventh coordinate (2:2:1) and the first coordinate are sequentially connected by a line segment, the ratio of the number of atoms in the range is included, and the range is from the first coordinate to the first coordinate. It is preferable to include the seventh coordinate.

Alternatively, one embodiment of the present invention is a display device including the semiconductor device described above and a display element.

Alternatively, one embodiment of the present invention is a module including the semiconductor device described above or the display device described above and an FPC.

Alternatively, one embodiment of the present invention is an electronic device including the semiconductor device described above, the display device described above, or the module described above, and a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a semiconductor device can have favorable electrical characteristics. Also,
A highly reliable semiconductor device can be provided.

In addition, a transistor with less variation can be provided. In addition, a semiconductor device having a memory element with favorable retention characteristics can be provided. Further, a semiconductor device suitable for miniaturization can be provided. Further, a semiconductor device with a reduced circuit area can be provided. In addition, a semiconductor device having a novel structure can be provided. Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have to have all of these effects. It should be noted that the effects other than these are obvious from the description of the specification, drawings, claims, etc., and from the description of the specification, drawings, claims, etc.,
It is possible to extract effects other than these.

7A and 7B are diagrams illustrating the atomic ratio of an oxide film according to one embodiment of the present invention. 7A and 7B are diagrams illustrating the atomic ratio of an oxide film according to one embodiment of the present invention. The figure explaining atomic number ratio. 7A and 7B are diagrams illustrating the atomic ratio of an oxide film according to one embodiment of the present invention. 6A and 6B each illustrate an atomic ratio of a target according to one embodiment of the present invention. The figure explaining atomic number ratio. 7A and 7B are diagrams illustrating a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. The figure which shows the analysis result by the X-ray-diffraction apparatus of nc-OS. The figure which shows the electron diffraction pattern of nc-OS. FIG. 8 illustrates a crystal of InGaZnO ₄ . 6A and 6B each illustrate a part of a band structure of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of CAAC-OS and nc-OS. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of CAAC-OS. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of CAAC-OS. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of nc-OS. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of nc-OS. The figure which shows the pellet size observed by the Cs correction|amendment high-resolution cross-sectional TEM image of CAAC-OS and nc-OS, and its frequency. 16A and 16B are graphs each showing the relation between the atomic ratio of a target and the atomic ratio of an oxide semiconductor film. The schematic diagram explaining the film-forming model of nc-OS, and the figure which shows a pellet. The schematic diagram explaining a film-forming apparatus. 3A and 3B are a block diagram and a circuit diagram illustrating a display device. FIG. 6 is a diagram of a display module according to an embodiment. 3 is a configuration example of an RF tag according to an embodiment. FIG. 10 illustrates an example of a transistor. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. 6A and 6B each illustrate an example of a transistor of one embodiment of the present invention. FIG. 6 is a top view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 3 is a circuit diagram according to an embodiment. FIG. 6 illustrates an example of a semiconductor device of one embodiment of the present invention. 6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 16A and 16B are XRD evaluation results of an oxide semiconductor film according to one embodiment of the present invention. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 11A is an electron diffraction pattern of an oxide semiconductor film. 17A and 17B show results of TDS analysis of an oxide semiconductor film. The figure which shows the change of the crystal|crystallization by electron beam irradiation. An example of using the RF tag according to the embodiment. An electronic device according to an embodiment. 6A and 6B are graphs showing film densities of oxide semiconductor films. FIG. 10 is a graph showing an etching rate of an oxide semiconductor film. FIG. 6 is a graph showing the amount of released gas from an oxide semiconductor film. FIG. 10 is a graph showing hydrogen concentration of an oxide semiconductor film. 16A and 16B each show a crystal size of an oxide semiconductor film. 16A and 16B each show a crystal size of an oxide semiconductor film. 16A and 16B show CPM measurement results of an oxide semiconductor film. 16A and 16B show CPM measurement results of an oxide semiconductor film. 16A and 16B show CPM measurement results of an oxide semiconductor film. The figure which shows the Cs correction|amendment high resolution cross-section TEM image of a-like OS. FIG. 10 is a graph showing hydrogen concentration of an oxide semiconductor film.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously modified without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

Note that, in the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description thereof is omitted. Further, when referring to the same function, the hatch patterns may be the same and may not be given a reference numeral in particular.

Note that in each drawing described in this specification, the size of each component, the layer thickness, or the region is as follows.
May be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that the ordinal numbers such as “first” and “second” in this specification and the like are added to avoid confusion among components, and are not limited numerically.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, a case of -5° or more and 5° or less is also included. Also,"
“Substantially parallel” means a state in which two straight lines are arranged at an angle of −30° or more and 30° or less. Further, “vertical” means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

A transistor is a kind of semiconductor element, and can realize amplification of current or voltage, switching operation for controlling conduction or non-conduction, and the like. A transistor in this specification is an IGFET (Insulated Gate Field Effect Trans).
istor) and thin film transistor (TFT: Thin Film Transistor)
)including.

(Embodiment 1)
In this embodiment, an example of the oxide semiconductor film which is one embodiment of the present invention will be described.

The oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film.
The non-single-crystal oxide semiconductor film means a CAAC-OS (CAxis Aligned Cry).
The term "stall oxide semiconductor" film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

The single crystal may be formed by firing at a high temperature of, for example, about 1000° C. or higher. Therefore, from an industrial viewpoint, it is preferable to use a non-single-crystal oxide semiconductor film which can be formed at a lower temperature because a semiconductor device can be manufactured at lower cost.

The smaller the grain boundaries of the oxide semiconductor film, the more preferable. By reducing the grain boundaries, for example, carrier mobility can be increased. When a transistor is formed using an oxide semiconductor film with few grain boundaries, a transistor with high field-effect mobility can be realized in some cases. As will be described in detail later, examples of the non-single-crystal oxide semiconductor film with few grain boundaries include an nc-OS film and a CAAC-OS film.

On the other hand, the oxide semiconductor film may include crystals with a spinel structure. A crystal having a spinel structure may be mixed in the CAAC-OS film or the nc-OS film to form a clear boundary portion (or grain boundary). At the boundary, for example, carrier scattering may increase and carrier mobility may decrease. Further, since the boundary portion is likely to serve as a moving path of impurities and trap impurities easily, there is a concern that the impurity concentration of the oxide semiconductor film is increased. Also,
When a conductive film is formed over the oxide semiconductor film, an element included in the conductive film, such as a metal, may diffuse to the boundary between the spinel and another region. Therefore, it is more preferable that the oxide semiconductor film do not include or have a spinel-type crystal structure.

Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When the oxide semiconductor contains indium, carrier mobility (electron mobility) is increased, for example. Further, the oxide semiconductor preferably contains the element M. The element M is preferably aluminum, gallium,
It should be yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, as the element M, there are cases where a plurality of the above-mentioned elements may be combined. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element having a binding energy with oxygen higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. In addition, the oxide semiconductor preferably contains zinc. The oxide semiconductor may be easily crystallized if it contains zinc. Here, an oxide containing indium, the element M, and zinc is referred to as an In-M-Zn oxide.

[About the ratio of the number of atoms]
The ratio of the number of atoms of an In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention is calculated as In:
It is expressed as M:Zn=x:y:z. A preferable range of x, y, and z will be described with reference to FIGS. 1 and 2.

Here, the ratio of the number of atoms of each element will be described with reference to FIG. FIG. 3 shows x, y, and z when the ratio of the numbers of atoms of the elements X, Y, and Z in the XYZ oxide film is x:y:z.
It is a figure which shows about the range of. Note that the atomic ratio of oxygen is not shown in FIG. Further, FIG. 3 may be referred to as an equilibrium state diagram. 3A and 3B show an equilateral triangle having vertices X, Y, and Z, and coordinates R(4:2:1) as an example of coordinates. Here, each vertex represents the elements X, Y, and Z, respectively. The value of each term in the ratio of the number of atoms is higher as the coordinate is closer to each vertex and lower as the distance is farther. Further, as shown in FIG. 3A, the value of each term in the atomic number ratio is represented by the length of a perpendicular line from the coordinate to the opposite side of the apex of the triangle. For example, the element X is represented by the length of the perpendicular line 21 from the coordinate to the opposite side of the vertex X, that is, the side YZ. Therefore, in the coordinate R shown in FIG. 3, the atomic ratio of the element X, the element Y, and the element Z is the ratio of the lengths of the vertical line 21, the vertical line 22, and the vertical line 23, that is, x:y:z=4:2:1. Indicates that there is. Further, a point where a straight line passing through the vertex X and the coordinate R intersects with the side YZ is γ. At this time, if the ratio of the length of the line segment Yγ to the length of the line segment γZ is Yγ:γZ, then Yγ:γZ=(number of atoms of element Z):(number of atoms of element Y).

Further, as shown in FIG. 3B, three straight lines passing through the coordinate R and parallel to the three sides of the triangle are drawn. At this time, x, y, and z can be expressed as shown in FIG. 3B by using the intersections of the three straight lines and the three sides.

In FIG. 6, the range is shown by a broken line when x:y:z in the In-M-Zn oxide film satisfies the following formula.

x:y:z=(1-α):(1+α):m (−1≦α≦1)

Here, FIG. 6 shows the case of m=1, 2, 3, 4, 5.

As described in Non-Patent Document 1, in the In-M-Zn _{oxide, InMO} 3 (Zn
It is known that there is a homologous phase represented by O) _m (m is a natural number) (homologous series). Here, as an example, consider a case where the element M is Ga. The region indicated by a thick straight line in FIG. 6 can be a single-phase solid solution region when, for example, In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and fired at 1350° C. Is a known composition. The solid solution region is
It is known that as the value of m is increased, that is, the proportion of zinc is increased, it becomes wider.

Further, the coordinates indicated by square symbols in FIG. 6 are, for example, as described in Non-Patent Document 1, when In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and fired at 1350° C. ,
It is a composition known to easily mix spinel type crystal structures. As shown in FIG. 6, when the composition in the vicinity of ZnGa ₂ O ₄ , that is, x, y and z have values close to (x, y, z)=(0, 2, 1), a spinel type crystal is formed. Non-Patent Document 1 describes that structures are likely to be formed or mixed.

The In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention preferably has a high proportion of indium. In the In-M-Zn oxide film, the s orbital of the metal atom mainly contributes to the carrier conduction, and by increasing the indium content, more s orbitals are overlapped, so that the indium content is high. Carrier mobility will be higher. When a transistor is manufactured using such a film for a channel region, a transistor having high field-effect mobility can be realized, for example. For example, x/y>0.5 is preferable,
x/y≧0.75 is more preferable, and x/y≧1 is still more preferable. Also, (x+y)≧z
Is preferred.

Therefore, x, y, and z preferably have a ratio of the number of atoms in the region 11 illustrated in FIG. 1 and more preferably have a ratio of the number of atoms in the region 12 illustrated in FIG. Here, the area 11 is
The first coordinate K (x:y:z=8:14:7) and the second coordinate R (x:y:z=2:4:3).
), the third coordinate L (x:y:z=2:5:7), and the fourth coordinate M (x:y:z=51:
149:300), the fifth coordinate N (x:y:z=46:288:833), the sixth coordinate O (x:y:z=0:2:11), and the seventh coordinate. P(x:y:z=0:0:1), the eighth coordinate Q(x:y:z=1:0:0), and the first coordinate K are sequentially represented by line segments. It is within the bound area. The area 11 includes a line segment connecting eight points. Further, the coordinates P and the coordinates Q are excluded from the area 11, and the other coordinates are included in the area 11. Further, the area 12 has the first coordinate K.
(X:y:z=8:14:7), the second coordinate R (x:y:z=2:4:3), and the third coordinate L (x:y:z=2:5). : 7), the fourth coordinate S (x:y:z=1:0:1), the fifth coordinate Q (x:y:z=1:0:0), and the first coordinate It is within a region in which K and K are sequentially connected by line segments. The area 12 includes a line segment connecting five points. Further, the coordinate Q is excluded from the area 12, and the other coordinates are included in the area 12.

[Structure of oxide semiconductor film]
Next, the structure of the oxide semiconductor film will be described.

First, the CAAC-OS film will be described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Transmission Electron Microscope (TEM)
A plurality of crystal parts can be confirmed by observing a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of the CAAC-OS film by oscopy. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed by a high-resolution TEM image. Therefore, the CAAC-OS film is
It can be said that the decrease in electron mobility due to the grain boundaries is unlikely to occur.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape that reflects unevenness of the surface (also referred to as a formation surface) of the CAAC-OS film, which is formed, or is aligned in parallel to the formation surface or the top surface of the CAAC-OS film. ..

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that the metal atoms are arranged in a triangular shape or a hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) having alignment are observed. For example, spots are observed when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm to 30 nm is performed on the formation surface or the top surface of the CAAC-OS film (FIG. 7B). reference.).

From the high-resolution TEM image of the cross section and the high-resolution TEM image of the plane, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most of the crystal parts included in the CAAC-OS film each fit inside a cube whose one side is less than 100 nm. Therefore, the crystal part included in the CAAC-OS film has a side of 10
It also includes a case of a size smaller than 5 nm, smaller than 5 nm, or smaller than 3 nm that fits in a cube. However, a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a high-resolution TEM image of a plane, a crystal region having a size of 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

X-ray diffraction (XRD: X-Ray Diffraction) of the CAAC-OS film
When structural analysis is performed using the apparatus, for example, a CAAC-OS including a crystal of InGaZnO ₄
In the analysis of the film by the out-of-plane method, a peak may appear near the diffraction angle (2θ) of 31°. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis faces a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, the in-pl which makes X-rays incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis
In the analysis by the ane method, a peak may appear near 2θ of 56°. This peak is assigned to the (110) plane of the InGaZnO ₄ crystal. In the case of an InGaZnO ₄ single crystal oxide semiconductor film, if 2θ is fixed at around 56° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), ( Six peaks attributed to a crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, 2θ is 5
No clear peak appears even when φ scan is performed with the angle fixed at around 6°.

From the above, in the CAAC-OS film, the a-axis and the b-axis are irregularly oriented between different crystal parts, but they have c-axis orientation and the c-axis is a normal to the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of the metal atoms arranged in layers, which is confirmed by the high-resolution TEM observation of the above-mentioned cross section, is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal might not be parallel to the normal vector of the formation surface or the upper surface of the CAAC-OS film.

Further, in the CAAC-OS film, the distribution of the c-axis aligned crystal parts may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region in the vicinity of the upper surface has a ratio of the c-axis aligned crystal parts in the region in the vicinity of the formation surface. Can be high. In addition, in the CAAC-OS film to which an impurity is added, the region to which an impurity is added is deteriorated, and regions in which the proportion of crystal parts partially c-axis aligned is different may be formed.

Note that an out-of-plane of a CAAC-OS film including a crystal of InGaZnO ₄ is used.
In the analysis by the method, in addition to the peak near 2θ of 31°, a peak may appear near 2θ of 36°. The peak near 2θ of 36° indicates that a part of the CAAC-OS film contains a crystal having no c-axis orientation. The CAAC-OS film preferably has a peak at 2θ of around 31° and no peak at 2θ of around 36°.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor film deprives the oxide semiconductor film of oxygen and thus disturbs the atomic arrangement of the oxide semiconductor film, resulting in crystallinity. Will be a factor to reduce. Further, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have a large atomic radius (or molecular radius); therefore, when contained in the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed and crystallinity is increased. Will be a factor to reduce. Note that the impurities contained in the oxide semiconductor film might serve as carrier traps or carrier generation sources.

Further, for example, oxygen vacancies in the oxide semiconductor film might serve as carrier traps or serve as carrier generation sources by capturing hydrogen. The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Specifically, it is less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×
An oxide semiconductor having a carrier density of 10 ⁻⁹ /cm ³ or more can be used.

In addition, a transistor including a CAAC-OS film has small variation in electric characteristics due to irradiation with visible light or ultraviolet light.

Next, the polycrystalline oxide semiconductor film will be described.

Crystal grains can be confirmed in a high-resolution TEM image of the polycrystalline oxide semiconductor film.
The crystal grains included in the polycrystalline oxide semiconductor film are, for example, a high-resolution TEM image of 2 nm or more and 3 nm or more.
The particle size is often 00 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less. In the high-resolution TEM image of the polycrystalline oxide semiconductor film, crystal grain boundaries can be found in some cases.

The polycrystalline oxide semiconductor film may include a plurality of crystal grains and crystal orientations may be different between the plurality of crystal grains. Further, when structural analysis is performed on the polycrystalline oxide semiconductor film by using an XRD apparatus, for example, ou of the polycrystalline oxide semiconductor film having InGaZnO ₄ crystals is obtained.
In the analysis by the t-of-plane method, a peak at 2θ of around 31°, a peak at 2θ of around 36°, or another peak may appear.

The polycrystalline oxide semiconductor film has high crystallinity and thus has high electron mobility in some cases. Therefore, a transistor including a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at crystal grain boundaries. Also,
A crystal grain boundary of the polycrystalline oxide semiconductor film becomes a defect level. Since a crystal grain boundary of a polycrystalline oxide semiconductor film might serve as a carrier trap or a carrier generation source, a transistor including a polycrystalline oxide semiconductor film has a large variation in electric characteristics and is a transistor with low reliability. May be.

Next, the microcrystalline oxide semiconductor film will be described.

The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. The crystal part included in the microcrystalline oxide semiconductor film is often 1 nm to 100 nm inclusive, or 1 nm to 10 nm inclusive. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystals) of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less is used.
c-OS (nano crystalline Oxide Semiconductor)
) Call it a membrane. Further, in the nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases.

The nc-OS film has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm inclusive, particularly a region of 1 nm to 3 nm inclusive). In the nc-OS film, no regularity is found in crystal orientation between different crystal parts. Therefore, no orientation is seen in the entire film.
Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, for the nc-OS film, XRD using X-rays having a diameter larger than that of the crystal part
When structural analysis is performed using an apparatus, a peak near 31° indicating a crystal plane is not detected by analysis by the out-of-plane method (see FIG. 8). Further, when electron diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter (eg, 50 nm or more) larger than that of a crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. To be done. On the other hand, spots are observed when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to or smaller than that of the crystal part. Further, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed like a circle (in a ring shape). When nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region. For example, as shown in FIG. 9A, when nc-OS having a thickness of about 50 nm is subjected to nanobeam electron diffraction with a probe diameter of 30 nm, 20 nm, 10 nm or 1 nm, a circle is drawn ( Areas with high brightness (in the form of rings) are observed. Further, it can be seen that as the probe diameter is reduced, the ring-shaped region is formed by a plurality of spots.

For more detailed structural analysis, the nc-OS film is thinned to a thickness of several nm (about 5 nm), and a transmission electron diffraction pattern is acquired using an electron beam with a probe diameter of 1 nm. As a result, a transmission electron diffraction pattern having spots having crystallinity shown in FIG. 9B was obtained.

When nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions may be observed.

The nc-OS film is an oxide semiconductor film having higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film.

In the nc-OS film, no regularity is found in crystal orientation between different crystal parts. for that reason,
The nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, nc-O
The S film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density may have high electron mobility. Therefore, a transistor including the nc-OS film might have high field-effect mobility.

The nc-OS film can be formed at a lower temperature than the CAAC-OS film. Also, nc-OS
The film may be formed even if it contains a relatively large amount of impurities. Therefore, n
The c-OS film may be easier to form than the CAAC-OS film. Therefore, nc-
A semiconductor device including a transistor including an OS film can be manufactured with high productivity in some cases.

In addition, the nc-OS film may have appropriate oxygen permeability. In the case of having appropriate oxygen permeability, for example, oxygen released from a film containing excess oxygen is likely to diffuse into the entire nc-OS film. Therefore, in the nc-OS film, oxygen vacancies may be easily reduced.

The low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high-purity intrinsic or substantially high-purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). Further, the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has low variation in electric characteristics and has high reliability. Note that the charge trapped in the carrier traps of the oxide semiconductor film takes a long time to be released, and may behave like fixed charge. Therefore, a transistor including an oxide semiconductor film having a high impurity concentration and a high density of defect states might have unstable electric characteristics.

Next, the amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor film in which atomic arrangement in the film is irregular and which does not have a crystal part. An example is an oxide semiconductor film having an amorphous state such as quartz.

In the high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found.

Structural analysis of the amorphous oxide semiconductor film using an XRD apparatus revealed that out-of-
In the analysis by the plane method, the peak indicating the crystal plane is not detected. In addition, a halo pattern is observed when electron diffraction is performed on the amorphous oxide semiconductor film. When nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration.
The amorphous oxide semiconductor film is an oxide semiconductor film having a high density of defect states.

An oxide semiconductor film having a high impurity concentration and a high density of defect states has many carrier traps and carrier generation sources.

Therefore, the carrier density of the amorphous oxide semiconductor film may be higher than that of the nc-OS film. Therefore, a transistor including an amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electric characteristics. The amorphous oxide semiconductor film has a high density of defect states and thus has a large number of carrier traps in some cases. Therefore, a transistor including an amorphous oxide semiconductor film is different from a transistor including a CAAC-OS film or an nc-OS film in
The transistor has a large variation in electrical characteristics and low reliability.

Next, the single crystal oxide semiconductor film will be described.

The single crystal oxide semiconductor film is an oxide semiconductor film having a low impurity concentration and a low density of defect states (small oxygen vacancies). Therefore, the carrier density can be lowered. Therefore, a transistor including a single crystal oxide semiconductor film rarely has normally-on electrical characteristics. Further, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, carrier traps may be reduced in some cases. Therefore, a transistor including a single crystal oxide semiconductor film has low variation in electric characteristics and high reliability.

Note that the oxide semiconductor film has high density when there are few defects. In addition, the oxide semiconductor film is
The higher the crystallinity, the higher the density. In addition, the density of the oxide semiconductor film is high when the concentration of impurities such as hydrogen is low. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. In addition, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. In addition, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. In addition, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. In particular, an oxide-semiconductor film having such a structure is used as an amorphous-like oxide semiconductor (amorphous-like oxide semiconductor).
: A-like OS) film.

In the high-resolution TEM image of the a-like OS film, a void may be observed. Further, in the high-resolution TEM image, there is a region where a crystal part can be clearly confirmed and a region where a crystal part cannot be confirmed. The a-like OS film may be crystallized by the irradiation of a small amount of electrons as observed with a TEM, and growth of a crystal part may be observed. On the other hand, in the case of a good quality nc-OS film, almost no crystallization due to a small amount of electron irradiation as observed by TEM is observed.

Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, a crystal of InGaZnO ₄ has a layered structure and includes two Ga—Zn—O layers between In—O layers. The unit cell of the InGaZnO ₄ crystal has a structure in which three layers of In—O layers and six layers of Ga—Zn—O layers, nine layers in total, are layered in the c-axis direction. Therefore, the distance between these adjacent layers is about the same as the lattice distance (also referred to as d value) of the (009) plane, and the value is 0.29 n from crystal structure analysis.
m is required. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe is In when the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less.
It was considered to correspond to the ab plane of the GaZnO ₄ crystal. The maximum length in the region where the lattice fringes are observed is the size of the crystal part of the a-like OS film and the nc-OS film. The size of the crystal part is 0.8 nm or more, and is selectively evaluated.

Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.

Note that a single crystal having the same composition may not exist. In that case, by combining single crystals having different compositions at an arbitrary ratio, the density corresponding to a single crystal having a desired composition can be estimated. The density corresponding to a single crystal having a desired composition may be estimated using a weighted average with respect to a ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

Note that the oxide semiconductor film may be, for example, a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. ..

[Nanobeam electron diffraction]
Next, nanobeam electron diffraction will be described.

When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nanobeam electron diffraction.

FIG. 7C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 61.
2 under the sample chamber 614, an optical system 616 under the sample chamber 614, an observation chamber 620 under the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber under the observation chamber 620. 622, and a transmission electron diffraction measuring apparatus having 622. The camera 618 is installed toward the inside of the observation room 620. Note that the film chamber 622 may not be provided.

Further, FIG. 7D shows the internal structure of the transmission electron diffraction measuring apparatus shown in FIG. 7C. In the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in the electron gun chamber 610 are irradiated onto the substance 628 arranged in the sample chamber 614 via the optical system 612. Substance 628
The electrons that have passed through enter the fluorescent plate 632 installed inside the observation chamber 620 via the optical system 616. On the fluorescent plate 632, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of the incident electrons.

The camera 618 is installed so as to face the fluorescent plate 632, and it is possible to take an image of the pattern appearing on the fluorescent plate 632. The angle formed by the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70°. Below. The smaller the angle, the larger the distortion of the transmission electron diffraction pattern taken by the camera 618. However, if the angle is known in advance, it is possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 618 may be installed in the film chamber 622 in some cases. For example, the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 632.

In the sample chamber 614, a holder for fixing a substance 628 which is a sample is installed.
The holder has a structure that allows electrons passing through the substance 628 to pass through. The holder may have a function of moving the substance 628 along the X axis, the Y axis, the Z axis, or the like, for example. The movement function of the holder may be, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm. These ranges may be set to optimum ranges depending on the structure of the substance 628.

Next, a method of measuring a transmission electron diffraction pattern of a substance using the above-mentioned transmission electron diffraction measuring device will be described.

For example, as shown in FIG. 7D, by changing (scanning) the irradiation position of the electron 624 which is a nanobeam in the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 7B is observed. Alternatively, when the substance 628 is an nc-OS film, a diffraction pattern as shown in FIG. 7A, for example, a diffraction pattern having a plurality of bright spots arranged in a circle (a ring with bright spots) Diffraction pattern) is observed. The diffraction pattern shown in FIG. 7A has bright points that are not symmetrically arranged (have no symmetry).

As shown in FIG. 7B, in the diffraction pattern of the CAAC-OS film, for example, a spot located at the top of a hexagon is confirmed. In the CAAC-OS film, by scanning the irradiation position, the orientation of this hexagon is not uniform, but it appears that the hexagon is gradually rotating. Also, the angle of rotation has a certain width.

Alternatively, in the diffraction pattern of the CAAC-OS film, by scanning the irradiation position,
It can be seen that it rotates little by little around the c-axis. It can be said that, for example, the surface formed by the a-axis and the b-axis is rotating.

By the way, a region where the substance 628 has a diffraction pattern similar to that of the CAAC-OS film (hereinafter referred to as a region having a CAAC structure) and a region where a diffraction pattern similar to that of the nc-OS film is observed (hereinafter, nc structure). And a region having a). Here, the ratio of the region where the diffraction pattern of the CAAC-OS film is observed in a certain range is the CAAC ratio (
Also referred to as CAAC conversion rate. ) Can be represented. Similarly, the ratio of the region where a diffraction pattern similar to that of the nc-OS film is observed can be represented by an nc ratio (also referred to as an nc conversion ratio).

The method for evaluating the CAAC ratio of the CAAC-OS film will be described below. Measurement points are randomly selected, transmission electron diffraction patterns are acquired, and the ratio of the number of measurement points at which the diffraction pattern of the CAAC-OS film is observed to the total number of measurement points is calculated. Here, the number of measurement points is preferably 50 or more, more preferably 100 or more.

As a method of randomly selecting the measurement points, for example, the irradiation position may be scanned linearly and a diffraction pattern may be acquired at regular intervals. CAAC by scanning the irradiation position
This is preferable because the boundary between the structured region and other regions can be confirmed. Note that nc
Similarly, the conversion ratio can be calculated by randomly selecting measurement points, acquiring a transmission electron diffraction pattern, and calculating the transmission electron diffraction pattern.

When such a measuring method is used, it may be possible to analyze the structure of the oxide semiconductor film having a plurality of structures.

In the oxide semiconductor film which is one embodiment of the present invention, for example, the sum of the nc ratio and the CAAC ratio is 80%.
Or more, preferably 90% or more and 100% or less, more preferably 95% or more and 100% or less, and preferably 98% or more and 100% or less, 9
It is more preferably 9% or more and 100% or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film with few clear grain boundaries can be realized. By reducing the number of clear grain boundaries, carrier mobility of the oxide semiconductor film can be increased, for example.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, an example of the oxide semiconductor film which is one embodiment of the present invention will be described.

In some cases, the nc-OS film can be formed at a relatively low film formation temperature as compared with the CAAC-OS film. For example, it may be formed without heating the substrate. Therefore, a semiconductor device including a transistor including an nc-OS film can be manufactured with high productivity in some cases.

Further, since the nc-OS film has appropriate oxygen permeability, oxygen is likely to diffuse throughout the film, and oxygen vacancies can be more easily reduced. Therefore, an oxide semiconductor film with low defect density can be realized in some cases. Therefore, the characteristics of the semiconductor device including the transistor including the nc-OS film can be improved in some cases. In addition, reliability may be improved in some cases.

Here, the nc-OS film and the CAAC-OS film both have a layered atomic arrangement. Such a layered atomic arrangement can be observed using, for example, TEM.

Here, spherical aberration correction (Spherical) is performed for the nc-OS film and the CAAC film.
Transmission electron microscopy (TEM: Aberration Corrector) function.
An image (also referred to as a TEM image) obtained by the Transmission Electron Microscopy is observed. A composite analysis image of a bright field image and a diffraction pattern obtained by TEM observation is called a high resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is called a Cs-corrected high-resolution TEM image. In addition, Cs correction high resolution TEM
The image is acquired, for example, by the atomic resolution analytical electron microscope JEM-ARM20 manufactured by JEOL Ltd.
It can be performed by 0F or the like.

In CAAC-OS and nc-OS, the size and orientation of crystals are investigated by analyzing the Cs-corrected high-resolution cross-sectional TEM image in more detail. Below, the crystal part of nc-OS may be called a pellet. As for the crystal size and orientation, pellets are extracted in a range of 20 nm square or more in a cross-sectional TEM image, and the size and orientation are investigated.

Note that FIG. 17A is a Cs-corrected high-resolution cross-sectional TEM image of the CAAC-OS. 17B is a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS. Note that the left and right figures are observations of the same place, and the right figure shows an auxiliary line indicating pellets.

FIG. 18A is a cross-sectional TEM image of a CAAC-OS formed by a DC sputtering method. Further, FIG. 18B is a Cs-corrected high-resolution cross-sectional TEM image of which a part is enlarged.
In FIG. 18B, the number of pellets is counted, and the size and direction of the pellets are frequency-distributed (see FIG. 22A). Here, the arrow shown in FIG. 18A indicates a direction perpendicular to the sample surface. In addition, the direction of the white line shown in FIG. 18B indicates the direction of the pellet, and the length of the white line indicates the size of the pellet.

FIG. 19A is a cross-sectional TEM image of a CAAC-OS formed by an RF sputtering method. In addition, FIG. 19B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged.
In FIG. 19B, the number of pellets is counted, and the size and direction of the pellets are frequency-distributed (see FIG. 22B).

FIG. 20A is a cross-sectional TEM image of the nc-OS formed by a DC sputtering method.
In addition, FIG. 20B is a Cs-corrected high-resolution cross-sectional TEM image of which part is enlarged. Figure 2
At 0 (B), the number of pellets is counted, and the size and direction of the pellets are frequency-distributed (see FIG. 22C).

FIG. 21A is a cross-sectional TEM image of the nc-OS formed by an RF sputtering method.
In addition, FIG. 21B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged. Figure 2
In 1(B), the number of pellets is counted, and the size and direction of the pellets are frequency-distributed (see FIG. 22D).

The table below shows the results obtained by summarizing FIG. Here, the orientation of the pellet indicates the absolute value of the angle with respect to the sample surface.

The nc-OS preferably has pellets with a size of preferably 0.5 nm or more and 3 nm or less, more preferably 1 nm or more and 3 nm or less. In the nc-OS,
It can be seen that the orientation of the pellets is oriented in the direction perpendicular to the sample surface by the RF sputtering method as compared with the DC sputtering method. Here, the ratio of the orientation of the nc-OS pellets to the sample surface is 0° or more and less than 30°, for example, preferably 0% or more and 70% or less, and the ratio of 30° or more and less than 60° is 10 % Or more and 60% or less, and the ratio of 60° or more and less than 90° is preferably 0% or more and 60% or less. nc-OS is CAAC-OS
It can be seen that the orientation of the pellets is random compared to.

The oxide semiconductor film having such pellets can be described with the following film formation model, for example.

[Deposition model]
Below, the film-forming model of nc-OS is demonstrated.

FIG. 24 is a schematic diagram of the inside of the film forming chamber showing a state in which the nc-OS is formed by the sputtering method.

The target 5130 is adhered on the backing plate. Target 5130
A plurality of magnets are arranged under the backing plate. A magnetic field is generated on the target 5130 by the plurality of magnets. A sputtering method that uses a magnetic field of a magnet to increase the film formation rate is called a magnetron sputtering method.

The target 5130 has a polycrystalline structure, and one of the crystal grains includes a cleavage plane.
The details of the cleavage plane will be described later.

The substrate 5120 is arranged so as to face the target 5130, and its distance d(
It is also called the target-substrate distance (T-S distance). ) Is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. Most of the film forming chamber has a film forming gas (for example,
Oxygen, argon, or a mixed gas containing 50% by volume or more of oxygen) and 0.
It is controlled to be 01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage of a certain level or higher to the target 5130, discharge starts and plasma is confirmed. Note that a high-density plasma region is formed by the magnetic field on the target 5130. In the high-density plasma region, the film formation gas is ionized to generate ions 5101. The ion 5101 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar
⁺ ) and so on.

The ions 5101 are accelerated toward the target 5130 side by the electric field and eventually collide with the target 5130. At this time, the pellets 5100a and 5100b, which are flat-plate-like or pellet-like sputtered particles, are peeled off from the cleavage plane and are knocked out. Note that the structures of the pellets 5100a and 5100b may be distorted by the impact of the collision of the ions 5101.

The pellet 5100a is a flat-plate-like or pellet-like sputtered particle having a triangular, for example, equilateral triangular flat surface. The pellet 5100b is a flat-plate-like or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. Note that flat plate-like or pellet-like sputtered particles such as the pellets 5100a and 5100b are collectively referred to as pellets. The shape of the plane of the pellet is not limited to a triangle or a hexagon.
The shape may be a combination of not less than 6 and not more than 6. For example, it may be a quadrangle formed by combining two equilateral triangles.

The thickness of the pellet is determined according to the type of film forming gas. The thickness of the pellets is preferably uniform. Further, it is preferable that the sputtered particles are in the form of pellets having a small thickness, rather than in the form of dice having a large thickness.

The pellet may be negatively or positively charged on the side surface by receiving an electric charge when passing through the plasma. The pellet has an oxygen atom on the side surface, and the oxygen atom may be negatively charged.

As shown in FIG. 24, for example, the pellets fly in the plasma like a kite and flutter up to the substrate 5120. Since the pellets are charged, a repulsive force is generated when the area where another pellet is already deposited approaches. Here, on the upper surface of the substrate 5120, a magnetic field oriented parallel to the upper surface of the substrate 5120 is generated. Further, since a potential difference is applied between the substrate 5120 and the target 5130,
An electric current is flowing toward 130. Therefore, the pellet receives a force (Lorentz force) on the upper surface of the substrate 5120 by the action of the magnetic field and the electric current. Note that in order to increase the force applied to the pellet, the magnetic field on the upper surface of the substrate 5120 in a direction parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, further preferably 30 G or more, and more preferably 50 G or more. It is advisable to provide the area. Alternatively, on the upper surface of the substrate 5120, the magnetic field in a direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more of the magnetic field in a direction perpendicular to the upper surface of the substrate 5120. More preferably, it is preferable to provide a region that is 5 times or more.

It is considered that the pellets are deposited on the substrate 5120 according to the above model.
Therefore, unlike the epitaxial growth, it can be seen that the nc-OS film can be formed even when the surface to be formed does not have a crystal structure. For example, even if the structure of the upper surface (formation surface) of the substrate 5120 is an amorphous structure, the nc-OS can be deposited.

Since the nc-OS is formed by such a model, it is preferable that the sputtered particles are in the form of pellets having no thickness. If the sputtered particles are thick dice,
In some cases, the surface of the sputtered particles facing the substrate 5120 is not constant, and the thickness and crystal orientation cannot be uniform.

Further, when the substrate 5120 is heated, the resistance such as friction between the pellet and the substrate 5120 is smaller. As a result, the pellet moves so as to glide over the upper surface of the substrate 5120. The movement of the pellets occurs with the flat plate surface of the pellets facing the substrate 5120. After that, when reaching the side surface of another pellet 5100 which has already been deposited, the side surfaces are bonded to each other and a CAAC-OS film is obtained.

When the substrate 5120 is not heated, the resistance such as friction between the pellet and the substrate 5120 is higher. As a result, it is difficult for the pellets to move so as to glide over the upper surface of the substrate 5120, and the nc-OS can be obtained by randomly depositing.

The CAAC-OS heats the substrate 5120 to form a film, whereas the nc-OS uses the substrate 51.
Film formation is possible without heating 20.

In addition, as shown in FIG. 25, for example, the atmosphere in the chamber is preferably room temperature or above 500
The heating may be performed at a temperature of not higher than 0°C, more preferably not lower than 200°C and not higher than 400°C. A lamp 5140 such as a halogen lamp may be used for heating the atmosphere. By heating the atmosphere, for example, pellets flying in the chamber are heated, and defects may be reduced. In addition, the pellet size may increase. Further, by heating the atmosphere, for example, water in the chamber is easily evaporated, and the degree of vacuum can be further increased.

[Cleave plane]
Hereinafter, the cleavage plane of the target described in the film formation model of the nc-OS will be described.

First, the cleavage plane of the target will be described with reference to FIG. InGaZ
₃ shows a crystal structure of nO ₄ . Note that FIG. 10A illustrates a structure in which a crystal of InGaZnO ₄ is observed from a direction parallel to the b axis with the c axis facing upward. In addition, FIG.
The structure when observing a crystal of InGaZnO ₄ from a direction parallel to the axis is shown.

The energy required for cleavage at each crystal plane of the InGaZnO ₄ crystal is calculated by the first principle calculation. In addition, a pseudo-potential and a density functional program (CASTEP) using a plane wave basis are used for the calculation. An ultra-soft type pseudopotential is used as the pseudopotential. Further, GGA PBE is used as the functional. The cutoff energy is 400 eV.

The energy of the structure in the initial state is derived after performing the structure optimization including the cell size. The energy of the structure after cleavage on each surface is derived after the structural optimization of atomic arrangement is performed with the cell size fixed.

Based on the structure of the InGaZnO ₄ crystal shown in FIG. 10, a structure in which a cleavage is formed on any of the first surface, the second surface, the third surface, and the fourth surface is manufactured, and the cell size is fixed. Perform the optimized structure optimization. Here, the first plane is a crystal plane between the Ga—Zn—O layer and the In—O layer, and (
This is a crystal plane parallel to the (001) plane (or the ab plane) (see FIG. 10A). The second plane is a crystal plane between the Ga—Zn—O layer and the Ga—Zn—O layer, and is the (001) plane (or a
The crystal plane is parallel to the (b-plane) (see FIG. 10A). The third plane is a crystal plane parallel to the (110) plane (see FIG. 10B). The fourth plane is a crystal plane parallel to the (100) plane (or the bc plane) (see FIG. 10B).

Under the above conditions, the energy of the structure after cleavage on each surface is calculated. Next, the difference between the energy of the structure after cleavage and the energy of the structure in the initial state is divided by the area of the cleavage plane to calculate the cleavage energy, which is a measure of the ease of cleavage on each plane. Note that the energy of a structure is energy that takes into account the kinetic energy of electrons and the interaction between atoms, between atoms and electrons, and between electrons with respect to atoms and electrons included in the structure.

As a result of the calculation, the cleavage energy of the first surface is 2.60 J/m ² , the cleavage energy of the second surface is 0.68 J/m ² , and the cleavage energy of the third surface is 2.18 J/m ² . It was found that the cleavage energy of the surface of No. 4 was 2.12 J/m ² (see the table below).

According to this calculation, in the structure of the InGaZnO ₄ crystal shown in FIG. 10, the cleavage energy on the second surface becomes the lowest. That is, it can be seen that the surface between the Ga—Zn—O layer and the Ga—Zn—O layer is the most easily cleaved surface (cleavage surface). Therefore, in this specification, the term “cleavage surface” refers to the second surface which is the most easily cleaved surface.

Since the second plane between the Ga—Zn—O layer and the Ga—Zn—O layer has a cleavage plane, the InGaZnO ₄ crystal shown in FIG. 10A is equivalent to the two second planes. Can be separated in various ways. Therefore, when the target is bombarded with ions or the like, it is considered that the wafer-like unit cleaved at the surface having the lowest cleavage energy (this is called a pellet) comes out as the minimum unit. In that case, the InGaZnO ₄ pellet has three layers of a Ga—Zn—O layer, an In—O layer, and a Ga—Zn—O layer.

Further, the third plane (the crystal plane between the Ga—Zn—O layer and the In—O layer, which is parallel to the (001) plane (or the ab plane)) is the third plane ( Since the cleavage energy of the crystal plane parallel to the (110) plane) and the fourth plane (the crystal plane parallel to the (100) plane (or bc plane)) is low, the planar shape of the pellet is often triangular or hexagonal. Is suggested.

[Film density]
Next, the density of the In-M-Zn oxide film was evaluated. In:Ga:Zn as a target
=1:1:1 using a polycrystalline In-Ga-Zn oxide by a DC sputtering method.
The OS was deposited. The pressure is 0.4 Pa, the film forming temperature is room temperature, the power supply is 100 W, and argon and oxygen are used as the film forming gas. The flow rates of argon and oxygen are 98 sccm and 2 oxygen, respectively.
It was set to sccm. The density of the obtained In-Ga-Zn oxide was 6.1 g/cm ³ . Here, according to Non-Patent Document 2, the density of single-crystal InGaZnO ₄ is 6.357 g/cm ^3.
Is. In addition, JCPDS card, No. As described in 00-038-1097, the density of single crystal In ₂ Ga ₂ ZnO ₇ is known to be 6.494 g/cm ³ . Therefore, it is found that the obtained nc-OS film is an excellent film having high density.

The density of the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention is, for example, preferably 85% or more, more preferably 90% or more of the density of a single crystal having approximately the same atomic ratio. 95% or more is more preferable.

Alternatively, when the element M is gallium, the density of the oxide semiconductor film which is one embodiment of the present invention is
For example 5.7 g / cm ³ or more 6.49 g / cm ³ or less, preferably 5.75 g / cm ³ or more 6.49 g / cm ³ or less, 5.8 g / cm ³ or more 6.33 g / cm ³ or less It is more preferably 5.85 g/cm ³ or more and 6.33 g/cm ³ or less.

Here, the atom number ratios that are substantially the same indicate that the difference in the atom number ratios possessed by each other is within 10%.

Here, for example, the density of a single crystal is two or more In-M-Zn having different atomic ratios.
It may be estimated from the density of the oxide film. Here, the density of a single crystal having an atomic ratio of In:M:Zn=1:1:1 is D ₁ , and the density of a single crystal having an atomic ratio of In:M:Zn=2:2:1 is D. _Set to ₂ . In-M- in which the atomic ratio of indium, element M and zinc is 1:1:0.8.
The density of the Zn oxide film is expected to take a value between D ₁ and D ₂ . Therefore, as the density of the single crystal, for example, an average value of D ₁ and D ₂ may be calculated and referred to, or a value of either D ₁ or D ₂ , for example, a value having a closer atomic number ratio may be referred to. Good. When the average value is calculated using D ₁ and D ₂ , it may be 0.6×D ₁ +0.4×D ₂ , for example. The atomic ratio is In:M:Z
The density of a single crystal with n=A:B:C is D _α , and the density of a single crystal with an atomic ratio of In:M:Zn=D:E:F is D _β . The density of a single crystal whose atomic ratio is In:M:Zn=X:Y:Z may be calculated as follows, for example.

First, α is set so that (αA+βD):(αB+βE):(αC+βF)=X:Y:Z.
And β are obtained. Next, using the obtained α and β, the density of the single crystal is calculated as {α/(α+β)}D _α
It may be calculated as +{β/(α+β)}D _β .

Next, an example of a method for manufacturing the nc-OS film will be described.

As a general method for forming an oxide semiconductor film, for example, a sputtering method, a chemical vapor deposition (CVD) method (a metal organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, or plasma chemistry) is used. A vapor phase deposition (including PECVD) method, a vacuum vapor deposition method, a pulse laser deposition (PLD) method and the like can be mentioned.

The nc-OS film is preferably formed by a sputtering method. As a target used for a sputtering method, an In-M-Zn oxide can be used.

Further, the target preferably has a polycrystalline In-M-Zn oxide. For example, when a target including a polycrystalline In-M-Zn oxide is used, the target has a cleavage property and an nc-OS film may be easily formed, which is more preferable.

An In-M-Zn oxide can be manufactured using a mixture of indium oxide, an oxide containing the element M, and zinc oxide as a target in some cases, but a target having a polycrystalline In-M-Zn oxide is used. It is preferable to use.

In addition, the nc-OS film is preferably formed in some cases at room temperature. For example, it may be formed without heating the substrate, which is preferable. Further, for example, the atmosphere in the chamber may be heated preferably at room temperature or higher and 500° C. or lower, and more preferably 200° C. or higher and 400° C. or lower.

[About the ratio of the number of atoms]
Here, for example, an In-M-Zn oxide film is preferably used as the oxide semiconductor film which is one embodiment of the present invention. The atomic ratio of In, M and Zn contained in the In-M-Zn oxide is I
n:M:Zn=x:y:z.

The In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention preferably has a high proportion of indium, for example.

In addition, it is preferable that the number of grain boundaries in the oxide semiconductor film is smaller. Examples of the non-single-crystal oxide semiconductor film having few grain boundaries include an nc-OS film and a CAAC-OS film. Further, the oxide semiconductor film may include both the nc-OS film and the CAAC-OS film.

In addition, the oxide semiconductor film which is one embodiment of the present invention, when subjected to nanobeam electron diffraction,
It is preferable to have a region (nc structure) in which the diffraction pattern of the nc-OS film is observed. The oxide semiconductor film which is one embodiment of the present invention includes a region where a diffraction pattern of the nc-OS film is observed and a region where a diffraction pattern of the CAAC-OS film is observed (CAAC structure). May be.

The oxide semiconductor film which is one embodiment of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. In the oxide semiconductor film which is one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or higher, more preferably 90% or higher and 100% or lower.
It is preferably 5% or more and 100% or less, more preferably 98% or more and 100% or less, and even more preferably 99% or more and 100% or less.

For the oxide semiconductor film which is one embodiment of the present invention, a plurality of films may be stacked. Further, the nc ratio and the CAAC ratio of each of the plurality of films may be different. Moreover, it is preferable that at least one layer of the plurality of stacked layers has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. In addition, the sum of the nc ratio and the CAAC ratio of at least one of the laminated films is preferably 80% or more, more preferably 90% or more and 100% or less, and 95% or more 1.
It is preferably not more than 00%, more preferably not less than 98% and not more than 100%,
% Or more and 100% or less is more preferable.

As shown in FIG. 6, powders of In ₂ O ₃ , Ga ₂ O ₃ and ZnO were mixed, and 1350
Non-Patent Document 1 describes that the solid solution region becomes wider by increasing the proportion of zinc when firing at ℃. Here, when the atomic ratio of the In—Ga—Zn oxide is within a range where a solid solution region can be obtained, the CAAC ratio of the oxide semiconductor film of one embodiment of the present invention may be higher. Therefore, in some cases, by reducing the proportion of zinc, the nc proportion of the oxide semiconductor film of one embodiment of the present invention can be increased. The atomic ratio of indium, element M, and zinc contained in the oxide semiconductor film is set to indium:element M:zinc=x:y:z. For example, it may be possible to further increase the nc ratio by increasing the ratio of x+y to z, that is, (x+y)/z. Specifically, for example, (x+y)>z is preferable, and (x+y)
y)≧1.5z is preferable, and (x+y)≧2z is preferable.

In addition, by mixing the crystal of the spinel structure with the CAAC-OS film or the nc-OS film,
In some cases, clear grain boundaries or boundaries may be formed. Therefore, it is preferable to keep away from the atomic ratio in which crystals with a spinel structure are more likely to be formed.

Therefore, In included in the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention
, The atomic number ratios x, y, and z of the element M and zinc preferably have the ratio of the number of atoms in the region 13 shown in FIG. 4A, and the ratio of the number of atoms in the region 14 shown in FIG. 4B. It is more preferable to have Here, the region 13 has a first coordinate K (x:y:z=8:14:7) and a second coordinate R.
(X:y:z=2:4:3), the third coordinate V(x:y:z=1:2:3), and the fourth coordinate S(x:y:z=1:0). :1), the fifth coordinate T (x:y:z=8:0:1), and the sixth coordinate
U (x:y:z=6:2:1) and the first coordinate K are sequentially connected by a line segment. The area 13 includes a line segment connecting six points. The area 13 includes all coordinates. In addition, the region 14 has a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate. V(x:y:z=1:2:3), the fourth coordinate W(x:y:z=7:1:8), and the fifth coordinate X(x:y:z=7: 1:1), the sixth coordinate U (x:y:z=6:2:1), and the first coordinate K are sequentially connected by a line segment. The area 14 includes a line segment connecting six points. Further, the area 14 includes all coordinates.

In addition, when the oxide semiconductor film is formed by a sputtering method, the atomic ratio of the obtained film is
It may deviate from the target atomic ratio. In particular, in the case of zinc, the ratio of zinc in the obtained film may be smaller than the ratio of zinc in the target. Specifically, the ratio of zinc in the obtained film may be, for example, 40 atomic% or more and 90 atomic% or less of the target zinc ratio.

Here, when forming an In-Ga-Zn oxide by a sputtering method, the relation between the atomic ratio of the target used and the atomic ratio of the obtained film was examined.

As film forming conditions, argon and oxygen were used as a film forming gas, and the oxygen flow rate ratio was 33%. Here, the oxygen flow rate ratio is an amount represented by oxygen flow rate/(oxygen flow rate+argon flow rate)×100[%]. The pressure was in the range of 0.4 Pa to 0.7 Pa, the substrate temperature was 200° C. to 300° C., and the power supply power was 0.5 kW (DC).

FIG. 23 shows the relationship between the ratio of the atomic number ratio and the residual zinc ratio when focusing on the two target elements. The numbers in the figure represent the target In:Ga:Zn atomic ratio. Here, the residual rate of zinc will be described. A value obtained by dividing the value of the term of zinc in the atomic ratio of the obtained film by the sum of the values of the terms of indium, gallium, and zinc of the film is Zn(Film). Further, a value obtained by dividing the value of the term of zinc in the atomic ratio of the target by the sum of the values of the terms of indium, gallium, and zinc of the target is Zn(Target). Here, the residual rate of zinc is defined as a value represented by A=Zn(Film)÷Zn(Target)×100[%].

Further, the atomic ratio of indium, gallium, and zinc of the In-Ga-Zn oxide target used is represented as a:b:c.

FIG. 23A shows the value (c/b) of the ratio of zinc to gallium of the target on the horizontal axis.
3(B) is the value of the ratio of gallium to the target atomic ratio of indium (b/a) on the horizontal axis.
23C, the horizontal axis shows the value of the ratio of zinc to indium of the target (c/a). Further, each vertical axis represents the zinc residual ratio A.

Here, from FIG. 23, the residual rate of zinc of the film obtained by the sputtering method is about 5
It can be seen that it is 0% or more and 90% or less. Further, it can be said that indium and gallium do not change significantly from the atomic ratio of the target as compared with zinc. Further, when the value of the ratio of zinc to gallium (c/b) of the target is 1, the residual ratio A of zinc is about 66%,
In the case of 2, it is about 74%, and in the case of 3, it is about 83%.

Further, FIG. 23A shows that there is a good correlation between the value of the ratio of zinc to gallium (c/b) as the target and the residual ratio of zinc. That is, the smaller the zinc content relative to the gallium content, the lower the residual rate.

In view of the above, in order to obtain the oxide semiconductor film in the region 13 illustrated in FIG. 4A by a sputtering method, for example, the value of the ratio of zinc of the target film to the value of the ratio of zinc of the target film Is preferably 1.7 times or more, more preferably 1.5 times or more. Therefore, it is preferable that the target indium, gallium, and zinc have the atomic ratio of the region 15 shown in FIG. Here, the region 15 has a first coordinate K (a:b:c=8:14:7) and a second coordinate R(a
:B:c=2:4:3), the third coordinate Y (a:b:c=1:2:5.1), and the fourth coordinate Z (a:b:c=1:0). : 1.7) and the fifth coordinate T (a:b:c=8:0:1),
It is within a region in which the sixth coordinate U (a:b:c=6:2:1) and the first coordinate K are sequentially connected by a line segment. The area 15 includes a line segment connecting six points. Region 15 contains all coordinates.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, an example of a transistor including an oxide semiconductor film which is one embodiment of the present invention will be described.

[Example 1 of transistor]
An example of a transistor including an oxide semiconductor film is described with reference to FIG.

FIG. 12A shows a top view of the transistor 100. In addition, FIG.
12C shows a cross section taken along one-dot chain line XX', and FIG. 12C shows a cross section taken along one-dot chain line YY'. The transistor 100 illustrated in FIG. 12 includes a substrate 50, an insulating film 51 in contact with an upper surface of the substrate 50, an insulating film 114 in contact with an upper surface of the insulating film 51, a semiconductor layer 101 in contact with an upper surface of the insulating film 114, and a conductive layer 104a. A conductive layer 104b, a gate insulating film 102 over the semiconductor layer 101, a gate electrode 103 overlapping with the semiconductor layer 101 with the gate insulating film 102 interposed therebetween,
Have. Further, an insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100. The transistor 100 may also include the conductive layer 105. Further, the insulating film may not be provided between the substrate 50 and the insulating film 114.

The semiconductor layer 101 may be formed as a single layer, and is more preferably formed as a stacked structure of the first layer to the third layer. The second layer is provided in contact with the first layer and the third layer is provided in contact with the second layer. Here, in the transistor of one embodiment of the present invention, the first layer and the third layer each have a region in which a current hardly flows as compared with the second layer. Therefore, the first layer and the third layer may be referred to as insulator layers. Therefore, as in the example shown in FIG.
Is preferably formed in a stacked structure of an insulating layer 101a, a semiconductor layer 101b, and an insulating layer 101c. In addition, the structure may not include any of the insulator layer 101a and the insulator layer 101c. In the example shown in FIG. 12, the semiconductor layer 101b is the insulator layer 101.
It contacts the upper surface of a. In addition, the conductive layers 104a and 104b are in contact with the top surface of the semiconductor layer 101b and are separated in a region overlapping with the semiconductor layer 101b. The insulator layer 101c is in contact with the top surface of the semiconductor layer 101b. The gate insulating film 102 is in contact with the top surface of the insulator layer 101c. The gate electrode 103 overlaps with the semiconductor layer 101b with the gate insulating film 102 and the insulating layer 101c interposed therebetween.

Further, an insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100.
Details of the insulating film 112 and the insulating film 113 will be described later in an embodiment.

The conductive layers 104a and 104b function as a source electrode or a drain electrode. Alternatively, a voltage lower than or higher than that of the source electrode may be applied to the conductive layer 105 to change the threshold voltage of the transistor in the positive direction or the negative direction. By changing the threshold voltage of the transistor in the positive direction, there is a case where normally-off in which the transistor is in a non-conducting state (off state) even when the gate voltage is 0 V can be realized. Note that the voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage may be connected to the conductive layer 105. The conductive layer 105 may be connected to the gate electrode 103.

The upper surface of the insulating film 114 has a CMP (Chemical Mechanical Polis).
Hing) method or the like is preferably used for flattening.

The insulating film 114 preferably contains an oxide. In particular, it is preferable to include an oxide material from which part of oxygen is released by heating. It is preferable to use an oxide containing more oxygen than that satisfying the stoichiometric composition. A part of oxygen is desorbed by heating in an oxide film containing oxygen in an amount larger than that in the stoichiometric composition. Oxygen desorbed from the insulating film 114 is supplied to the semiconductor layer 101 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electric characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than the stoichiometric composition has a desorption amount of oxygen in terms of oxygen atoms, for example, by thermal desorption gas spectroscopy analysis (TDS analysis). 1.0 x 10 ^1
The oxide film has a thickness of ⁸ atoms/cm ³ or more, preferably 3.0×10 ²⁰ atoms/cm ³ or more. The surface temperature of the film during the TDS analysis is 100° C. or higher 7
The temperature is preferably 00°C or lower, or 100°C or higher and 500°C or lower.

For example, a material containing silicon oxide or silicon oxynitride is preferably used as such a material. Alternatively, a metal oxide can be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. Note that in this specification, silicon oxynitride refers to a material whose content of oxygen is higher than that of nitrogen as its composition, and silicon oxynitride is a material whose content of nitrogen is higher than that of oxygen as its composition. Indicates.

In order to make the insulating film 114 contain excess oxygen, oxygen may be introduced into the insulating film 114 to form a region containing excess oxygen. For example, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after the film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

The semiconductor layer 101 includes an oxide semiconductor. As the oxide semiconductor, it is preferable to use a semiconductor material having a wider bandgap and a smaller carrier density than silicon because the current in the off state of the transistor can be reduced. In addition, since the semiconductor layer 101 includes an oxide semiconductor, fluctuations in electrical characteristics are suppressed and a highly reliable transistor can be realized.

Here, as the semiconductor layer 101, for example, the oxide semiconductor described in Embodiment 1 or 2 can be used.

Note that in this specification and the like, when substantially referred to as intrinsic, the carrier density of the oxide semiconductor layer is less than 1×10 ¹⁷ /cm ^3, less than 1×10 ¹⁵ /cm ³ , or 1×10 ¹³ /cm ^3.
Is less than. By making the oxide semiconductor layer highly purified and intrinsic, stable electrical characteristics can be given to the transistor.

Here, a case where a stacked film of an insulating layer 101a, a semiconductor layer 101b, and an insulating layer 101c is used as the semiconductor layer 101 is described in detail. For the semiconductor layer 101b, it is preferable to use an oxide having an electron affinity higher than those of the insulator layers 101a and 101c. For example, as the semiconductor layer 101b, an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more. An oxide larger than 4 eV is used. The electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

When an oxide having an electron affinity higher than those of the insulator layers 101a and 101c is used for the semiconductor layer 101b and an electric field is applied to the gate electrode, the insulator layers 101a,
A channel is formed in the semiconductor layer 101b having a large electron affinity among the semiconductor layer 101b and the insulator layer 101c. Here, by forming a channel in the semiconductor layer 101b, for example, the channel formation region is separated from the interface with the gate insulating film 102, so that the influence of scattering at the interface with the gate insulating film can be reduced. Therefore, the field-effect mobility of the transistor can be increased. Here, since the semiconductor layer 101b and the insulator layer 101c have the same constituent elements as described later, interface scattering hardly occurs.

In the case where a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or the like is used for the gate insulating film, silicon contained in the gate insulating film might be mixed in the oxide semiconductor film. When silicon is contained in the oxide semiconductor film, crystallinity of the oxide semiconductor film, carrier mobility, or the like might be reduced. Therefore, in order to reduce the impurity concentration of the semiconductor layer 101b in which the channel is formed, for example, the silicon concentration, the semiconductor layer 10 is reduced.
An insulator layer 101c is preferably provided between 1b and the gate insulating film. For the same reason, it is preferable to provide the insulator layer 101a between the semiconductor layer 101b and the insulating film 114 in order to reduce the influence of impurity diffusion from the insulating film 114.

As the semiconductor layer 101b, for example, an oxide semiconductor film containing indium, the element M, and zinc may be used. For example, the oxide semiconductor film described in Embodiment 1 or 2 is preferably used.

For the semiconductor layer 101b, for example, an oxide with a wide energy gap is used. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.7 eV or less, and more preferably 2.8 eV or more and 3.3 eV or less.

Next, the insulating layer 101a and the insulating layer 101c will be described. For example, the insulator layer 1
01a and the insulator layer 101c are one or more elements other than oxygen constituting the semiconductor layer 101b,
Alternatively, it is an oxide composed of two or more kinds. Since the insulator layer 101a and the insulator layer 101c are composed of one or more elements other than oxygen that form the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b, and the semiconductor layer 101b. Insulator layer 1
An interface level is hard to be formed at the interface with 01c.

Here, the band structure is shown in FIG. FIG. 11 shows a vacuum level.
Notated as vel. ), the energy at the bottom of the conduction band (denoted as Ec) and the energy at the top of the valence band (denoted as Ev) of each layer.

Here, a mixed region of the insulator layer 101a and the semiconductor layer 101b may be provided between the insulator layer 101a and the semiconductor layer 101b. In addition, the semiconductor layer 101b and the insulator layer 101
There may be a mixed region of the semiconductor layer 101b and the insulator layer 101c between the region c and the region c.
The mixed state has a low interface state density. Therefore, the insulator layer 101a and the semiconductor layer 101b
The stacked body of the insulating layer 101c and the insulating layer 101c has a band structure in which energy continuously changes (also referred to as continuous bonding) in the vicinity of each interface.

At this time, the electrons are not in the insulator layer 101a and the insulator layer 101c but in the semiconductor layer 1
It mainly moves in 01b. As described above, the insulator layer 101a and the semiconductor layer 101b
By lowering the interface state density at the interface of the semiconductor layer 101b and the interface state density at the interface between the semiconductor layer 101b and the insulating layer 101c, electron transfer in the semiconductor layer 101b is less likely to be hindered, and the on-state current of the transistor is reduced. Can be higher.

Note that FIG. 11 illustrates the case where the Ec of the insulator layer 101a and the Ec of the insulator layer 101c are similar, but they may be different from each other. For example, Ec of the insulating layer 101c may have higher energy than that of the insulating layer 101a.

As shown in FIG. 12B, the side surface of the semiconductor layer 101b has a conductive layer 104a and a conductive layer 1
Contact with 04b. In addition, as shown in FIG. 12C, the electric field of the gate electrode 103 causes
The semiconductor layer 101b can be electrically surrounded (a structure of a transistor that electrically surrounds a semiconductor by an electric field of a conductor can be used as a surrounded channel (s-c
channel) structure. ). Since the gate electrode 103 is provided so as to face the top surface and the side surface of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the top surface of the semiconductor layer 101b but also in the entire bulk. In the s-channel structure, a large current can flow between the source and the drain of the transistor, and the current (ON current) at the time of conduction can be increased.

Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since the transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high density. For example,
The transistor has a region whose channel length is preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, further preferably 30 nm or less, more preferably It has a region of 20 nm or less. In particular, the smaller the channel width is, the wider the region where the channel is formed inside the semiconductor layer 101b.

As the insulator layer 101a and the insulator layer 101c, for example, an In-M-Zn oxide can be used.

Note that indium gallium oxide has a low electron affinity and a high oxygen blocking property. Therefore, for example, the insulator layer 101c may include indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more.

Further, the insulator layer 101c more preferably contains gallium oxide. Insulator layer 101
When g contains gallium oxide, a lower off-state current may be realized in some cases.

For the insulator layers 101a and 101c, an nc-OS film or a CAAC-OS film is preferably used. Here, the nc ratio of the insulator layer 101a and the insulator layer 101c, the CA
By increasing the AC ratio, for example, the number of defects can be reduced. Further, for example, the region having spinel-type crystals can be reduced. Further, for example, carrier scattering can be reduced. Further, for example, a film having a high ability to block impurities can be obtained. Further, entry of impurities into the semiconductor layer 101b can be suppressed, and the impurity concentration of the semiconductor layer 101b can be reduced.

The nc ratio of the insulator layer 101a and the insulator layer 101c is preferably 10% or more,
30% or more is preferable, 50% or more is preferable, 80% or more is preferable, 90% or more is preferable, and 95% or more is preferable.

Here, the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are In-M-Zn.
Consider the case where it is an oxide. In having the insulator layer 101a, the atomic ratio of the element M and Zn and _{x a, y} a, and _{z a.} Similarly, In, an element M, and Zn included in the semiconductor layer 101b
Let x _{b be} the atomic ratio of x, y _b and z _b . Similarly, the atomic ratio of In, the elements M, and Zn included in the insulator layer 101c is x _c , y _c, and z _c . Each preferable value will be described below.

x _{b, y b} and _{z b} are 1, region 11 shown in FIG. 2 (A) and FIG. 4, region 12, region 13
It is preferable to take any one of the areas 14 and 14.

It is preferable that the insulator layer 101a and the insulator layer 101c do not include or have few spinel crystal structures. _{Thus, x a: y a: z} a and _{x c:} y _{c: z} c, for example FIG. 1
It is preferable to take a value within the range of the region 11 and having a smaller electron affinity than the semiconductor layer 101b.

Here, in order to make the electron affinity of the semiconductor layer 101b higher than that of the insulator layers 101a and 101c, for example, the indium content of the semiconductor layer 101b is preferably higher than that of the insulator layers 101a and 101c. ..

For _{example, x b / (x b +} y b + z b)> x a / (x a + y a + z a), and _x b / (x
_{b + y b + z b)} > It is preferable to satisfy the _{x c / (x c + y} c + z c).

For example, preferably _{x a / (x a + y} a) <0.5, more preferably _x a / (x
_a + _{y a)} <0.33, more preferably from _{x a / (x a + y} a) <0.25. Further, preferably x _b /(x _b +y _b )≧0.25, and more preferably x _b /(
x _b +y _b )≧0.34. Further, preferably x _c /(x _c +y _c )<0.5, more preferably x _c /(x _c +y _c )<0.33, and further preferably x _c /(x _c
+y _c )<0.25.

_{Or, x a, y a, z} a, and _{x c,} y _{c, z} c preferably has an atomic number ratio in the region 16 shown in FIG. 2 (B). Here, the region 16 has the first coordinates K(x:y:z=8:
14:7), the second coordinate R (x:y:z=2:4:3), and the third coordinate L (x:y:z
=2:5:7), the fourth coordinate M (x:y:z=51:149:300), the fifth coordinate B (x:y:z=1:4:10), The coordinates C (x:y:z=1:1:4) of 6 and the 7th
Is a region in which the coordinates A (x:y:z=2:2:1) and the first coordinates K are sequentially connected by a line segment. The region 16 includes all coordinates.

Note that when the transistor has an s-channel structure, a channel is formed over the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-state current of the transistor. For example, the semiconductor layer 101b may have a region with a thickness of 20 nm or more, preferably 40 nm or more, further preferably 60 nm or more, more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, the semiconductor layer 101b may have a region with a thickness of 300 nm or less, preferably 200 nm or less, further preferably 150 nm or less.

Further, in order to increase the on-state current of the transistor, it is preferable that the thickness of the insulator layer 101c be smaller. For example, less than 10 nm, preferably 5 nm or less, more preferably 3 nm
The insulator layer 101c having the following regions may be used. On the other hand, the insulator layer 101c is connected to the semiconductor layer 101b in which a channel is formed by an element other than oxygen (hydrogen,
Silicon, etc.) has the function of blocking so that it does not enter. Therefore, the insulator layer 10
1c preferably has a certain thickness. For example, the insulator layer 101c may have a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more. The insulator layer 101c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the gate insulating film 102 and the like.

Further, in order to improve reliability, it is preferable that the insulator layer 101a be thick and the insulator layer 101c be thin. For example, 10 nm or more, preferably 20 nm or more, more preferably 4
The insulator layer 101a may have a region with a thickness of 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulator layer 101a, the adjacent insulator and the insulator layer 101
The distance from the interface with a to the semiconductor layer 101b where the channel is formed can be increased.
However, since the productivity of the semiconductor device may decrease, for example, the insulator layer 1 having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.
It may be 01a.

When the oxide semiconductor film contains a large amount of hydrogen or moisture, a donor level due to hydrogen might be formed. The formation of the donor level may shift the threshold value of the transistor in the negative direction. Therefore, it is preferable that dehydration treatment (dehydrogenation treatment) be performed after formation of the oxide semiconductor film so that hydrogen or moisture is removed and purification is performed so that impurities are not contained as much as possible.

Note that oxygen may be simultaneously reduced by the dehydration treatment (dehydrogenation treatment) performed on the oxide semiconductor film. Therefore, it is preferable to supply oxygen after the dehydration treatment to fill oxygen vacancies in the oxide semiconductor film. In this specification and the like, supplying oxygen to the oxide semiconductor film may be referred to as oxygenation treatment. Alternatively, making the proportion of oxygen contained in the oxide semiconductor film higher than the stoichiometric composition is referred to as peroxygenation treatment in some cases.

As described above, hydrogen or water is removed by dehydration treatment and oxygen deficiency is compensated for by oxygenation treatment, so that i-type (intrinsic) or i-type is infinitely close or substantially i-type.
A type (intrinsic) oxide semiconductor film can be realized. Note that “substantially intrinsic” means that carriers derived from a donor are extremely small in the oxide semiconductor film (close to zero), carrier density is 1×10 ¹⁷ /cm ³ or less, 1×10 ¹⁶ /cm ³ or less, It is 1×10 ¹⁵ /cm ³ or less, 1×10 ¹⁴ /cm ³ or less, and 1×10 ¹³ /cm ³ or less.

A transistor including an i-type or substantially i-type oxide semiconductor film can realize extremely excellent off-state current. For example, the off-state current of a transistor including an oxide semiconductor film is 1×10 ⁻¹⁸ A or lower at room temperature (about 25° C.), preferably 1×10 ⁻²¹ A or lower, more preferably 1×10 ⁻²⁴ A. Or less, or 1×10 ⁻¹⁵ A or less at 85° C., preferably 1×10 ⁻¹⁸ A or less, more preferably 1×10 ⁻²¹ A or less. Here, off-state current refers to drain current when the transistor is in an off state. Further, the transistor is in an off state in the case of an n-channel transistor in which the gate voltage is sufficiently lower than the threshold value. Specifically, when the gate voltage is lower than the threshold value by 1 V or more, 2 V or more, or 3 V or more, the transistor is turned off.

One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode.

The conductive layers 104a and 104b each have a single-layer structure or a stacked-layer structure using a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as its main component. Used as. For example,
A single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked on a titanium film, a two-layer structure in which an aluminum film is stacked on a tungsten film, and a copper film is stacked on a copper-magnesium-aluminum alloy film. Two-layer structure, two-layer structure in which a copper film is stacked on a titanium film, two-layer structure in which a copper film is stacked on a tungsten film, a titanium film or a titanium nitride film, and aluminum overlaid on the titanium film or the titanium nitride film A three-layer structure in which a film or a copper film is stacked and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film. There is a three-layer structure in which a layered structure is formed and a molybdenum film or a molybdenum nitride film is further formed thereon.
Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

The gate insulating film 102 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn-based metal oxide, silicon nitride, or the like may be used, and they are provided as a stacked layer or a single layer.

As the gate insulating film 102, hafnium silicate (HfSiO _x ), nitrogen-added hafnium silicate (HfSi _x O _y N _z ), nitrogen-added hafnium aluminate (HfAl _x O _y N _z ), and yttrium oxide are used. High-k materials such as

As the gate insulating film 102, an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide is used. , A nitride insulating film of silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like, or a mixed material thereof.

As the gate insulating film 102, like the insulating film 114, it is preferable to use an oxide insulating film which contains more oxygen than the stoichiometric composition.

Note that when a specific material is used for the gate insulating film, electrons can be captured in the gate insulating film under specific conditions and the threshold voltage can be shifted in the positive direction. For example, a material with many electron trap levels such as hafnium oxide, aluminum oxide, and tantalum oxide is used for a part of the gate insulating film such as a stacked film of silicon oxide and hafnium oxide, and a higher temperature (use of a semiconductor device Temperature higher than the storage temperature or storage temperature, or 125 °C to 450 °C, typically 150 °C to 300 °C), the state where the potential of the gate electrode is higher than the potential of the source electrode or the drain electrode, By maintaining for 1 second or more, typically 1 minute or more, electrons move from the semiconductor layer toward the gate electrode, and some of them are trapped in an electron trap level.

The gate electrode 103 is formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten, an alloy containing the above metal as a component, an alloy in which the above metal is combined, or the like. You can Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used. Further, the gate electrode 103 may have a single-layer structure or a layered structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, and a two-layer structure in which a tungsten film is stacked over a titanium nitride film. There are a layer structure, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a titanium film and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon. is there. Also, on aluminum,
An alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.

The gate electrode 103 is formed of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above-described light-transmitting conductive material and the above metal can be used.

In addition, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, and an In-Zn-based film are provided between the gate electrode 103 and the gate insulating film 102. Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I
nN, ZnN, etc.) may be provided. These films have a work function of 5 eV or higher, preferably 5.5 eV or higher and have a value higher than the electron affinity of an oxide semiconductor; therefore, the threshold voltage of a transistor including an oxide semiconductor is increased in the positive direction. It is possible to shift, and it is possible to realize a switching element having a so-called normally-off characteristic. For example, when using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of the semiconductor layer 101, specifically, 7 atomic% or more is used.

The above is the description of the transistor 100.

Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion of a semiconductor in which a current flows when the transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. , Source (source region or source electrode)
And the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when a transistor is in an on state) and a gate electrode overlap with each other, or a region where a channel is formed in which a source and a drain face each other. It is the length of the part where it exists. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be set to one value. Therefore, in this specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Note that depending on the structure of the transistor, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and a channel width shown in a top view of the transistor (hereinafter, an apparent channel width). May be different from. For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be higher than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which a channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the semiconductor shape is known. Therefore, it is difficult to measure the effective channel width accurately when the shape of the semiconductor is not known accurately.

Therefore, in this specification, in a top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW)”. : Surrounded Channel
Width)". Further, in this specification, when simply described as channel width, it may indicate an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width.
Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image and analyzing the image. it can.

Note that when the field-effect mobility of a transistor, a current value per channel width, or the like is calculated and obtained, the enclosed channel width may be used in some cases. In that case, the value may be different from the value calculated using the effective channel width.

[Example 2 of transistor]
An example of a structure of a transistor including an oxide semiconductor film which is one embodiment of the present invention, which is different from that in FIG. 12, is described with reference to FIGS. 13A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 13C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. 13A.

The transistor 100 includes a gate electrode 203a which functions as a gate electrode over the substrate 50, a gate insulating film 202 over the substrate 50 and the gate electrode 203a, a semiconductor layer 201 over the gate insulating film 202, and a semiconductor layer 201 electrically. A conductive layer 204a and a conductive layer 204b which function as a source electrode and a drain electrode which are connected to each other are included. In addition, the transistor 100
Above, more specifically, the insulating film 21 over the conductive layer 204a, the conductive layer 204b, and the semiconductor layer 201.
4, an insulating film 216, and an insulating film 218 are sequentially stacked.

Next, components included in the transistor of this embodiment are described.

For the gate electrode 203a functioning as the gate electrode of the transistor 100, the description of the gate electrode 103 may be referred to.

For the gate insulating film 202 which functions as the gate insulating film of the transistor 100, the description of the gate insulating film 102 may be referred to. Alternatively, a stacked film of two or more layers may be used as the gate insulating film 202. For example, as shown in FIG. 13, a two-layer structure of a gate insulating film 202a and a gate insulating film 202b may be used. In that case, for example, a lower layer, here, the gate insulating film 20
A film having a function as a blocking film that suppresses the permeation of oxygen may be used for 2a. For a film having a function as a blocking film, for example, the barrier film 111 described later may be referred to.

As the semiconductor layer 201, the oxide semiconductor film described in Embodiment 1 or 2 may be used. For the semiconductor layer 201, the description of the semiconductor layer 101 may be referred to. Alternatively, the semiconductor layer 201 may be a stacked film of two or more layers.

The insulating film 214, the insulating film 216, and the insulating film 218 have a function as a protective insulating film of the transistor 100. The insulating film 214 also functions as a damage mitigating film for the semiconductor layer 201 when the insulating film 216 is formed.

It is more preferable that the insulating film 214 and the insulating film 216 have a region containing oxygen in excess of the stoichiometric composition (oxygen excess region) like the above-described insulating film 114, for example.

It is preferable that the insulating film 214 have a small amount of defects. Typically, the signal has a spin density of 3×10 ¹⁷ spins/cm which appears at g=2.001 which is derived from a dangling bond of silicon by ESR measurement. It is preferably ³ or less. When the density of defects in the insulating film 214 is high, oxygen is bonded to the defects and the amount of oxygen that permeates the insulating film 214 is reduced.

In the insulating film 214, all the oxygen that entered the insulating film 214 from the outside is entirely contained in the insulating film 21.
Some oxygen does not move to the outside of the insulating film 214 and stays in the insulating film 214. In addition, when oxygen enters the insulating film 214 and oxygen contained in the insulating film 214 moves to the outside of the insulating film 214, oxygen may move in the insulating film 214. When an oxide insulating film which can transmit oxygen is formed as the insulating film 214, oxygen released from the insulating film 216 which is provided over the insulating film 214 is transferred to the semiconductor layer 201 through the insulating film 214. You can

The insulating film 214 has an energy (E _{v — os} ) at the upper end of the valence band of the oxide semiconductor film.
And an energy (E _{c — os} ) at the lower end of the conduction band can be formed using an oxide insulating film in which the level density of nitrogen oxide is low. As an oxide insulating film having a low level density of nitrogen oxides between E _{v — os} and E _{c — os,} a silicon oxynitride film that releases a small amount of nitrogen oxides, an aluminum oxynitride film that releases a small amount of nitrogen oxides, or the like Can be used.

Note that a silicon oxynitride film that releases a small amount of nitrogen oxides is a film that releases a larger amount of ammonia molecules than a released amount of nitrogen oxides in a thermal desorption gas analysis method. The emission amount is 1×10 ¹⁸ pieces/cm ³ or more and 5×10 ¹⁹ pieces/cm ³ or less. The amount of released ammonia molecules is such that the surface temperature of the film is 50° C. or higher and 650° C. or lower, preferably 5° C.
The amount released by heat treatment at 0°C or higher and 550°C or lower.

Nitrogen oxide (NO _x , x is greater than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO, forms a level in the insulating film 214 or the like. The level is the semiconductor layer 20.
It is located within the energy gap of 1. Therefore, when nitrogen oxide diffuses into the interface between the insulating film 214 and the semiconductor layer 201, the level may trap electrons on the insulating film 214 side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating film 214 and the semiconductor layer 201, so that the threshold voltage of the transistor is shifted in the positive direction.

Further, nitrogen oxide reacts with ammonia and oxygen in heat treatment. Insulating film 214
In the heat treatment, the nitrogen oxide contained in OH reacts with ammonia contained in the insulating film 216, so that the nitrogen oxide contained in the insulating film 214 is reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 214 and the semiconductor layer 201.

Note that the insulating film 214 has a function of protecting the back channel region of the semiconductor layer 201 by being in contact with the semiconductor layer 201 on the opposite side of a region where a channel is formed in the semiconductor layer 201 (hereinafter referred to as a back channel region). Have.

By using an oxide insulating film having a low level density of nitrogen oxide between E _{v — os} and E _{c — os} as the insulating film 214, shift of the threshold voltage of the transistor can be reduced and It is possible to reduce fluctuations in electrical characteristics.

An oxide insulating film having a low level density of nitrogen oxides between E _{v — os} and E _{c — os} is S
The nitrogen concentration measured by IMS is 6×10 ²⁰ atoms/cm ³ or less.

Further, the insulating film 216 preferably has a small amount of defects, and typically, the ESR measurement shows that the spin density of a signal appearing at g=2.001 derived from a dangling bond of silicon is 1.5×10 ^18. less than spins/cm ³ , and further 1×10 ¹⁸ spins/cm ³
The following is preferable. Note that the insulating film 216 is different from the insulating film 214 in the semiconductor layer 2 in
Since it is separated from 01, the defect density may be higher than that of the insulating film 214.

Alternatively, the transistor 100 may have the structure illustrated in FIGS. Here, the transistor 100 shown in FIG. 13 is a channel-etch type transistor, but the transistor 100 shown in FIGS. 14 and 15 is a channel-protection type transistor.

14A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 14C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. 14A. The transistor 100 illustrated in FIG. 14 includes a gate electrode 203a provided over the substrate 50, a gate insulating film 202 formed over the substrate 50 and the gate electrode 203a, and a semiconductor overlapping with the gate electrode 203a with the gate insulating film 202 interposed therebetween. The layer 201, the insulating film 214 on the gate insulating film 202 and the semiconductor layer 201, the insulating film 216 on the insulating film 214, and the semiconductor layer 20 in the openings 141a and 141b of the insulating film 214 and the insulating film 216.
1 has a pair of conductive layers 204a and 204b which are in contact with each other. Also, the transistor 1
00, more specifically, the insulating film 218 may be provided over the conductive layer 204a, the conductive layer 204b, and the insulating film 216.

15A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 15C corresponds to a cross-sectional view of a cross section taken along alternate long and short dash line Y1-Y2 in FIG. 15A. The transistor 100 shown in FIG. 15 corresponds to the transistor 10 shown in FIG.
0 and the shapes of the insulating films 214 and 216 are different. Specifically, the transistor 1 shown in FIG.
00 insulating films 214 and 216 are provided in an island shape on the channel region of the semiconductor layer 101.
Other structures are similar to those of the transistor 100 shown in FIG. 14, and have similar effects.

In each of the transistors 100 illustrated in FIGS. 14 and 15, the semiconductor layer 201 is covered with the insulating film 214 and the insulating film 216 when the pair of conductive layers 204a and 204b are formed; The semiconductor layer 201 is not damaged by the etching for forming the conductive layer 204b. Further, when the insulating film 214 and the insulating film 216 are oxide insulating films containing nitrogen and having a small amount of defects, variation in electric characteristics is suppressed and a transistor with improved reliability can be manufactured. it can.

Further, the transistor 100 may have an electrode 203b over the insulating film 218 as illustrated in FIG. 16A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along dashed-dotted line X1-X2 in FIG. 16C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. 16A. In FIG. 16, the electrode 203b is shown as the insulating film 214 and the insulating film 2.
Although the structure is shown in which the gate electrode 203a is connected through the opening 142c and the opening 142d provided in 16, the electrode 203b and the gate electrode 203a may not be connected.
When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the electrodes.

As shown in FIG. 16, the side surface of the semiconductor layer 201 and the electrode 203b in the channel width direction.
And the gate electrode 203a and the electrode 203b surround the semiconductor layer 201 with the gate insulating film 202 and the insulating film 214, the insulating film 216, and the insulating film 218 in the channel width direction. The region where carriers flow in the semiconductor layer 201 is not only the interface between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201, but also the semiconductor layer 20.
Since carriers flow inside 1 as well, the amount of carrier movement in the transistor 100 increases. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is increased. Further, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201 or the end portion including the side surface and the vicinity thereof, generation of a parasitic channel on the side surface or the end portion of the semiconductor layer 201 can be suppressed.

In addition, in FIG. 16, as an example of the semiconductor layer 201, the semiconductor layer 201b is formed over the semiconductor layer 201a.
The structure which laminates is shown. Here, for example, in the semiconductor layer 201b, the energy of the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 201a, and typically, the energy of the lower end of the conduction band of the semiconductor layer 201b and the energy of the conduction band of the semiconductor layer 201a. The difference from the energy at the bottom is 0.05 eV
Or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less,
It is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more and 0.07 e.
V or higher, 0.1 eV or higher, or 0.15 eV or higher and 2 eV or lower, 1 eV or lower, 0.
It is 5 eV or less, or 0.4 eV or less.

For the semiconductor layer 201a, the semiconductor layer 101b described in Embodiment 3 may be referred to. For example, a preferable range of the atomic ratio of indium, the element M, and zinc included in the semiconductor layer 101b may be referred to. Further, as the semiconductor layer 201b, the insulator layer 1 described in Embodiment 3 is used.
01c may be referred to. For example, the preferable range of the atomic ratio of indium, the element M, and zinc that the insulator layer 101c has may be referred to.

[Modification of transistor]
Modification examples of the transistor 100 are shown in FIGS. For example, the transistor 100 may have the structure shown in FIG. 30, the shapes of the conductive layers 104a and 104b are different from those in FIG. Note that FIG. 30B passes through the dashed-dotted line AB shown in FIG.
A cross section of a plane perpendicular to 0 (A) is shown.

Further, the transistor 100 may have the structure shown in FIG. In FIG. 12, the insulator layer 101
While c is in contact with the top surfaces of the conductive layers 104a and 104b, in FIG.
04a and the lower surface of the conductive layer 104b. Note that FIG. 31B illustrates a cross section of a surface which is perpendicular to FIG. 31A and passes through the dashed-dotted line AB in FIG. With such a structure, the films forming the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c can be continuously formed without being exposed to the air during film formation. , Each interface defect can be reduced.

Further, the transistor 100 may have the structure shown in FIG. Note that FIG. 32B illustrates a cross section of a plane which is perpendicular to FIG. 32A and which passes through the dashed-dotted line AB in FIG. 32A. Figure 32
Differs from FIG. 12 in that it does not have the conductive layers 104a and 104b. Here in FIG.
As illustrated in (C), the transistor 100 may include the low resistance layer 171a and the low resistance layer 171b. The low resistance layer 171a and the low resistance layer 171b preferably function as a source region or a drain region. Further, impurities may be added to the low resistance layer 171a and the low resistance layer 171b. The resistance of the semiconductor layer 101 can be reduced by adding an impurity. As impurities to be added, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium,
It is preferable to add one or more selected from zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. The low-resistance layer 171a and the low-resistance layer 171b include, for example, the above-mentioned impurity element in the semiconductor layer 101 at 5×10 ¹⁹ atoms/cm ³ or more, preferably 1×10 ²⁰ atoms/c.
m ³ or more, more preferably 2×10 ²⁰ atoms/cm ³ or more, and more preferably 5×.
This is a region containing 10 ²⁰ atoms/cm ³ or more. FIG. 32D is an enlarged view of the region 324 of FIG. 32C.

In some cases, impurities such as unnecessary hydrogen can be trapped in such a low resistance region. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region can be reduced, and favorable characteristics of the transistor 100 can be obtained.

Further, the transistor 100 may have the structure shown in FIG. FIG. 33 shows the insulator layer 101.
The shapes of c and the gate insulating film 102 are different from those in FIG. Note that FIG. 33B corresponds to FIG.
FIG. 33A shows a cross section of a plane perpendicular to FIG. 33A through the dashed-dotted line AB.

In the structure shown in FIGS. 30 to 33, the insulating layer 101 is in contact with the semiconductor layer 101b.
Although the configuration in which a and the insulator layer 101c are provided has been described, the insulator layer 101a or the insulator layer 1 is described.
One or both of 01c may be omitted.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described in any of the above embodiments will be described below with reference to FIGS.

FIG. 34 is a top view showing an example of a display device. A display device 700 illustrated in FIG. 34 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, and a source. A sealing material 712 arranged so as to surround the driver circuit portion 704 and the gate driver circuit portion 706;
A second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are
It is sealed by the first substrate 701, the sealant 712, and the second substrate 705. In addition,
Although not shown in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705.

In the display device 700, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the gate driver circuit portion are provided in a region different from the region surrounded by the sealant 712 on the first substrate 701. FPC terminal portion 708 electrically connected to 706
(FPC: Flexible printed circuit) is provided. Also,
The FPC 716 is connected to the FPC terminal portion 708, and the pixel portion 702 is connected by the FPC 716.
Various signals and the like are supplied to the source driver circuit portion 704 and the gate driver circuit portion 706. Further, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706.
, And the FPC terminal portion 708 are connected to signal lines 710, respectively. Various signals and the like supplied by the FPC 716 are given to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the signal line 710.

Further, the display device 700 may be provided with a plurality of gate driver circuit portions 706. Further, although the display device 700 shows an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702, the present invention is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (eg, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. .. The method of connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a wiring portion or a plurality of transistors, and thus the semiconductor device of one embodiment of the present invention can be applied. it can.

Further, the display device 700 can include various elements. The element is, for example, a liquid crystal element, an EL (electroluminescence) element (an EL element containing an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, a red LED, a green LED, a blue LED).
Etc.), transistors (transistors that emit light in response to current), electron-emitting devices, electronic ink, electrophoretic devices, grating light valves (GLV), plasma displays (P
DP), a display element using MEMS (micro electro mechanical system),
Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MIRASOL (registered trademark), IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electro-wet It has at least one of a switching element, a piezoelectric ceramic display, a display element using carbon nanotubes, and the like. In addition to these, a display medium whose contrast, luminance, reflectance, transmittance, or the like is changed by an electrical or magnetic action may be included. An EL display is an example of a display device using an EL element. As an example of a display device using an electron-emitting device, a field emission display (FED) or a SED type flat-panel display (SED: Surface-conduction E) is used.
electron-emitter display). An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display).
and so on. An example of a display device using electronic ink or an electrophoretic element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have a function as a reflective electrode. For example, part or all of the pixel electrode may include aluminum, silver, or the like. Further, in that case, a storage circuit such as SRAM can be provided below the reflective electrode. Thereby, the power consumption can be further reduced.

Note that the display device 700 can use a progressive system, an interlace system, or the like as a display system. Further, as a color element controlled by the pixel when displaying in color, R is
It is not limited to the three colors of GB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pen tile array, one color element may be configured by two colors of RGB, and two different colors may be selected and configured by the color element. Alternatively, one or more colors of yellow, cyan, magenta, etc. may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) emits white light (
A colored layer (also referred to as a color filter) may be used in order to display a display device in full color using W). The coloring layer is, for example, red (R), green (G), blue (B)
, Yellow (Y), and the like can be used in an appropriate combination. By using the colored layer,
The color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, by arranging a region having a colored layer and a region not having a colored layer, white light in the region having no colored layer may be directly used for display. By arranging a region having no colored layer in part, it is possible to reduce the decrease in brightness due to the colored layer during bright display and reduce power consumption by about 20 to 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from the elements having respective luminescent colors. .. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.

In this embodiment mode, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. Note that FIG. 35 is a cross-sectional view taken along dashed-dotted line QR in FIG. 34 and has a structure in which a liquid crystal element is used as a display element. 36 is a cross-sectional view taken along alternate long and short dash line QR shown in FIG. 34, in which an EL element is used as a display element.

First, common parts shown in FIGS. 35 and 36 will be described first, and then different parts will be described below.

[Explanation on common parts of display device]
The display device 700 illustrated in FIGS. 35 and 36 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 has a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790 (a capacitor 790a or a capacitor 790b). In addition, the source driver circuit portion 704 includes a transistor 752.

The signal line 710 is formed in the same step as a conductive film functioning as a source electrode and a drain electrode of the transistors 750 and 752. Note that the signal line 710 is connected to the transistor 75.
A conductive film formed in a process different from that of the source and drain electrodes of 0 and 752, for example, a conductive film functioning as a gate electrode may be used. When a material containing a copper element, for example, is used as the signal line 710, signal delay or the like due to wiring resistance is small and display on a large screen is possible.

As the transistors 750 and 752, the above-described transistors can be used. Although an example in which the structure of the transistor 100 illustrated in FIGS. 13A and 13B is used for the transistor 750 and the transistor 752 is described here, another transistor described above may be used.

Alternatively, the transistor 750 and the transistor 752 may have the structure of the transistor 100 illustrated in FIG. 16, for example. In this case, the electrode 203b can be formed using the same process as the formation of the conductive layer 772 and the conductive layer 784, for example. By using the structure of the transistor 100 illustrated in FIG. 16, for example, the transistor 750 and the transistor 75
2 can be increased, and the circuit operation speed can be increased. In addition, the channel width of the transistor 750 or the transistor 752 can be reduced in some cases, so that the circuit can be integrated.

The transistor used in this embodiment has a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The transistor can have a low current value in the off state (off current value). Therefore, the holding time of an electric signal such as an image signal can be extended, and the writing interval can be set long in the power-on state. Therefore, the frequency of refresh operations can be reduced, which leads to an effect of suppressing power consumption.

In addition, the transistor used in this embodiment can have relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over one substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, in the pixel portion as well, by using a transistor which can be driven at high speed, a high-quality image can be provided.

Further, the FPC terminal portion 708 includes the connection electrode 760, the anisotropic conductive layer 780, and the FPC 71.
Have 6. Note that the connection electrode 760 is formed in the same step as a conductive film functioning as a source electrode and a drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is F
It is electrically connected to a terminal included in the PC 716 through the anisotropic conductive layer 780.

Further, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, flexible substrates may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

A flexible display device can be manufactured by using a flexible substrate. Since the display device has flexibility, the display device can be attached to a curved surface or an irregular shape, so that a variety of applications can be realized.

For example, by using a flexible substrate such as a plastic substrate, the display device can be thin and lightweight. Further, for example, a display device using a flexible substrate such as a plastic substrate is less likely to be broken, and, for example, durability against impact when dropped can be improved.

Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix,
A coloring film 736 which functions as a color filter and an insulating film 734 which is in contact with the light-blocking film 738 and the coloring film 736 are provided.

Further, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching the insulating film,
It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778. In addition, FIG.
In the above, the structure 778 is provided on the second substrate 705 side, but the structure is not limited to this. For example, as shown in FIG. 36, the structure 778 may be provided on the first substrate 701 side, or the structure 778 may be provided on both the first substrate 701 and the second substrate 705.

In addition, in FIGS. 35 and 36, on the transistor 750 and the transistor 752,
Insulating films 764, 766, 768 are provided.

As the insulating films 764, 766, and 768, the insulating film 214 described in any of the above embodiments is used.
216, 218 and the same material and manufacturing method.

[Configuration Example of Display Device Using Liquid Crystal Element as Display Element]
The display device 700 illustrated in FIG. 35 includes a capacitor 790a. The capacitor 790a has a structure having a dielectric between a pair of electrodes. More specifically, as one electrode of the capacitor 790a, an oxide semiconductor film with high conductivity formed through the same step as the oxide semiconductor film functioning as a semiconductor layer of the transistor 750 is used. A conductive layer 772 electrically connected to the transistor 750 is used as the other electrode. In addition, an insulating film 768 is used as a dielectric sandwiched between the pair of electrodes.

Here, the highly conductive oxide semiconductor film which functions as one of the pair of electrodes of the capacitor 790a is described below.

[About highly conductive oxide semiconductor film]
When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed, hydrogen enters the oxygen vacancies and a donor level is formed in the vicinity of the conduction band. As a result, the oxide semiconductor has high conductivity,
It becomes a conductor. An oxide semiconductor which has been converted to a conductor can be referred to as an oxide conductor. In general, an oxide semiconductor has a large energy gap and thus has a property of transmitting visible light.
On the other hand, the oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the effect of absorption by the donor level is small, and the light-transmitting property is similar to that of an oxide semiconductor with respect to visible light.

Here, in each of a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film (OC)). The temperature dependence of the resistivity will be described.

The temperature dependence of the resistivity of the oxide conductor film (OC) is smaller than the temperature dependence of the resistivity of the oxide semiconductor film (OS). Typically, the rate of change in resistivity of the oxide semiconductor film (OC) at 80 K or higher and 290 K or lower is less than ±20%. Or 150K or more 2
The rate of change in resistivity at 50 K or less is less than ±10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level match or substantially match.
Therefore, the oxide conductor film can be used for one electrode of the capacitor 790a. Here, the oxide conductor film can be formed by forming silicon nitride over the In-M-Zn oxide, for example.

The display device 700 illustrated in FIG. 35 includes a liquid crystal element 775. The liquid crystal element 775 is
The conductive layer 772, the conductive layer 774, and the liquid crystal layer 776 are included. The conductive layer 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700 shown in FIG.
The voltage applied to the conductive layers 772 and 774 changes the alignment state of the liquid crystal layer 776, whereby light transmission and non-transmission is controlled, so that an image can be displayed.

The conductive layer 772 is connected to a conductive film functioning as a source electrode and a drain electrode included in the transistor 750. The conductive layer 772 is formed on the insulating film 768 and is a pixel electrode,
That is, it functions as one electrode of the display element.

Examples of the conductive layer 772 include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.

Although not shown in FIG. 35, an alignment film may be provided on each of the conductive layers 772 and 774 which is in contact with the liquid crystal layer 776. Although not shown in FIG. 35, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

In the case of adopting the horizontal electric field method, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition in which a chiral agent of several wt% or more is mixed is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent,
Since the response speed is short and it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, rubbing treatment is not necessary, so that electrostatic breakdown caused by the rubbing treatment can be prevented and defects and damages of the liquid crystal display device during a manufacturing process can be reduced. ..

When a liquid crystal element is used as a display element, TN (Twisted Nematic)
) Mode, IPS (In-Plane-Switching) mode, FFS (Frin)
ge Field Switching mode, ASM (axially symmetry)
tric aligned Micro-cell) mode, OCB (Optical)
Compensated Birefringence mode, FLC (Ferroe)
Electric Liquid Crystal mode, AFLC (AntiFerr)
For example, an electric liquid crystal mode can be used.

Alternatively, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, MVA (Multi-Domain Vertical Alignment) is used.
) Mode, PVA (Patterned Vertical Alignment) mode, ASV mode and the like can be used.

[Display Device Using Light Emitting Element as Display Element]
The display device 700 illustrated in FIG. 36 includes a capacitor 790b. The capacitor 790b has a structure having a dielectric between a pair of electrodes. More specifically, a conductive film formed in the same step as the conductive film functioning as the gate electrode of the transistor 750 is used as one electrode of the capacitor 790b, and the source of the transistor 750 is used as the other electrode of the capacitor 790b. A conductive film which functions as an electrode or a drain electrode is used. An insulating film functioning as a gate insulating film of the transistor 750 is used as the dielectric sandwiched between the pair of electrodes.

Further, in FIG. 36, a planarization insulating film 770 is provided over the insulating film 768.

As the planarization insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed of these materials. Further, as shown in FIG. 35, the planarization insulating film 77
The configuration may be such that 0 is not provided.

Further, the display device 700 illustrated in FIG. 36 includes a light emitting element 782. The light emitting element 782 is
A conductive layer 784, an EL layer 786, and a conductive layer 788 are included. Display device 700 shown in FIG.
The EL layer 786 included in the light emitting element 782 emits light, so that an image can be displayed.

The conductive layer 784 is connected to a conductive film which functions as a source electrode and a drain electrode included in the transistor 750. The conductive layer 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive layer 784, a conductive film which transmits visible light or a conductive film which reflects visible light can be used. As the conductive film having a property of transmitting visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective to visible light, a material containing aluminum or silver may be used, for example.

In addition, in the display device 700 illustrated in FIG. 36, the insulating film 730 is provided over the planarization insulating film 770 and the conductive layer 784. The insulating film 730 covers part of the conductive layer 784. Note that the light emitting element 782 has a top emission structure. Therefore, the conductive layer 788 has a light-transmitting property and
The light emitted from the L layer 786 is transmitted. Although the top emission structure is illustrated in the present embodiment, the present invention is not limited to this. For example, the invention can be applied to a bottom emission structure that emits light to the conductive layer 784 side and a dual emission structure that emits light to both the conductive layer 784 and the conductive layer 788.

Further, a colored film 736 is provided in a position overlapping with the light emitting element 782, and a light shielding film 738 is provided in a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. The coloring film 736 and the light-shielding film 738 are covered with the insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that FIG.
In the display device 700 shown in (1), the configuration in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by coating separately, the coloring film 736 may be omitted.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 5)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

The display device illustrated in FIG. 26A includes a region including a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion provided outside the pixel portion 502 and including a circuit for driving the pixel (
Hereinafter, referred to as a drive circuit portion 504) and a circuit having a function of protecting an element (hereinafter, the protection circuit 50).
6) and a terminal portion 507. Note that the protection circuit 506 may not be provided.

It is preferable that part or all of the driver circuit portion 504 be formed over the same substrate as the pixel portion 502. As a result, the number of parts and the number of terminals can be reduced. Drive circuit unit 504
When part or all of the driving circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is COG or TAB (Tape Automated B).
Onboarding).

The pixel portion 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) Y columns (Y is a natural number of 2 or more). The driving circuit portion 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel ( Hereinafter, a driver circuit such as the source driver 504b) is included.

The gate driver 504a includes a shift register and the like. The gate driver 504a is
A signal for driving the shift register is input through the terminal portion 507 and the signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling potentials of wirings (hereinafter referred to as scan lines GL_1 to GL_X) to which scan signals are given. Note that a plurality of gate drivers 504a may be provided and the scan lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the gate driver 50 is not limited to this.
4a can also supply another signal.

The source driver 504b includes a shift register and the like. The source driver 504b is
A signal (image signal) which is a source of a data signal is input through the terminal portion 507 in addition to a signal for driving the shift register. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on an image signal. Further, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. Further, the source driver 504b has a function of controlling the potential of a wiring to which a data signal is applied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches and the like.
The source driver 504b sequentially turns on a plurality of analog switches,
A signal obtained by time-sharing an image signal can be output as a data signal. Alternatively, the source driver 504b may be formed using a shift register or the like.

A pulse signal is input to each of the plurality of pixel circuits 501 through one of the plurality of scan lines GL to which a scan signal is supplied, and a data signal is received through one of the plurality of data lines DL to which a data signal is supplied. Is entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data of a data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and the n-th column, a pulse signal is input from the gate driver 504a through the scan line GL_m (m is a natural number less than or equal to X), and the data line DL_n( depending on the potential of the scan line GL_m(
A data signal is input from the source driver 504b via (n is a natural number equal to or less than Y).

The protection circuit 506 illustrated in FIG. 26A includes, for example, the gate driver 504a and the pixel circuit 5
It is connected to the scanning line GL, which is a wiring between 01. Alternatively, the protection circuit 506 is connected to the data line DL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 is a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit which, when a potential outside a certain range is applied to a wiring to which the protection circuit 506 is connected, brings the wiring and another wiring into a conductive state.

As shown in FIG. 26A, the protection circuit 50 is provided in each of the pixel portion 502 and the driver circuit portion 504.
By providing 6, ESD (Electro Static Discharge:
It is possible to increase the resistance of the display device to an overcurrent generated by (electrostatic discharge) or the like.
However, the configuration of the protection circuit 506 is not limited to this, and for example, the gate driver 504a may be connected to the protection circuit 506 or the source driver 504b may be connected to the protection circuit 506. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

26A illustrates an example in which the driver circuit portion 504 is formed by the gate driver 504a and the source driver 504b, the invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a separately prepared substrate on which a source driver circuit is formed (eg, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

The plurality of pixel circuits 501 illustrated in FIG. 26A can have the structure illustrated in FIG. 26B, for example.

The pixel circuit 501 illustrated in FIG. 26B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in any of the above embodiments can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is set as appropriate in accordance with the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570, a TN mode, an STN mode, a VA mode, and an ASM (Axially Symmetric Aligned M) are used.
micro-cell) mode, OCB (optically compensated)
Birefringence mode, FLC (Ferroelectric Liquid)
id Crystal mode, AFLC (Anti Ferroelectric Li)
liquid crystal mode, MVA mode, PVA (Patterned Ve)
vertical alignment mode, IPS mode, FFS mode, or TBA
(Transverse Bend Alignment) mode or the like may be used.
Further, as a driving method of the display device, in addition to the driving method described above, an ECB (Electric) is used.
all Controlled Birefringence mode, PDLC(P
Polymer Dispersed Liquid Crystal) mode, PNLC
There are (Polymer Network Liquid Crystal) mode, guest host mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 550 is electrically connected to the data line DL_n and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. It In addition, the gate electrode of the transistor 550 is the scan line G
It is electrically connected to L_m. The transistor 550 has a function of controlling writing of data of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 has a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL).
) And the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Note that the value of the potential of the potential supply line VL is set as appropriate in accordance with the specifications of the pixel circuit 501. The capacitor 560 has a function as a storage capacitor that holds written data.

For example, in a display device including the pixel circuit 501 in FIG. 26B, for example, in FIG.
The pixel driver 501 of each row is sequentially selected by the gate driver 504a shown in (1), the transistor 550 is turned on, and the data of the data signal is written.

The pixel circuit 501 in which the data is written enters a holding state by turning off the transistor 550. An image can be displayed by sequentially performing this for each row.

The plurality of pixel circuits 501 illustrated in FIG. 26A can have the structure illustrated in FIG. 26C, for example.

The pixel circuit 501 illustrated in FIG. 26C includes transistors 552 and 554, a capacitor 562, and a light emitting element 572. Transistor 552 and transistor 554
The transistor described in any of the above embodiments can be applied to either or both of them.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is applied (hereinafter referred to as a signal line DL_n). In addition, the transistor 55
The second gate electrode is electrically connected to a wiring to which a gate signal is applied (hereinafter, referred to as a scanning line GL_m).

The transistor 552 has a function of controlling writing of data of a data signal by being turned on or off.

One of a pair of electrodes of the capacitor 562 has a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL).
_A), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

The capacitor 562 has a function as a storage capacitor that holds written data.

One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of an anode and a cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that the high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and the low power supply potential VSS is applied to the other.

In a display device including the pixel circuit 501 in FIG. 26C, for example, the pixel driver 501 in each row is sequentially selected by the gate driver 504a illustrated in FIG. 26A, the transistor 552 is turned on, and data of a data signal is output. Write.

The pixel circuit 501 in which the data is written enters a holding state by turning off the transistor 552. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with a luminance corresponding to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 6)
Hereinafter, an example of a semiconductor device including the oxide semiconductor of one embodiment of the present invention will be described.

[Example of semiconductor device]
FIG. 37A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 37A includes a transistor 100, a transistor 130, a capacitor 150, a wiring WBL, a wiring RBL, a wiring WL, a wiring CL, a wiring BG, and a wiring SL. ..

One of a source and a drain of the transistor 130 is electrically connected to the wiring RBL,
The other is electrically connected to the wiring SL, and the gate is electrically connected to one of a source and a drain of the transistor 100 and one electrode of the capacitor 150. The other of the source and the drain of the transistor 100 is electrically connected to the wiring WBL and the first gate thereof is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. The wiring BG is electrically connected to the second gate of the transistor 100. The transistor 1
30, the source or the drain of the transistor 100, and the capacitor 150.
The node between one of the electrodes is called a node FN.

In the semiconductor device in FIG. 37A, a potential corresponding to the potential of the wiring WBL is applied to the node FN when the transistor 100 is in a conductive state (on state). In addition, the transistor 100 has a function of holding the potential of the node FN when the transistor 100 is off (in an off state). That is,
The semiconductor device illustrated in FIG. 37A functions as a memory cell of a memory device. FIG. 37
By arranging the semiconductor devices shown in (A) in a matrix, a memory device (memory cell array) can be formed.

In addition, a liquid crystal element or an organic EL (Electroluminescence) electrically connected to the node FN.
In the case where the semiconductor device in FIG. 37A can be used as a pixel of the display device, the semiconductor device in FIG. 37A can be used.

The conductive state and the non-conductive state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold value of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with low off-state current as the transistor 100, the potential of the node FN in the non-conduction state can be held for a long time. Therefore, the frequency of refreshing the semiconductor device can be reduced, and a semiconductor device with low power consumption can be realized. By using a transistor including an oxide semiconductor film as the transistor 100, a transistor with low off-state current can be realized.

Note that a constant potential such as a reference potential, a ground potential, or any fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. By utilizing the fact that the conduction state and the non-conduction state of the transistor 130 are changed due to the apparent fluctuation of the threshold voltage, the potential information held in the node FN can be read as data.

Note that the potential held at the node FN was maintained at 85° C. for 10 years (3.15×10 ⁸ seconds).
In order to maintain the capacitance, the off-current value per 1 fF of capacitance and 1 μm of channel width of the transistor is preferably less than 4.3 yA (Yogtoampere: 1 yA is 10 ⁻²⁴ A). At this time, it is preferable that the allowable fluctuation of the potential of the node FN is within 0.5V. Alternatively, at 95° C., the off-state current is preferably less than 1.5 yA.

Further, by increasing the capacitance, the potential can be held at the node FN for a longer time. That is, the holding time can be extended.

In the semiconductor device in FIG. 37A, by utilizing the feature that the potential of the gate electrode of the transistor 130 can be held, writing, holding, and reading of data can be performed as follows.

Writing and holding of information will be described. First, the potential of the wiring WL is set to the transistor 1
The transistor 100 is turned on by setting the potential at which 00 turns on. This allows
The potential of the wiring WBL is applied to the gate electrode of the transistor 130 and the capacitor 150. That is, predetermined charge is applied to the gate electrode of the transistor 130 (writing). Here, charges that give two different potential levels (hereinafter referred to as Low level charge, High
or h level charge). After that, the potential of the wiring WL is changed to
The electric potential applied to the transistor 100 is turned off and the transistor 100 is turned off, whereby the charge applied to the gate electrode of the transistor 130 is held (holding).

Since the off-state current of the transistor 100 is extremely small, the charge of the gate electrode of the transistor 130 is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the wiring CL with a predetermined potential (constant potential) applied to the wiring RBL, the wiring SL has a different potential depending on the amount of charge held in the gate electrode of the transistor 130. Take In general, when the transistor 130 is an n-channel type, the apparent threshold value V _{th_H} when high level charge is applied to the gate electrode of the transistor 130 is low level charge applied to the gate electrode of the transistor 130. This is because the threshold value becomes lower than the apparent threshold value V _{th_L} . Here, the apparent threshold voltage refers to a potential of the wiring CL which is necessary to turn on the transistor 130. Therefore, the potential of the wiring CL is set to V _{t
By setting} the potential V ₀ between _{h_H} and V _{th_L} , the charge given to the gate electrode of the transistor 130 can be determined. For example, in writing, when high-level charge is applied, if the potential of the wiring CL becomes V ₀ (>V _{th_H} ), the transistor 1
30 is in the "on state". When the low-level charge is applied, the transistor 130 remains in the “off state” even when the potential of the wiring CL becomes V ₀ (<V _{th_L} ). Therefore, the held information can be read by determining the potential of the wiring SL. Note that in order to reduce the number of wirings, for example, WBL and RBL illustrated in FIG. 37A may be electrically connected.

When the memory cells are arranged and used in an array, it is necessary to read only the information of a desired memory cell. In such a case where the information is not read, a potential at which the transistor 130 is turned off regardless of the state of the gate electrode, that is, V _{th_H}
A smaller potential may be applied to the wiring CL. _{Alternatively} , a potential such that the transistor 130 is turned on regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be applied to the wiring CL.

The semiconductor device illustrated in FIG. 37B is mainly illustrated in FIG. 37 in that the transistor 130 is not provided.
It is different from (A). In this case also, information writing and holding operations can be performed by the same operation as described above.

Next, reading of information will be described. When the transistor 100 is turned on, the wiring BL which is in a floating state and the capacitor 150 are brought into conduction, and electric charge is redistributed between the wiring BL and the capacitor 150. As a result, the potential of the wiring BL changes. The amount of change in the potential of the wiring BL is
It takes different values depending on the potential of one electrode of the capacitor 150 (or the charge accumulated in the capacitor 150).

For example, the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, and the wiring B
When the capacitance component of L is CB, and the potential of the wiring BL before the charge is redistributed is VB0,
The potential of the wiring BL after the charge is redistributed is (CB×VB0+C×V)/(CB+C). Therefore, as the state of the memory cell, the potential of one electrode of the capacitor 150 is V1.
And V0 (V1>V0), the wiring BL in the case of holding the potential V1
Potential (=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the wiring BL (=(CB×VB0+C×V0)/(CB+C)) when the potential V0 is held. I understand.

Then, information can be read by comparing the potential of the wiring BL with a predetermined potential.

The semiconductor device illustrated in FIGS. 37A and 37B can be used as a memory device of a CPU, for example.

FIG. 38 shows an example of a cross-sectional structure of a semiconductor device which can realize the circuit shown in FIG. Note that FIG. 38 shows an example in which WBL and RBL are electrically connected in order to reduce the number of wirings. Note that FIG. 38B illustrates a cross section of a surface which is perpendicular to FIG. 38A and which passes through dashed-dotted line AB in FIG. 38A. Further, FIG. 38C passes through the dashed-dotted line CD shown in FIG.
8(A) shows a cross section of a plane perpendicular to FIG.

The transistor 100 is preferably provided above the transistor 130. By stacking the transistor 100 and the transistor 130, the circuit area can be reduced, for example. As the transistor 100, for example, the transistor described in Embodiment 3 can be used. 38 shows an example in which the transistor 100 shown in FIG. 12 is used.

The transistor 130 is configured to include the first semiconductor material. Also, the transistor 1
00 is configured to include the second semiconductor material. Examples of the semiconductor that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium, and arsenic; compound semiconductor materials containing silicon, germanium, gallium, arsenic, aluminum, and the like; An organic semiconductor material, an oxide semiconductor material, or the like can be given.

The first semiconductor material and the second semiconductor material may be the same material, but are preferably different semiconductor materials. Here, single crystal silicon is used as the first semiconductor material.
The case where an oxide semiconductor is used as the second semiconductor material will be described.

[First transistor]
The transistor 130 is provided in the semiconductor substrate 131 and includes a semiconductor layer 132 which is part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and a low resistance layer 133a and a low resistance layer 133b which function as a source region or a drain region. Have.

The transistor 130 may be either a p-channel type or an n-channel type, but an appropriate transistor may be used depending on a circuit configuration and a driving method.

A region such as a region where a channel of the semiconductor layer 132 is formed, a region in the vicinity thereof, and the low-resistance layer 133a and the low-resistance layer 133b which serve as a source region or a drain region preferably include a semiconductor such as a silicon-based semiconductor, and a single crystal. It preferably contains silicon. Or G
e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide),
It may be formed of a material having GaAlAs (gallium aluminum arsenide) or the like. A structure using silicon having a strain in the crystal lattice may be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 130 is replaced with a HEMT (High Electron Mob).
It may be an “Ility Transistor”.

In addition, the transistor 130 may include a region 176a and a region 176b which are LDD (Lightly Doped Drain) regions.

The low resistance layer 133a and the low resistance layer 133b include, in addition to the semiconductor material applied to the semiconductor layer 132, an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron. Including.

The gate electrode 135 is formed of an element that imparts n-type conductivity such as phosphorus, or a p-type element such as boron.
A semiconductor material such as silicon containing an element imparting mold conductivity, a metal material, an alloy material, or a conductive material such as a metal oxide material can be used.

Here, instead of the transistor 130, a transistor 190 as illustrated in FIGS. 29A and 29B may be used. FIG. 29B shows a cross section of a plane which passes through the alternate long and short dash line E-F shown in FIG. 29A and is perpendicular to FIG. 29A. In the transistor 190, a semiconductor layer 132 (a part of a semiconductor substrate) in which a channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along a side surface and an upper surface of the semiconductor layer 132. Further, an element isolation layer 181 is provided between the transistors. Such a transistor 190 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating film which functions as a mask for forming the protrusion may be provided in contact with the top of the protrusion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI (Silicon o
(n Insulator) substrate may be processed to form a semiconductor layer having a convex shape.

An insulating film 136, an insulating film 137, and an insulating film 138 are sequentially stacked to cover the transistor 130.

The insulating film 136 is used as the low resistance layer 133a and the low resistance layer 133 in a manufacturing process of a semiconductor device.
It functions as a protective film when the element imparting conductivity added to b is activated. Insulating film 13
6 may be omitted if unnecessary.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By performing the heat treatment, dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137, so that reliability of the transistor 130 can be improved.

The insulating film 138 functions as a planarization layer which planarizes a step generated by the transistor 130 and the like provided therebelow. The upper surface of the insulating film 138 may be flattened by a CMP method or the like.

Further, the insulating film 136, the insulating film 137, and the insulating film 138 include the low resistance layer 133a and the low resistance layer 1.
A plug 140 electrically connected to 33b and the like, a plug 139 electrically connected to the gate electrode 135 of the transistor 130, and the like may be embedded.

A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film 111 is a layer having a function of suppressing diffusion of water and hydrogen from the lower layer to the upper layer. Further, the barrier film 111 preferably has low oxygen permeability. Here, “difficult to diffuse water and hydrogen” means that the permeability of water and hydrogen is low as compared with, for example, silicon oxide generally used as an insulating film. The low oxygen permeability means that the oxygen permeability is low as compared with, for example, silicon oxide generally used as an insulating film.

Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST). ) Such as so-called h
The insulating film containing the high-k material can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, an oxynitride film may be formed by nitriding these insulating films. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating film and used. In particular, aluminum oxide is more preferable because it has an excellent barrier property against water and hydrogen.

In addition to the hydrogen and water, the above-mentioned materials have excellent barrier properties against oxygen. Therefore, oxygen released when the insulating film 114 is heated can be prevented from diffusing to a layer below the barrier film 111. As a result, the transistor 100 is released from the insulating film 114.
The amount of oxygen that can be supplied to the semiconductor layer can be increased.

Here, in the layer below the barrier film 111, it is preferable to reduce hydrogen, water, and the like by, for example, heat treatment. The heat treatment conditions may be, for example, 170° C. or higher in an inert gas atmosphere or a reduced pressure atmosphere.

In the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment includes treatment for terminating dangling bonds (also referred to as dangling bonds) of silicon with hydrogen (also referred to as hydrogenation treatment). Can be combined.

The conductive layer 151, the conductive layer 152a, and the conductive layer 152b are provided so as to sandwich the barrier film 111, and the capacitor 150 is formed. The conductive layer 151 is electrically connected to the conductive layer 104a of the transistor 100.

An insulating film 114 is provided so as to cover the barrier film 111, the conductive layer 152a, the conductive layer 152b, the conductive layer 105, and the like. For the insulating film 114, refer to the description of the insulating film 114 in FIG. 12, for example.

[Second transistor]
The transistor 100 is provided over the insulating film 114. In the example shown in FIG. 38, the transistor shown in FIG. 12 is used as the transistor 100.

In addition, the transistor 100 illustrated in FIG. 38 includes the conductive layer 1 which functions as a second gate electrode.
Have 05. The conductive layer 105 may be formed at the same time as the conductive layers 152a and 152b which form part of the capacitor 150. By forming these conductive layers at the same time, for example, the process can be simplified.

Further, an insulating film 112, an insulating film 113, and an insulating film 116 are provided so as to cover the transistor 100.

As with the barrier film 111, the insulating film 112 is preferably made of a material in which water and hydrogen are less likely to diffuse. In particular, it is preferable to use a material that hardly permeates oxygen.

Note that the insulating film 112 may have a stacked structure including two or more layers. In that case, for example, it is preferable that the insulating film 112 has a two-layer stacked structure and a material in which water and hydrogen are less likely to diffuse is used for the upper layer. For the lower layer, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used. The insulating film provided in the lower layer may be a structure similar to the insulating film 114 in which oxygen is released by heating, so that oxygen is also supplied from above the semiconductor layer 101 through the gate insulating film 102.

By covering the semiconductor layer 101 with the insulating film 112, release of oxygen from the semiconductor layer 101 to above the insulating film 112 can be suppressed. Further, oxygen released from the insulating film 114 and the like can be confined below the insulating film 112, so that the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

In addition, by providing the insulating film 112, entry of water or hydrogen into the oxide semiconductor from the outside can be suppressed. Therefore, a highly reliable transistor in which variation in electrical characteristics is suppressed can be realized.

As the insulating film 113, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and a stacked layer or a single layer is provided.

The insulating film 116 that covers the transistor 100 functions as a planarization layer that covers the uneven shape of the underlying layer. In addition, the insulating film 113 may have a function as a protective film when the insulating film 116 is formed. The insulating film 113 may be omitted if unnecessary. As the insulating film 116, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and the insulating film 116 is provided as a stacked layer or a single layer.

A plug 321, a plug 322, and a plug 123, which are electrically connected to the conductive layer 104b, are embedded in the insulating film 112, the insulating film 113, and the insulating film 116.

Wirings 124 and the like that are electrically connected to the plugs 322 are provided on the insulating film 116.

Further, as shown in FIG. 38, an insulating film 137 containing a material similar to that of the barrier film 111 may be provided over the insulating film 136 containing hydrogen. With such a structure, upward diffusion of water or hydrogen remaining in the insulating film 136 containing hydrogen can be effectively suppressed.

The wiring such as the wiring 124 and the wiring 166, the conductive layer 143, the conductive layer 151, the conductive layer 152a, the conductive layer 152b, the conductive layer such as the conductive layer 251, and the plug 123, the plug 139, and the plug 1
A conductive material such as a metal material, an alloy material, or a metal oxide material can be used for the plugs such as 40, the plug 164, and the plug 165. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, a material such as titanium nitride or titanium may be stacked with another material and used.

[Example of manufacturing method]
Next, an example of a method for manufacturing the semiconductor device in FIG. 38 is described with reference to FIGS.

First, the semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. An SOI substrate may be used as the semiconductor substrate 131. The case where single crystal silicon is used as the semiconductor substrate 131 will be described below.

Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. Element isolation layer is LOC
OS (Local Oxidation of Silicon) method or STI (Sh
It may be formed by using an allow Trench Isolation method, a mesa separation method, or the like.

When a p-type transistor and an n-type transistor are formed on the same substrate, the semiconductor substrate 1
An n well or p well may be formed in a part of 31. For example, an n-type semiconductor substrate 13
An n-type transistor and a p-type transistor may be formed on the same substrate by adding an impurity element such as boron imparting p-type conductivity to 1 to form a p-well.

Then, an insulating film to be the gate insulating film 134 is formed on the semiconductor substrate 131. For example,
The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, a stacked structure of a silicon oxide film and a silicon oxynitride film may be formed by nitriding the surface of the silicon oxide film by performing nitriding treatment after forming silicon oxide by a thermal oxidation method. Alternatively, silicon oxide, silicon oxynitride, tantalum oxide that is a high dielectric constant material (also referred to as a high-k material), hafnium oxide, hafnium oxide silicate, zirconium oxide,
A metal oxide such as aluminum oxide or titanium oxide, or a rare earth oxide such as lanthanum oxide may be used.

The insulating film is formed by a sputtering method or a CVD (Chemical Vapor Depo).
position (including thermal CVD method, MOCVD (Metal Organic CVD) method, PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo
regular Beam Epitaxy method, ALD (Atomic Layer)
Deposition method or PLD (Pulsed Laser Deposition)
Ion) method or the like.

Then, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or an alloy material or a compound material containing these metals as main components. Further, polycrystalline silicon to which impurities such as phosphorus are added can be used. Alternatively, a laminated structure of a metal nitride film and the above metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

The conductive film is formed by sputtering, vapor deposition, CVD (thermal CVD, MOCVD, PEC).
It is possible to form a film by a VD method or the like). In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

Then, a resist mask is formed over the conductive film by a lithography method or the like, and unnecessary portions of the conductive film are removed. After that, the resist mask is removed, whereby the gate electrode 135 can be formed.

Here, a method of processing the film to be processed will be described. As the processing method, various fine processing techniques can be used. For example, a method of performing slimming processing on a resist mask formed by photolithography or the like may be used. Alternatively, a dummy pattern may be formed by a photolithography method or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the film to be processed may be etched using the remaining sidewall as a resist mask. Moreover, in order to realize a high aspect ratio as etching of the processed film,
It is preferable to use anisotropic dry etching. Alternatively, a hard mask made of an inorganic film or a metal film may be used.

The light used for forming the resist mask is, for example, i-line (wavelength 365 nm), g-line (wavelength 43 nm).
6 nm), h-ray (wavelength 405 nm), or light obtained by mixing these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used.
Further, the exposure may be performed by a liquid immersion exposure technique. Further, as the light used for the exposure, EUV (Extreme Ultra-violet) or X-ray may be used. An electron beam may be used instead of the light used for exposure. Use of extreme ultraviolet light, X-rays, or electron beams is preferable because it enables extremely fine processing. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

Further, an organic resin film having a function of improving the adhesiveness between the film to be processed and the resist film may be formed before forming the resist film serving as the resist mask. The organic resin film can be formed, for example, by a spin coating method so as to cover the steps of the lower layer to flatten the surface, and the thickness of the resist mask provided in the upper layer of the organic resin film can vary. Can be reduced. Further, particularly when performing fine processing, it is preferable to use a material that functions as an antireflection film for the light used for exposure as the organic resin film. Examples of the organic resin film having such a function include BARC (Bottom Anti-Reflection).
Coating film. The organic resin film may be removed simultaneously with the removal of the resist mask, or may be removed after removing the resist mask.

After that, for the description of the processing using the resist mask, for example, the processing method described for the gate electrode 135 may be referred to. Further, in this specification, the description of resist removal after etching the film to be processed may be omitted.

After forming the gate electrode 135, a sidewall that covers the side surface of the gate electrode 135 may be formed. The sidewall is formed by forming an insulating film thicker than the thickness of the gate electrode 135,
It can be formed by performing anisotropic etching and leaving the insulating film only on the side surface portion of the gate electrode 135.

Although FIG. 39 shows an example in which the gate insulating film is not etched when the sidewall is formed, the insulating film to be the gate insulating film 134 may be simultaneously etched when the sidewall is formed. In this case, the gate insulating film 134 is formed below the gate electrode 135 and the sidewall.

Subsequently, an element that imparts n-type conductivity such as phosphorus or an element that imparts p-type conductivity such as boron is added to a region of the semiconductor substrate 131 where the gate electrode 135 (and the sidewall) is not provided. To do. A schematic cross-sectional view at this stage corresponds to FIG.

Subsequently, after the insulating film 136 is formed, heat treatment for activating the above-described element imparting conductivity is performed, for example. The heat treatment can be performed in an inert gas atmosphere such as a rare gas or a nitrogen gas or in a reduced pressure atmosphere, for example, at 400 °C or higher and lower than the strain point of the substrate.

For the insulating film 136, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and the insulating film 136 is provided as a stacked layer or a single layer. The insulating film 136 can be formed by a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce plasma damage, thermal CVD method, MOCVD method or A
The LD method is preferred.

At this stage, the transistor 130 is formed. Further, the third transistor 160 may be formed by a method similar to that of forming the transistor 130.

Then, the insulating film 137 and the insulating film 138 are formed.

The insulating film 137 may be formed using silicon nitride containing oxygen and hydrogen (SiNOH) in addition to the material that can be used for the insulating film 136. In addition to the materials that can be used for the insulating film 136, the insulating film 138 includes TEOS (Tetra-Ethyl-Ortho-Sili).
Cate) or silane or the like and silicon oxide formed by reacting oxygen or nitrous oxide or the like with good step coverage is preferably used.

The insulating film 137 and the insulating film 138 are formed, for example, by a sputtering method, a CVD method (a thermal CVD method,
MOCVD method, PECVD method and the like), MBE method, ALD method or PLD method can be used. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

Then, the upper surface of the insulating film 138 is planarized by using the CMP method or the like. A flattening film may be used as the insulating film 138. In that case, it is not always necessary to flatten by the CMP method or the like.
For forming the flattening film, for example, a normal pressure CVD method or a coating method can be used. Normal pressure C
The film that can be formed by the VD method is, for example, BPSG (Boron Phosphor).
us Silicate Glass) and the like. In addition, examples of the film that can be formed by using the coating method include HSQ (hydrogen silsesquioxane). After that, heat treatment for terminating dangling bonds in the semiconductor layer 132 with hydrogen which is released from the insulating film 137 may be performed.

Then, an opening reaching the low resistance layer 133a, the low resistance layer 133b, the gate electrode 135, and the like is formed in the insulating film 136, the insulating film 137, and the insulating film 138 (see FIG. 39B). After that, a conductive film is formed so as to fill the opening (see FIG. 39C). Then, the insulating film 138
By planarizing the conductive film so that the upper surface of the plug is exposed, the plug 139, the plug 140, and the like are formed (see FIG. 39D). The conductive film can be formed by a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

Then, the insulating film 215 is formed over the insulating film 138. The insulating film 215 can be formed using a material and a method similar to those of the insulating film 136 and the like. After forming the insulating film 215, heat treatment may be performed.

The third heat treatment can be performed under the conditions illustrated in the above description of the stacked structure. For example, the conditions described in the first heat treatment can be used.

Then, an opening is formed in the insulating film 215. After that, a conductive film is formed so as to fill the opening, and the conductive film is planarized so that the upper surface of the insulating film 215 is exposed, whereby the conductive layers 251, 143, 151, and the like are formed. (See FIG. 39E). When the conductive film is formed in the opening, for example, a material such as titanium nitride or titanium may be formed in the opening and then another conductive material may be laminated. For example, by using titanium nitride or titanium as the lower layer of the laminated film, the adhesion to the opening can be improved.

Then, a barrier film 111 is formed and an opening is formed (see FIG. 40A). The barrier film 111 is formed of, for example, a sputtering method, a CVD method (a thermal CVD method, a MOCVD method, a PECVD method).
Method, etc.), MBE method, ALD method, PLD method, or the like.
In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

Then, a conductive film to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b is formed.
After that, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see FIG. 40B).

Next, the insulating film 114 is formed. The insulating film 114 is, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method or a PL.
It can be formed by using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

In order to make the insulating film 114 contain excess oxygen, the insulating film 11 may be formed in an oxygen atmosphere, for example.
4 may be formed. Alternatively, oxygen may be introduced into the formed insulating film 114 to form a region containing excess oxygen, or both means may be combined.

For example, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after the film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Or
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

In addition, after the insulating film 114 is molded, planarization treatment using a CMP method or the like may be performed in order to improve flatness of the upper surface of the insulating film 114.

Next, a semiconductor film to be the insulator layer 101a and a semiconductor film to be the semiconductor layer 101b are sequentially formed (see FIG. 40C). The semiconductor film is preferably formed continuously without being exposed to the air. The semiconductor to be the insulator layer 101a and the semiconductor to be the semiconductor layer 101b may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Note that as a semiconductor to be the insulator layer 101a and a semiconductor to be the semiconductor layer 101b, I
When the n-Ga-Zn oxide layer is formed by MOCVD, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as a source gas. Note that the combination of the above source gases is not limited, and triethylindium or the like may be used instead of trimethylindium. Moreover, you may use triethyl gallium etc. instead of trimethyl gallium. Further, diethyl zinc or the like may be used instead of dimethyl zinc.

Here, oxygen may be introduced into the insulator layer 101a after the insulator layer 101a is formed. For example, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after the film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Or
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

After the insulator layer 101a and the semiconductor layer 101b are formed, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. The heat treatment may be performed in an inert gas atmosphere and then in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement desorbed oxygen. The heat treatment may be performed immediately after the semiconductor film is formed, or the semiconductor film is processed to form island-shaped insulator layers 101a and 101b.
You may carry out after forming. By the heat treatment, oxygen is supplied to the semiconductor film from the insulating film 114 or the oxide film, so that oxygen vacancies in the semiconductor film can be reduced.

After that, the island-shaped insulator layer 101a and the island-shaped semiconductor layer 101b are formed using a resist mask.
The laminated structure is formed (see FIG. 40D). Note that when the semiconductor film is etched, part of the insulating film 114 may be etched and the insulating film 114 in a region not covered with the insulator layer 101a and the semiconductor layer 101b may be thinned. Therefore, it is preferable that the insulating film 114 be formed thick in advance so that the insulating film 114 does not disappear by the etching.

Depending on the etching conditions of the semiconductor film, the resist may disappear during the etching process, so a so-called hard mask made of a material having high etching resistance, for example, an inorganic film or a metal film may be used. Here, an example of using a conductive film as the hard mask 281 is shown. 41A illustrates an example in which the semiconductor film is processed using the hard mask 281 to form the insulator layer 101a and the semiconductor layer 101b. Here, if a material that can be used for the conductive layers 104a and 104b is used for the hard mask 281, the hard mask 281 can be processed to form the conductive layers 104a and 104b. By using such a method, the transistor 100 illustrated in FIG. 30, for example, can be manufactured.

After the structure illustrated in FIG. 40D is formed, an opening reaching the conductive layer 151, the conductive layer 251, and the like is provided in the insulating film 114 (see FIG. 41B). After that, a conductive film to be the conductive layer 104a, the conductive layer 104b, or the like is formed so as to fill the opening provided in the insulating film 114. Conductive layer 1
04a, the conductive layer 104b and the like are formed by, for example, a sputtering method, a CVD method (
(Including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PLD
It can be formed using a method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

Next, using a resist mask, unnecessary portions of the conductive film to be the conductive layers 104a, 104b, and the like are removed by etching to form the conductive layers 104a, 104b, and the like (
41C). Here, when the conductive film is etched, the semiconductor layer 101b and the insulating film 1
A part of the upper part of 14 may be etched, and a part which does not overlap with the conductive layers 104a and 104b may be thinned. Therefore, the thickness of the semiconductor film or the like to be the semiconductor layer 101b is
It is preferable to form a thick film in advance in consideration of the etching depth.

Next, the insulator layer 101c and the gate insulating film 102 are formed. After that, etching is performed using the resist mask (see FIG. 42A). Next, a conductive film to be the gate electrode 103 is formed, and the conductive film is processed using a resist mask to form the gate electrode 103 (see FIG. 42B).

Note that for the method for forming the insulator layer 101c, the insulator layer 101a may be referred to, for example.

Further, oxygen may be introduced into the insulating layer 101c after the insulating layer 101c is formed. For example, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101c after the film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Or
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

At this stage, the transistor 100 is formed.

Next, the insulating film 112 is formed. The insulating film 112 is, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method or a PL.
It can be formed by using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

After the insulating film 112 is formed, heat treatment may be performed. By the heat treatment, oxygen can be supplied from the insulating film 114 or the like to the semiconductor layer 101, so that oxygen vacancies in the semiconductor layer 101 can be reduced.

Further, the insulating film 112 may have a stacked structure including two or more layers.

Then, the insulating film 113 is formed. The insulating film 113 is formed by, for example, a sputtering method or CVD.
Method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed by using the LD method or the like. In particular, CVD method, preferably plasma CVD
It is preferable to form a film by the method because the coverage can be improved. In order to reduce the damage due to plasma, the thermal CVD method, MOCVD method or ALD method is preferable.

Then, the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulator layer 101c are
An opening reaching the conductive layer 104a and the like is provided. Then, after forming a conductive film so as to fill the opening, unnecessary portions are removed using a resist mask to form plugs 321 and 322.

Then, the insulating film 116 is formed. The insulating film 116 is formed by, for example, a sputtering method or CVD.
Method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed by using the LD method or the like. When an organic insulating material such as an organic resin is used for the insulating film 116, a coating method such as a spin coating method may be used. Further, it is preferable to perform planarization treatment on the upper surface of the insulating film 116 after the insulating film 116 is formed. Further, as the insulating film 116, the material shown in the insulating film 138 or the formation method may be used.

Then, the plug 12 reaching the plug 322 is formed on the insulating film 116 by the same method as described above.
3 etc. are formed.

Then, a conductive film is formed over the insulating film 116. After that, unnecessary portions of the conductive film are removed by etching using a resist mask by a method similar to that described above, so that the wiring 124 and the like can be formed.

Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, an example of a circuit including the transistor of one embodiment of the present invention will be described with reference to the drawings.

[Circuit configuration example]
In the structure shown in the semiconductor device to which Embodiment 1 is applied, various circuits can be formed by changing connection structures of transistors, wirings, and electrodes. Hereinafter, an example of a circuit structure which can be realized by using the semiconductor device of one embodiment of the present invention will be described.

[CMOS circuit]
The circuit diagram in FIG. 37C is a so-called CM in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
The configuration of the OS circuit is shown. Note that, in the drawing, a transistor to which the second semiconductor material is applied is indicated by the symbol "OS". Here, the CMOS circuit shown in this embodiment has N
AND circuit, NOR circuit, encoder, decoder, MUX (multiplamplif)
ier), DEMUX (demultiplexer), and the like can be used as a basic element of a logic circuit.

[Analog switch]
The circuit diagram in FIG. 37D illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With this configuration,
It can function as a so-called analog switch.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, a display module including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

The display module 8000 shown in FIG. 27 includes a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, and a printed board 801 between an upper cover 8001 and a lower cover 8002.
0, the battery 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and size of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

As the touch panel 8004, a touch panel of a resistance film type or a capacitance type can be used by being superimposed on the display panel 8006. Alternatively, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, the display panel 8
It is also possible to provide an optical sensor in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008. Note that although FIG. 27 illustrates the structure in which the light source 8008 is provided over the backlight 8007, the invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007 and a light diffusion plate may be used. Note that in the case of using a self-luminous light emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function of protecting the display panel 8006 and a function of an electromagnetic shield for blocking an electromagnetic wave generated by the operation of the printed board 8010. The frame 8009 may also have a function as a heat dissipation plate.

The printed circuit board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply by a battery 8011 provided separately. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate and a prism sheet.

The display module 8000 described in this embodiment may have flexibility. Since it has flexibility, it can be pasted on a curved surface or an irregular shape, and various uses can be realized.

The structure described in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

(Embodiment 9)
In this embodiment, an R including the transistor or the memory device described in any of the above embodiments is used.
The F tag will be described with reference to FIG.

The RF tag in this embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using a non-contact means such as wireless communication. Due to such characteristics, the RF tag can be used in an individual authentication system or the like for identifying an item by reading individual information of the item or the like. Note that extremely high reliability is required for use in these applications.

The structure of the RF tag will be described with reference to FIG. FIG. 28 is a block diagram showing a configuration example of an RF tag.

As shown in FIG. 28, the RF tag 800 includes an antenna 804 that receives a wireless signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). Further, the RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that the demodulation circuit 807 may have a structure in which a transistor which has a rectifying function and which can sufficiently suppress reverse current is used, for example, an oxide semiconductor. As a result, it is possible to suppress a decrease in the rectification action caused by the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made close to linear. There are three major data transmission methods: an electromagnetic coupling method in which a pair of coils are arranged opposite to each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which radio waves are used for communication. Be separated. The RF tag 800 described in this embodiment can be used for any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a wireless signal by the antenna 804, for example, rectifies a half-wave double voltage, and rectifies the signal rectified by a capacitor element provided in a subsequent stage. This is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so that electric power of a certain electric power or more is not input to the circuit in the subsequent stage when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to make the logic circuit 8
This is a circuit for generating a reset signal of 09.

The demodulation circuit 807 is a circuit for demodulating the input AC signal by envelope detection and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing the demodulated signal and performing processing. The memory circuit 810 is a circuit which holds input information and includes a row decoder, a column decoder, a memory area, and the like. Further, the ROM 811 is a circuit for storing a unique number (ID) and the like, and outputting according to processing.

The above-mentioned circuits can be appropriately discarded as necessary.

Here, the memory circuit described in any of the above embodiments can be used for the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain information even when power is off, it can be preferably used for an RF tag. Further, in the memory circuit of one embodiment of the present invention, electric power (voltage) required for writing data is significantly smaller than that of a conventional nonvolatile memory; thus, a difference in maximum communication distance between reading data and writing data is not generated. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.

The memory circuit of one embodiment of the present invention can be used as a nonvolatile memory and thus can be applied to the ROM 811. In this case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command. By shipping the product after the manufacturer writes the unique number before shipping, it is possible to assign the unique number only to the good product to be shipped, instead of assigning the unique number to all the manufactured RF tags, The unique number of the product after shipment does not become discontinuous, and the customer management corresponding to the product after shipment becomes easy.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 10)
A semiconductor device according to one embodiment of the present invention is an image reproducing device including a display device, a personal computer, and a recording medium (typically a DVD: Digital Versatile Disc).
It can be used for a device having a display capable of reproducing a recording medium such as c and displaying an image thereof. In addition, as electronic devices in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book, a video camera,
Cameras such as digital still cameras, goggle type displays (head mounted displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction machines, automatic teller machines (ATM). ), vending machines and the like. Specific examples of these electronic devices are shown in FIGS.

FIG. 57A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, and a stylus 90.
Has 8 mag. Note that although the portable game machine illustrated in FIG. 57A includes two display portions 903 and 904, the number of display portions included in the portable game machine is not limited to this.

FIG. 57B shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. First display section 91
3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. is there. The image on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915. Further, a display device in which a function as a position input device is added to at least one of the first display unit 913 and the second display unit 914 may be used. The function as the position input device can be added by providing a touch panel on the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element also called a photosensor in the pixel portion of the display device.

FIG. 57C illustrates a laptop personal computer, which includes a housing 921, a display portion 922,
It has a keyboard 923, a pointing device 924, and the like.

FIG. 57D shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 9.
It has 33 etc.

FIG. 57E illustrates a video camera, which includes a first housing 941, a second housing 942, and a display portion 943.
, Operation keys 944, a lens 945, a connecting portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. is there. The image on the display unit 943 is displayed on the first housing 941 and the second housing 94 on the connection unit 946.
The configuration may be switched according to the angle between the two.

FIG. 57F shows an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953,
It has a light 954 and the like.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 11)
In this embodiment, an example of using the RF tag of one embodiment of the present invention will be described with reference to FIGS. The RF tag has a wide range of uses, but for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 56(A)), packaging containers (wrapping paper, 56C), recording medium (DVD, video tape, etc., see FIG. 56B), vehicles (bicycle, etc., see FIG. 56D), personal items (bags, glasses, etc.) , Food,
Plants, animals, humans, clothing, daily necessities, medical products including medicines and drugs, or electronic devices (
It can be used by being provided on an article such as a liquid crystal display device, an EL display device, a television device, or a mobile phone, or a tag attached to each article (see FIGS. 56E and 56F).

By attaching or embedding the RF tag 4000 according to one embodiment of the present invention on the surface,
Fixed to the item. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention realizes a small size, a thin shape, and a light weight, and thus does not deteriorate the design of the article itself even after being fixed to the article. Further, by providing the RF tag 4000 according to one embodiment of the present invention on banknotes, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, Counterfeiting can be prevented. Further, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal belongings, foods, clothes, household goods, electronic devices, and the like, efficiency of systems such as inspection systems can be improved. Can be planned. Further, even in vehicles, by attaching the RF tag according to one embodiment of the present invention, security against theft or the like can be improved.

As described above, by using the RF tag of one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of data can be reduced, so that the maximum communication distance can be long. Is possible. In addition, since information can be retained for an extremely long period even when power is cut off, it can be preferably used for applications in which writing and reading are infrequent.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

Note that a diagram (or part of it) described in one embodiment is another part of the diagram, another diagram (or part) described in the embodiment, and/or one or more. More drawings can be formed by combining the drawings described in another embodiment of FIG.

Note that one embodiment of the invention can be configured in which it is stipulated that the content not specified in the drawings or the text in the specification is excluded. Alternatively, if a numerical range indicated by an upper limit value and a lower limit value, etc. is stated for a certain value, the range can be narrowed by arbitrarily narrowing the range or excluding one point in the range. It is possible to define one aspect of the excluded invention. From these, for example, it can be defined that the related art does not fall within the technical scope of one aspect of the present invention.

As a specific example, a circuit diagram in which first to fifth transistors are used in a circuit is described. In that case, it can be specified as an invention that the circuit does not include the sixth transistor. Alternatively, it can be specified that the circuit does not include a capacitor. Further, the invention can be configured by defining that the circuit does not include the sixth transistor having a specific connection structure. Alternatively, the invention can be configured by defining that the circuit does not include a capacitor element having a specific connection structure. For example, it may be possible to define the invention as having no sixth transistor whose gate is connected to the gate of the third transistor.
Alternatively, for example, the invention can be specified such that the first electrode does not include a capacitor connected to the gate of the third transistor.

As another specific example, regarding a property of a certain substance, for example, “a certain film is an insulating film”.
Is described. In that case, for example, it is possible to define that the insulating film is not an organic insulating film, which is one embodiment of the invention. Alternatively, for example, one embodiment of the invention can be specified to exclude the case where the insulating film is an inorganic insulating film. Alternatively, for example, the case where the film is a conductive film can be excluded, and one embodiment of the invention can be specified. Alternatively, for example, it is possible to specify that the film is not a semiconductor film, which is one embodiment of the invention.

As another specific example, it is assumed that a certain laminated structure is described as "a certain film is provided between the A film and the B film". In that case, for example, the invention can be defined as excluding the case where the film is a laminated film of four or more layers. Alternatively, for example, the invention can be specified to exclude the case where a conductive film is provided between the A film and the film.

Note that in this specification and the like, one part of a diagram or a text described in one embodiment can be taken out to form one embodiment of the invention. Therefore, in the case where a diagram or a sentence which describes a certain portion is described, the extracted content of the diagram or the sentence of the part is also disclosed as one embodiment of the invention, and may constitute one embodiment of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operating methods, manufacturing methods In a drawing or a text in which a single or a plurality of the above are described, a part of the drawing or the text can be taken out to constitute one embodiment of the invention. For example, N (N
Is an integer) and M (where M is an integer, M<N) circuit elements (transistors, capacitive elements, etc.) are extracted from the circuit diagram configured to have circuit elements (transistors, capacitive elements, etc.), It is possible to form one aspect of the invention. As another example, M (M is an integer and M<N) layers are extracted from a cross-sectional view including N layers (N is an integer) to form one embodiment of the invention. It is possible to do so. As still another example, M (M is an integer and M<N) elements are extracted from a flowchart configured with N (N is an integer) elements to form one embodiment of the invention. It is possible to do so. As still another example, some elements are arbitrarily extracted from the sentence described as "A has B, C, D, E, or F", and "A is B and E". "Has,""A has E and F,""A has C, E, and F."
Alternatively, one aspect of the invention such as “A has B, C, D, and E” can be configured.

Note that in this specification and the like, when at least one specific example is described in a diagram or a text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. Be understood by. Therefore, when at least one specific example is described in a drawing or a text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. And it can be said that one aspect of the invention is clear.

In this specification and the like, at least the contents described in the drawings (a part of the drawings may be included)
Is disclosed as one aspect of the invention, and one aspect of the invention can be configured. Therefore, as long as some content is described in the drawings, the content is disclosed as one embodiment of the invention even if it is not described using a sentence, and may form one embodiment of the invention. It is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and one embodiment of the invention can be constituted. And
It can be said that one aspect of the invention is clear.

In this example, evaluation results of the oxide semiconductor film which is one embodiment of the present invention will be described.

[Production method]
The silicon wafer was thermally oxidized to form a silicon oxide film having a thickness of 100 nm. After that, as the oxide semiconductor film, an In—Ga—Zn oxide with a thickness of 100 nm was formed by a sputtering method. As a condition of the sputtering method, a target is a polycrystalline In—Ga—Zn oxide of In:Ga:Zn=1:1:1 (atomic ratio), a power source is 0.5 kW (DC), and a substrate is used. The distance between the targets was 60 mm. Argon and oxygen are used as a film forming gas,
The respective flow rates were 30 sccm for argon and 15 sccm for oxygen. Pressure is 0.4
It was Pa. The substrate temperature was 170° C. for sample E1-1 and 300° C. for sample F1-1.

Next, heat treatment was performed. The heat treatment was performed at 450° C. in a nitrogen atmosphere for 1 hour, and then in the same treatment chamber at 450° C. in an oxygen atmosphere for 1 hour.

[XRD evaluation]
Next, the result of evaluation using the XRD device will be described. The XRD device is a multi-functional thin film material evaluation X-ray diffraction device D8 DISCOVER Hybrid (manufactured by Bruker AXS).
Was used to evaluate each sample. FIG. 43 shows the analysis result by the Out-Of-Plane method. 43A shows the results of the sample E1-1 and FIG. 43B shows the results of the sample F1-1. A peak was observed near 2θ=31° in all the samples. The peak was broad under the conditions of film formation at 170° C., and the peak tended to be sharper under the conditions of film formation at 300° C. Since this peak is assigned to the (009) plane of the InGaZnO ₄ crystal, it is suggested that the crystal of the oxide semiconductor film having c-axis orientation is increased by increasing the film formation temperature.

[Film density evaluation]
Next, the film density was measured. XRR (X-ray reflectance method: X-ray R
eflectry) was used. The obtained film density was 6.18 [g for Sample E1-1.
/Cm ³ ], and the sample F1-1 had 6.36 [g/cm ³ ]. A dense and good film was obtained under any of the conditions.

[Nanobeam electron diffraction]
Next, the samples E1-1 and F1-1 were analyzed by nanobeam electron diffraction. "HF-2000" manufactured by Hitachi High-Technologies Corporation was used for acquisition of electron diffraction. The acceleration voltage was 200 kV.

The transmission electron diffraction pattern was acquired while moving the sample stage little by little and scanning with respect to the upper surface of each sample which has an oxide semiconductor film. Electron beam has a probe diameter of 1 nm
Nanobeam electron beam was used. In addition, the same measurement was performed at three points for each sample. That is, in each sample, scan 1 to scan 3 was performed three times in total.

A diffraction pattern was observed while scanning at a speed of 5 nm/sec to acquire a moving image. next,
The diffraction pattern observed in the obtained moving image was converted into a still image every 0.5 seconds. The converted still image was analyzed and classified into three patterns, that is, the pattern of the nc-OS film, the pattern of the CAAC-OS film, and the pattern of the spinel type crystal structure. Table 3 shows the number of images classified into each pattern in Scan1 to Scan3 for the sample E1-1 and the sample F1-1. Further, the results of scan1 of the electron diffraction pattern of Sample E1-1 are shown in FIGS.
The results of scan-1 of -1 are shown in FIGS. 49 to 53. Further, among the results of electron diffraction shown in FIGS. 44 to 48, the ones judged to be the patterns of the CAAC-OS film are surrounded by a broken line and shown. Further, among the results of electron diffraction shown in FIGS. 49 to 53, the ones judged to be the pattern of the nc-OS film are surrounded by a broken line and shown.

In sample E1-1, the nc ratio showed a high value of 90% or more. It was found that the nc ratio was further increased by lowering the film forming temperature. In addition, in any sample, n
The sum of the c ratio and the CAAC ratio was 100%.

In this example, the film density evaluation result of In-Ga-Zn oxide and TDS (Thermal) were obtained.
The result of Desorption Spectroscopy: thermal desorption spectroscopy is shown.

An In-Ga-Zn oxide film was formed by a sputtering method on a quartz substrate that had been washed in advance. The target is polycrystalline In- of In:Ga:Zn=1:1:1 (atomic ratio).
Ga-Zn oxide was used. The film formation conditions were that the power supply was 100 W, argon and oxygen were used as film formation gases, and the flow rate of oxygen gas was 2 with respect to the total flow rate of argon gas and oxygen gas.
The flow rate was adjusted to be %. The pressure was 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. Table 4 shows film forming conditions and film density. sampleB and sample
For D, an In—Ga—Zn oxide film was formed by a sputtering method, and then heat treatment was performed at 450° C. XRR was used to evaluate the film density. As shown in Table 4, the density of sampleC showed a high value of 6 [g/cm ³ ] or more.

Next, TDS analysis was performed on sampleA to sampleD. Molecular weight is 1
The released amount of degas of No. 8 is shown in FIGS. 54(A) and (B). The outgassing with a molecular weight of 18 is considered to originate from H ₂ O. The amount of release was large in sampleA, and the amount of release was reduced in sampleB which was heat-treated. It is considered that sampleC, which has a high film density, has a small amount of released gas even if heat treatment is not performed, and the amount of water contained in the film is small.

Next, regarding sampleA to sampleD, the crystal size (
The change in crystal size) was evaluated. The crystal size was calculated by observing the cross section using TEM. FIG. 55 shows the result of evaluating the relationship between the cumulative irradiation amount and the crystal size by performing electron beam irradiation using TEM. In sampleA, the crystals tended to become larger each time the electron beam irradiation was performed. Here, the crystal size before the electron beam irradiation may be set to a value at which the cumulative irradiation amount is 0 [e ⁻ /nm ² ] in the approximate line shown in FIG. 55, for example. In sample B that was heat-treated, the change in crystal size was small. In addition, sample C and sample with high film density
In D, the crystal size was not significantly changed in the range of the cumulative irradiation dose of electron beams up to 4.2×10 ⁸ [e ⁻ /nm ² ].

In this example, the stability of the oxide semiconductor film was evaluated. Sample 1, Sample 2 and Sample 3
The manufacturing method of is shown below.

First, a 100 nm-thick In-Ga-Z film was formed on a quartz substrate by RF sputtering.
An n oxide is deposited. The target is a polycrystalline In-Ga-Zn oxide (In:Ga:Z).
n=1:1:1 [atomic ratio]) was used. As the film forming gas, oxygen gas was 2 sccm and argon gas was 98 sccm. Moreover, the power was 100 W. The substrate temperature during film formation was room temperature. Here, the sample 1 had a film forming pressure of 0.4 Pa. In addition, Sample 2 had a film forming pressure of 1.0 Pa.

In Sample 3, a 100-nm-thick In-Ga film was formed on a quartz substrate by DC sputtering.
-Zn oxide film is formed. The target is an In-Ga-Zn oxide (In:Ga:Zn=
1:1:1 [atomic ratio]) was used. As the film forming gas, oxygen gas was 10 sccm and argon gas was 20 sccm. In addition, the power was 200W. The substrate temperature during film formation was 300°C. The film forming pressure was 0.4 Pa.

Next, heat treatment was performed for 1 hour in an atmosphere containing oxygen and nitrogen. Heat treatment temperature is 25
Five conditions of 0°C, 300°C, 350°C, 400°C, and 450°C were set. After that, the film densities of Sample 1, Sample 2, and Sample 3 were measured including the condition that the heat treatment was not performed. The film density is measured by XRR by an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS.
Was used. The results of Sample 1 are shown in FIG. 58(A), the results of Sample 2 are shown in FIG. 58(B), and the results of Sample 3 are shown in FIG. 58(C). The horizontal axis represents the temperature of heat treatment. The film density of sample 1 is 5.9 g/c
It was from m ³ to 6.1 g/cm ³ . The film density of Sample 2 is 5.6 g/cm ³ to 5.8 g/
It was in the range of cm ³ . The film density of Sample 3 was in the range of 6.2 g/cm ³ to 6.4 g/cm ³ .

Next, Sample 1, Sample 2, and Sample 3 were etched using an aqueous solution prepared by diluting phosphoric acid 100 times with pure water. Then, the etching rate was measured by measuring the thickness before and after etching. The result of Sample 1 is shown in FIG. 59(A), the result of Sample 2 is shown in FIG. 59(B), and the result of Sample 3 is shown in FIG. 59(C). It was found that the higher the heating temperature of Sample 1 and Sample 2, the lower the etching rate. It was found that Sample 3 had a small difference due to the temperature of the heat treatment. In addition, the sample 1 not subjected to the heat treatment is better than the sample 2 subjected to the heat treatment.
It was found that the etching rate was lowered. Further, it was found that the sample 3 not subjected to the heat treatment had a lower etching rate than the sample 1 subjected to the heat treatment.

Next, Sample 1, Sample 2, and Sample 3 were subjected to TDS analysis to measure the amount of degassed (water) released with a mass-to-charge ratio of 18. For the TDS analysis, a thermal desorption analyzer TDS-12 manufactured by Electronic Science Co., Ltd.
00 was used. The result of Sample 1 is shown in FIG. 60A, the result of Sample 2 is shown in FIG.
The result is shown in FIG. 60(C). It was found that in Sample 1, Sample 2, and Sample 3, the higher the temperature of the heat treatment, the smaller the released amount of outgas with a mass-to-charge ratio of 18. Further, it was found that the sample 1 which was not subjected to the heat treatment had a smaller amount of released degas with a mass-to-charge ratio of 18 than the sample 2 which was subjected to the heat treatment. Further, it was found that the sample 3 which was not subjected to heat treatment had a smaller amount of released degas with a mass-to-charge ratio of 18 than the sample 1 which was subjected to heat treatment.

Next, the hydrogen concentrations of Sample 1 and Sample 2 were measured. The hydrogen concentration was measured by SIMS.
As SIMS, IMS 7fR manufactured by CAMECA was used. The results of Sample 1 are shown in FIGS. 61(A) and 68(A), and the results of Sample 2 are shown in FIGS. 61(B) and 68(B). here,
68A and 68B, the horizontal axis represents the depth from the film surface and the vertical axis represents the hydrogen concentration. Further, FIGS. 61A and 61B show average values of hydrogen concentration from a depth of 10 nm to 60 nm. In addition, in FIGS. 68A and 68B, the quartz substrate was measured without the In—Ga—Zn oxide film remaining after the region where the hydrogen concentration drastically changed near the depth of 80 nm. There is a possibility that Further, in a region of less than 10 nm, there is a possibility of being affected by the surface condition. Therefore, the hydrogen concentration of the In-Ga-Zn oxide film is, for example, 10
It is preferable to represent the average value from nm to 60 nm. It was found that in Samples 1 and 2, the higher the heat treatment temperature, the lower the hydrogen concentration. Further, it was found that the sample 1 not subjected to the heat treatment had a lower hydrogen concentration than the sample 2 subjected to the heat treatment.

Next, the change in crystal size due to the heat treatment of Sample 1, Sample 2, and Sample 3 was measured by TEM. The crystal size is shown as an average value of 20 to 45 points. As the TEM, Hitachi Transmission Electron Microscope H-9000NAR was used. The result of Sample 1 is shown in FIG. 62(A), and the result of Sample 2 is shown in FIG.
The results of Sample No. 2 (B) and Sample 3 are shown in FIG. 62(C). It was found that Sample 1 had a crystal size of about 1.4 nm regardless of the temperature of the heat treatment. Sample 2 had a crystal size of about 1.2 nm when not subjected to heat treatment (see FIG. 67), but grew to about 1.3 nm by heat treatment at 250° C., and further heated at 300° C. It grew to about 1.6 nm by the treatment. Further, no change was observed in the crystal size in the range of 300°C to 450°C. Further, also in Sample 3, the crystal size is 1.5 to 1.6 nm regardless of the temperature of the heat treatment.
Met.

Next, changes in crystal size of Sample 1, Sample 2, and Sample 3 due to electron beam irradiation were measured by TEM. The result of Sample 1 is shown in FIG. 63(A), the result of Sample 2 is shown in FIG. 63(B), and the result of Sample 3 is shown in FIG. 63(C). The sample 1 and the sample 3 showed almost no change in the crystal size regardless of the temperature of the heat treatment and also by the electron beam irradiation. Sample 2 showed an increase in crystal size due to electron beam irradiation. This tendency was more remarkable as the temperature of the heat treatment was lower.

Looking at the change in crystal size due to heat treatment and the change in crystal size due to electron beam irradiation,
It can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When the sample 1, the sample 2, and the sample 3 are compared with the classification of the structure described above, the sample 1 becomes the nc-OS film, the sample 2 becomes the a-like OS film, and the sample 3 becomes the CAAC-OS.

Thus, the nc-OS film has a higher film density, a lower etching rate, less degassing of water, and a lower hydrogen concentration than the a-like OS film. Further, the difference cannot be filled by heat treatment after film formation. That is, it is important to use an oxide semiconductor film which is an nc-OS film for forming a transistor.

In this example, the localized level of the nc-OS film was evaluated. The evaluation of the localized level is performed by CPM (Con
It was carried out by stan photocurrent method measurement.

For the CPM measurement, a gate electrode (tungsten) on the glass substrate and nc- on the gate electrode are used.
An OS film, a gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film, n
A pair of electrodes (a stacked body formed of tungsten, aluminum, and titanium in this order) in contact with the c-OS film, and an insulator (silicon oxynitride and silicon nitride formed in this order on the nc-OS film and the pair of electrodes). And a laminated body) were prepared. In addition, nc-OS
The film was formed by an AC sputtering method with a thickness of 35 nm. The target is In
A —Ga—Zn oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) was used. As the film forming gas, 10% by volume of oxygen gas and 90% by volume of argon gas were used. Also, the power is 2
． It was set to 5 kW. The substrate temperature during film formation was room temperature. The film forming pressure was 0.6 Pa.

Next, heat treatment was performed on the manufactured sample. The heat treatment was performed in a nitrogen atmosphere for 1 hour and then in an atmosphere containing oxygen and nitrogen for 1 hour.

The CPM measurement is performed by adjusting the amount of light applied to the sample surface between the terminals so that the photocurrent value becomes constant with a voltage applied between a pair of electrodes provided in contact with the nc-OS film. Derive the absorption coefficient. Here, the absorption coefficient is derived at each wavelength. In the CPM measurement, the absorption coefficient at energy (converted from wavelength) corresponding to the localized level density increases. The localized level density of the sample can be derived by multiplying this increase in absorption coefficient by a constant.

Further, the absorption coefficient α due to the localized level can be calculated from the following equation by removing the light absorption (Urback tail) caused by the band tail from the curve of the light absorption spectrum.

α=∫[(α(E)−α _u )/E]dE

Here, E represents energy, α(E) represents the absorption coefficient at each energy, and α _u represents the absorption coefficient by the urback tail.

The inclination of the Urbach tail is called Urbach energy. It can be said that the lower the Urbach energy, the less the defects, and the more highly ordered the semiconductor film is, in which the tail of the level at the band edge of the valence band is steeper.

FIG. 64 shows a result of fitting the absorption coefficient (dotted line) measured by the spectrophotometer and the absorption coefficient (solid line) measured by CPM in the energy range of the energy gap of the oxide semiconductor film or more. 64A shows the result of the sample which was subjected to heat treatment at 300° C. after film formation, and FIG. 64B shows the result of the sample which was subjected to heat treatment at 400° C. after film formation.
C) shows the results of samples that were heat-treated at 450° C. after film formation. The Urbach energies obtained from the absorption coefficient measured by CPM are 72.65 meV and 69, respectively.
． It was 45 meV and 70.32 meV.

Further, in FIG. 64, the background (thin dotted line) was subtracted from the absorption coefficient derived by the CPM measurement to derive the integrated value of the absorption coefficient. The results are shown in Fig. 65. The absorption coefficients due to the localized levels are 6.27×10 ⁻¹ cm ⁻¹ , 4.19×10 ⁻¹ cm ⁻¹ and 2.29, respectively.
It was ×10 ⁻¹ cm ⁻¹ . FIG. 66 shows the relationship between the temperature of heat treatment and the absorption coefficient. FIG. 66
From this, it is understood that the higher the temperature of the heat treatment, the smaller the absorption coefficient, and thus the smaller the local level density.

11 region 12 region 13 region 14 region 15 region 16 region 21 vertical line 22 vertical line 23 vertical line 50 substrate 51 insulating film 100 transistor 101 semiconductor layer 101a insulating layer 101b semiconductor layer 101c insulating layer 102 gate insulating film 103 gate electrode 104a conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 114 Insulating film 123 Plug 124 Wiring 130 Transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating film 137 Insulating film 138 Insulating film 139 Plug 140 Plug 143 Conductive layer 150 Capacitive element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 Transistor 164 Plug 165 Plug 166 Wiring 171a Low resistance layer 171b Low resistance layer 176a Region 176b Region 181 Element isolation layer 190 Transistor 191 Transistor 201 Semiconductor layer 201a Semiconductor layer 201b Semiconductor layer 202 Gate insulating film 202a Gate insulating film 202b Gate insulating film 203a Gate electrode 203b Electrode 204a Conductive layer 204b Conductive layer 214 Insulating film 215 Insulating film 216 Insulating film 218 Insulating film 251 Conductive layer 281 hard mask 321 plug 322 plug 324 region 501 pixel circuit 502 pixel unit 504 driving circuit unit 504a gate driver 504b source driver 506 protection circuit 507 terminal unit 550 transistor 552 transistor 554 transistor 560 capacitor element 562 capacitor element 570 liquid crystal element 572 light emitting element 610 Electron gun chamber 612 Optical system 614 Sample chamber 616 Optical system 618 Camera 620 Observation chamber 622 Film chamber 624 Electronic 632 Fluorescent plate 700 Display device 701 Substrate 702 Pixel portion 704 Source driver circuit portion 705 Substrate 706 Gate driver circuit portion 708 FPC terminal portion 710 Signal Wire 711 Wiring portion 712 Sealing material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Coloring film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulating film 766 Insulating film 768 Insulating film 770 Flattening insulating film 772 Conductive layer 774 Conductive layer 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive layer 782 Light emitting element 784 Conductive layer 786 EL layer 788 Conductive layer 790 Capacitive element 790a Capacitive element 790b Capacitive element 800 RF tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM
901 housing 902 housing 903 display unit 904 display unit 905 microphone 906 speaker 907 operation key 908 stylus 911 housing 912 housing 913 display unit 914 display unit 915 connection unit 916 operation key 921 housing 922 display unit 923 keyboard 924 pointing device 931 housing 932 refrigerating room door 933 freezing room door 941 housing 942 housing 943 display section 944 operation key 945 lens 946 connection section 951 vehicle body 952 wheel 953 dashboard 954 light 2100 transistor 2200 transistor 4000 RF tag 5100 pellet 5100a pellet 5100b Pellet 5101 Ion 5120 Substrate 5130 Target 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (5)

A first conductive layer,
A first insulating layer on the first conductive layer;
An oxide semiconductor layer on the first insulating layer;
A second insulating layer on the oxide semiconductor layer;
A second conductive layer on the second insulating layer,
The first conductive layer overlaps with the oxide semiconductor layer through the first insulating layer,
The second conductive layer overlaps with the oxide semiconductor layer through the second insulating layer,
The oxide semiconductor layer contains indium and zinc, and contains, as the element M, at least one of aluminum, gallium, yttrium, or tin.
The ratio of the numbers of atoms of indium, element M, and zinc contained in the oxide semiconductor layer satisfies indium:element M:zinc=x:y:z,
In the equilibrium diagram in which the three elements of indium, element M, and zinc are vertices, x, y, and z are the first coordinates (x:y:z=8:14:7) and the second coordinate The coordinates (x:y:z=2:4:3), the third coordinates (x:y:z=2:5:7), and the fourth coordinates (x:y:z=51:149: 300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y). :Z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment in the range of the number of atoms. The range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate,
When irradiating a plurality of positions of the oxide semiconductor layer with an electron beam to observe a plurality of electron diffraction patterns ,
Of the plurality of electron diffraction patterns observed at the plurality of positions, the proportion having the first electron diffraction pattern is 50% or more,
The first electron diffraction pattern is a transistor in which spots are not symmetrically arranged or a pattern having a plurality of spots arranged in a circle. A first conductive layer,
A first insulating layer on the first conductive layer;
An oxide semiconductor layer on the first insulating layer;
A second insulating layer on the oxide semiconductor layer;
A second conductive layer on the second insulating layer,
The second insulating layer has an island shape,
The first conductive layer overlaps with the oxide semiconductor layer through the first insulating layer,
The second conductive layer overlaps with the oxide semiconductor layer through the second insulating layer,
The oxide semiconductor layer contains indium and zinc, and contains, as the element M, at least one of aluminum, gallium, yttrium, or tin.
The ratio of the numbers of atoms of indium, element M, and zinc contained in the oxide semiconductor layer satisfies indium:element M:zinc=x:y:z,
In the equilibrium diagram in which the three elements of indium, element M, and zinc are vertices, x, y, and z are the first coordinates (x:y:z=8:14:7) and the second coordinate Coordinates (x:y:z=2:4:3), third coordinates (x:y:z=2:5:7), and fourth coordinates (x:y:z=51:149: 300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y). :Z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment in the range of the number of atoms. The range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate,
When irradiating a plurality of positions of the oxide semiconductor layer with an electron beam to observe a plurality of electron diffraction patterns ,
Of the plurality of electron diffraction patterns observed at the plurality of positions, the proportion having the first electron diffraction pattern is 50% or more,
The first electron diffraction pattern is a transistor in which spots are not symmetrically arranged or a pattern having a plurality of spots arranged in a circle. A first conductive layer,
A first insulating layer on the first conductive layer;
An oxide semiconductor layer on the first insulating layer;
A second insulating layer on the oxide semiconductor layer;
A second conductive layer on the second insulating layer,
The second insulating layer has an island shape,
The end of the second insulating layer is outside the end of the second conductive layer,
The first conductive layer overlaps with the oxide semiconductor layer through the first insulating layer,
The second conductive layer overlaps with the oxide semiconductor layer through the second insulating layer,
The oxide semiconductor layer contains indium and zinc, and contains, as the element M, at least one of aluminum, gallium, yttrium, or tin.
The ratio of the numbers of atoms of indium, element M, and zinc contained in the oxide semiconductor layer satisfies indium:element M:zinc=x:y:z,
In the equilibrium diagram in which the three elements of indium, element M, and zinc are vertices, x, y, and z are the first coordinates (x:y:z=8:14:7) and the second coordinate The coordinates (x:y:z=2:4:3), the third coordinates (x:y:z=2:5:7), and the fourth coordinates (x:y:z=51:149: 300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y). :Z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment in the range of the number of atoms. The range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate,
When irradiating a plurality of positions of the oxide semiconductor layer with an electron beam to observe a plurality of electron diffraction patterns ,
Of the plurality of electron diffraction patterns observed at the plurality of positions, the proportion having the first electron diffraction pattern is 50% or more,
The first electron diffraction pattern is a transistor in which spots are not symmetrically arranged or a pattern having a plurality of spots arranged in a circle. In any one of Claim 1 thru|or 3,
A transistor in which a probe diameter of an electron beam used for observing the electron diffraction pattern is 1 nm. In any one of Claim 1 thru|or 4,
A transistor having a pair of electrode layers in contact with side surfaces of the oxide semiconductor layer.