JP2016066776A - Semiconductor film, semiconductor device, display device, module and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable provision of excellent electrical characteristics to a semiconductor device.SOLUTION: Plural electron diffraction patterns are observed by irradiating an oxide semiconductor film forming target face with an electron beam for which the half-value width of a probe diameter is set to 1 nm while the position of the film and the position of the electron beam are relatively moved. The plural electron diffraction patterns have 50 or more electron diffraction patterns observed at different places. The total of the occupancy ratio of first electron diffraction patterns to the 50 or more electron diffraction patterns and the occupancy ratio of second electron diffraction patterns to the 50 or more electron diffraction patterns is equal to 100%. The occupational rate of the first electron diffraction patterns is equal to 50% or more. The first electron diffraction pattern has observation points having no symmetry or plural observation points which are arranged as if a circle is drawn. The second electron diffraction pattern is an oxide semiconductor film having observation points located at the apexes of a hexagonal shape.SELECTED DRAWING: None

Description

  The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. An arithmetic device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

The physical properties of indium and zinc-containing oxides are interesting and extensively studied (Non-patent Documents 1 and 2). Non-Patent Document 1 states that a homologous phase represented by In _1-x Ga _{1 + x} O ₃ (ZnO) _m (x is a number satisfying −1 ≦ x ≦ 1 and m is a natural number) exists. . It also describes the solid solution range of the homologous phase. For example, when powders of In ₂ O ₃ , Ga ₂ O ₃ and ZnO are mixed and fired at 1350 ° C., the solid solution region of the homologous phase when m = 1 is such that x is from −0.33 to 0. .08, and the solid solution region of the homologous phase in the case of m = 2 has a description of x from −0.68 to 0.32.

As a compound having a spinel crystal structure, a compound represented by AB ₂ O ₄ (A and B are metals) is known. Non-Patent Document 1 shows an example of In _x Zn _y Ga _z O _w , where x, y and z are compositions in the vicinity of ZnGa ₂ O ₄ , that is, x, y and z are (x, y, z). == (0, 1, 2), it is described that a spinel crystal structure is easily formed or mixed.

  Further, a technique for forming a transistor using a semiconductor material has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor material applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

  For example, a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

  In recent years, with the increase in performance, size, and weight of electronic devices, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density.

JP 2007-123861 A JP 2007-96055 A

M.M. Nakamura, N .; Kimizuka, and T.K. Mohri, “The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350 ° C.”, J. Mohr. Solid State Chem. 1991, Vol. 93, pp. 298-315 M.M. Nespolo, A.M. Sato, T .; Osawa, and H.H. Ohashi, “Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. X-ray Diffraction Study of 20 kb Single Crystal and 50 kb Mw. Res. Technol. , 2000 Vol. 35, pp151-165

  An object of one embodiment of the present invention is to impart favorable electrical characteristics to a semiconductor device.

  Another object is to provide a highly reliable semiconductor device.

  Another object is to provide a favorable transistor with little variation in characteristics. Another object is to provide a semiconductor device including a memory element with favorable retention characteristics. Another object is to provide a semiconductor device suitable for miniaturization. Another object is to provide a semiconductor device with a reduced circuit area. Another object is to provide a semiconductor device with a novel structure.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M, and zinc satisfies indium: element M: zinc = x: y: z, and x, y, and z are in equilibrium with three elements of indium, element M, and zinc as vertices. In the state diagram, the first coordinates (x: y: z = 8: 14: 7), the second coordinates (x: y: z = 2: 4: 3), and the third coordinates (x: y : Z = 2: 5: 7), the fourth coordinate (x: y: z = 51: 149: 300), the fifth coordinate (x: y: z = 46: 288: 833), 6 coordinates (x: y: z = 0: 2: 11), seventh coordinates (x: y: z = 0: 0: 1), and eighth coordinates ( : Y: z = 1: 0: 0) and the first coordinate in the range of the number of atoms in a range obtained by connecting the first coordinate by a line segment in order, the range is the first coordinate to the sixth coordinate The position of the oxide semiconductor film with respect to the surface on which the oxide semiconductor film is formed using an electron beam that includes coordinates, does not include the seventh coordinate and the eighth coordinate, and the probe diameter half-value width is 1 nm. When the plurality of electron diffraction patterns are observed by irradiating the electron beam while relatively moving the position of the electron beam and the position of the electron beam, the plurality of electron diffraction patterns are 50 or more observed at different locations. The sum of the ratio of having the first electron diffraction pattern and the ratio of having the second electron diffraction pattern among the 50 or more electron diffraction patterns is 100%, and the first electron A diffraction pattern is a non-symmetrical observation point or circle. A plurality of observation points arranged so as to form a second electron diffraction pattern is an oxide semiconductor film having an observation point located on the hexagonal vertices.

  Alternatively, according to one embodiment of the present invention, the position of the oxide semiconductor film and the position of the electron beam are relatively set with respect to the formation surface of the oxide semiconductor film by using an electron beam having a probe diameter half-width of 1 nm. In the case where a plurality of electron diffraction patterns are observed by irradiating an electron beam while moving the plurality of electron diffraction patterns, the plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at different locations. Of the plurality of electron diffraction patterns, the sum of the ratio having the first electron diffraction pattern and the ratio having the second electron diffraction pattern is 100%, and the ratio having the first electron diffraction pattern is 50%. The first electron diffraction pattern has observation points that do not have symmetry, or a plurality of observation points arranged so as to draw a circle, and the second electron diffraction pattern has a hexagonal apex. Located in An oxide semiconductor film having a survey point.

  Another embodiment of the present invention is an oxide semiconductor film represented by an atomic ratio of In: M (Al, Ga, Y, or Sn): Zn = x: y: z, in which the coordinates x: y : Z = 1: 0: 0, coordinates x: y: z = 0: 1: 0, and coordinates x: y: z = 0: 0: 1 are the top of the equilibrium state diagram. Coordinates (x: y: z = 8: 14: 7), second coordinates (x: y: z = 2: 4: 3), and third coordinates (x: y: z = 2: 5: 7), the fourth coordinate (x: y: z = 51: 149: 300), the fifth coordinate (x: y: z = 46: 288: 833), and the sixth coordinate (x: y : Z = 0: 2: 11), the seventh coordinate (x: y: z = 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), In the range where the first coordinate and the line segment are connected in order, the formation of the oxide semiconductor film On the other hand, 50 or more electron diffraction patterns are observed at different locations by relatively moving the position of the oxide semiconductor film and the position of the electron beam whose half width of the probe diameter is 1 nm. The above-mentioned electron diffraction pattern includes an electron diffraction pattern having a plurality of spots arranged at least asymmetrically, an electron diffraction pattern having a plurality of spots arranged in a circle, and a spot arranged at the apex of the hexagon. And the range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate. is there.

  In the above structure, the oxide semiconductor film includes indium, an element M, and zinc. The element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of the element M and zinc satisfies indium: element M: zinc = x: y: z, and x, y, and z are equilibrium diagrams with the three elements of indium, element M, and zinc as vertices. , The first coordinates (x: y: z = 8: 14: 7), the second coordinates (x: y: z = 2: 4: 3), and the third coordinates (x: y: z) = 2: 5: 7), the fourth coordinate (x: y: z = 51: 149: 300), the fifth coordinate (x: y: z = 46: 288: 833), the sixth coordinate Coordinates (x: y: z = 0: 2: 11), seventh coordinates (x: y: z = 0: 0: 1), and eighth coordinates ( : Y: z = 1: 0: 0) and the ratio of the number of atoms in the range in which the first coordinates are connected by line segments in order, the ranges are the first to sixth coordinates It is preferable that the seventh coordinate and the eighth coordinate are not included.

  Alternatively, one embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, and the oxide semiconductor film includes a plurality of crystal parts arranged at random and includes a plurality of crystals. The average diameter in the longitudinal direction of the part is an oxide semiconductor film which is 1 nm or more and 3 nm or less.

  Another embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M, and zinc satisfies indium: element M: zinc = x: y: z, and x, y, and z have three elements of indium, element M, and zinc as vertices. In the equilibrium diagram, the first coordinate (x: y: z = 8: 14: 7), the second coordinate (x: y: z = 2: 4: 3), and the third coordinate (x : Y: z = 2: 5: 7), the fourth coordinate (x: y: z = 51: 149: 300), and the fifth coordinate (x: y: z = 46: 288: 833) , The sixth coordinate (x: y: z = 0: 2: 11), the seventh coordinate (x: y: z = 0: 0: 1), (X: y: z = 1: 0: 0) and the ratio of the number of atoms in a range obtained by connecting the first coordinates in order by a line segment. The oxide semiconductor film includes the sixth coordinate, does not include the seventh coordinate and the eighth coordinate, and the density of the oxide semiconductor film is 90% or more of the density of the single crystal having the same atomic ratio. .

  Another embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The oxide semiconductor film has a plurality of crystal parts arranged at random, and the plurality of crystal parts have no orientation, and a crystal having a diameter in the longitudinal direction of the plurality of crystal parts of 1 nm to 3 nm. The density of the oxide semiconductor film is 90% or more of the density of single crystals having the same atomic ratio.

Alternatively, one embodiment of the present invention is an oxide semiconductor film including indium, gallium, and zinc, and the oxide semiconductor film includes a plurality of crystal parts, and the plurality of crystal parts have orientation. the no, the average longitudinal diameter of the plurality of crystal parts is at 1nm or more 3nm or less, the density of the oxide semiconductor film is 5.7 g / cm ³ or more 6.49 g / cm ³ or less oxide A semiconductor film. In the above structure, the density of the oxide semiconductor film is preferably 90% or more of the density of single crystals having the same atomic ratio.

Alternatively, an embodiment of the present invention is an oxide semiconductor film including indium, gallium, and zinc, and the oxide semiconductor film includes a plurality of crystal parts arranged at random, and the plurality of crystal parts Has no orientation, the average A [nm] of the longitudinal diameters of the plurality of crystal parts is 1 nm or more and 3 nm or less, and the electron beam energy is 1 × 10 ⁷ [e ⁻ / nm ² ] or more and 4 The average B [nm] of the diameter in the longitudinal direction of the crystal part after irradiation with less than × 10 ⁸ [e ⁻ / nm ² ] is an oxide larger than A × 0.7 and smaller than A × 1.3 It is a semiconductor film.

  In the above structure, the oxide semiconductor film is formed by a sputtering method, and a target used for the sputtering method includes indium, an element M, and zinc. The target includes indium, the element M, and zinc atoms. The number ratio satisfies indium: element M: zinc = a: b: c, and a, b, and c are the first coordinates in the equilibrium diagram with the three elements of indium, element M, and zinc as vertices. (A: b: c = 8: 14: 7), second coordinates (a: b: c = 2: 4: 3), and third coordinates (a: b: c = 1: 2: 5) .1), the fourth coordinate (a: b: c = 1: 0: 1.7), the fifth coordinate (a: b: c = 8: 0: 1), and the sixth coordinate ( a: b: c = 6: 2: 1) and the first coordinate, and the ratio of the number of atoms in a range in which the first coordinates are connected by a line segment in order, Preferably includes a first coordinate to sixth coordinates.

Another embodiment of the present invention is a semiconductor device including the oxide semiconductor film described above. In the above structure, the oxide semiconductor includes a first conductive layer, a first insulating film in contact with an upper surface and a side surface of the first conductive layer, and a pair of electrodes in contact with the upper surface of the oxide semiconductor film. The film preferably has a region in contact with the upper surface of the first insulating film. In the above structure, the first conductive layer, the first insulating film in contact with the top surface and the side surface of the first conductive layer, the second insulating film in contact with the top surface of the oxide semiconductor film, and the oxide semiconductor film The oxide semiconductor film preferably includes a region in contact with the top surface of the first insulating film. The oxide semiconductor film preferably includes a pair of electrodes in contact with the top surface and the top surface and side surfaces of the second insulating film. In the above structure, it is preferable that the second oxide film be in contact with the top surface of the oxide semiconductor film. In the above structure, the oxide affinity of the oxide included in the oxide semiconductor film is preferably larger than the electron affinity of the oxide included in the second oxide film. In the above structure, the second oxide film includes indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M, and zinc included in the second oxide film is represented by indium: element M: zinc = x ₂ : y ₂ : z ₂ (x ₂ : y ₂ : z ₂ ) In the equilibrium diagram with the three elements of indium, element M and zinc as vertices, the first coordinate (8: 14: 7), the second coordinate (2: 4: 3), and the third Coordinates (2: 5: 7), fourth coordinates (51: 149: 300), fifth coordinates (1: 4: 10), sixth coordinates (1: 1: 4), The ratio of the number of atoms within a range in which the seventh coordinate (2: 2: 1) and the first coordinate are connected by a line segment in order. And, the range preferably includes a first coordinate to a seventh coordinate.

  Another embodiment of the present invention is a display device including the above-described semiconductor device and a display element.

  Another embodiment of the present invention is a module including the semiconductor device described above or the display device described above and an FPC.

  Another embodiment of the present invention is an electronic device including the semiconductor device described above, the display device described above, or the module described above and a microphone, a speaker, or an operation key.

  According to one embodiment of the present invention, favorable electrical characteristics can be imparted to a semiconductor device. In addition, a highly reliable semiconductor device can be provided.

  In addition, a transistor with little variation can be provided. In addition, a semiconductor device including a memory element with favorable retention characteristics can be provided. In addition, a semiconductor device suitable for miniaturization can be provided. In addition, a semiconductor device with a reduced circuit area can be provided. In addition, a semiconductor device having a novel structure can be provided. Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

10A and 10B illustrate an atomic ratio of an oxide film according to one embodiment of the present invention. 10A and 10B illustrate an atomic ratio of an oxide film according to one embodiment of the present invention. The figure explaining atomic number ratio. 10A and 10B illustrate an atomic ratio of an oxide film according to one embodiment of the present invention. FIG. 9 illustrates an atomic ratio of a target according to one embodiment of the present invention. The figure explaining atomic number ratio. The figure which shows the nano beam electron diffraction pattern of an oxide semiconductor film, and the figure which shows an example of a transmission electron diffraction measuring apparatus. The figure which shows the analysis result by the X-ray-diffraction apparatus of nc-OS. The figure which shows the electron diffraction pattern of nc-OS. 4A and 4B illustrate a crystal of InGaZnO ₄ . 4A and 4B each illustrate a band structure of part of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of CAAC-OS and nc-OS. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of CAAC-OS. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of CAAC-OS. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of nc-OS. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of nc-OS. The figure which shows the pellet size observed by the Cs correction | amendment high-resolution cross-sectional TEM image of CAAC-OS and nc-OS, and its frequency. The figure which shows the relationship between the atomic ratio of a target, and the atomic ratio of an oxide semiconductor film. The schematic diagram explaining the film-forming model of nc-OS, and the figure which shows a pellet. FIG. 3 is a schematic diagram illustrating a film formation apparatus. 10A and 10B are a block diagram and a circuit diagram illustrating a display device. The figure of the display module based on Embodiment. The structural example of RF tag based on Embodiment. FIG. 6 illustrates an example of a transistor. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 10 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 14 is a top view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. FIG. 14 is a cross-sectional view illustrating one embodiment of a display device. The circuit diagram based on Embodiment. FIG. 6 illustrates an example of a semiconductor device according to one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 10A to 10D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4 shows an XRD evaluation result of an oxide semiconductor film according to one embodiment of the present invention. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. An electron diffraction pattern of an oxide semiconductor film. The TDS analysis result of an oxide semiconductor film. The figure which shows the change of the crystal | crystallization by electron beam irradiation. The usage example of RF tag based on Embodiment. An electronic device according to an embodiment. FIG. 9 shows the film density of an oxide semiconductor film. FIG. 9 shows an etching rate of an oxide semiconductor film. FIG. 9 shows the amount of released gas from an oxide semiconductor film. FIG. 11 shows hydrogen concentration of an oxide semiconductor film. FIG. 6 illustrates a crystal size of an oxide semiconductor film. FIG. 6 illustrates a crystal size of an oxide semiconductor film. FIG. 9 shows CPM measurement results of an oxide semiconductor film. FIG. 9 shows CPM measurement results of an oxide semiconductor film. FIG. 9 shows CPM measurement results of an oxide semiconductor film. The figure which shows the Cs correction | amendment high-resolution cross-sectional TEM image of a-like OS. FIG. 11 shows hydrogen concentration of an oxide semiconductor film.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

  In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

  Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

(Embodiment 1)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

  An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

  The single crystal may be formed by firing at a high temperature of about 1000 ° C. or higher, for example. Therefore, from an industrial viewpoint, it is preferable to use a non-single-crystal oxide semiconductor film that can be formed at a lower temperature because a semiconductor device can be manufactured at lower cost.

  The fewer the grain boundaries of the oxide semiconductor film, the better. By reducing the grain boundaries, for example, carrier mobility can be increased. When a transistor is formed using an oxide semiconductor film with few grain boundaries, for example, a transistor with high field-effect mobility may be realized. Although described in detail later, examples of the non-single-crystal oxide semiconductor film with few grain boundaries include an nc-OS film and a CAAC-OS film.

  On the other hand, the oxide semiconductor film may have a spinel crystal. In some cases, a spinel structure crystal is mixed in the CAAC-OS film or the nc-OS film, so that a clear boundary (or grain boundary) is formed. In the boundary portion, for example, carrier scattering may increase and carrier mobility may decrease. In addition, since the boundary portion is likely to be an impurity migration path and is likely to trap the impurity, there is a concern that the impurity concentration of the oxide semiconductor film is increased. In the case where a conductive film is formed over the oxide semiconductor film, an element included in the conductive film, such as metal, may diffuse into the boundary portion between the spinel and another region. Therefore, it is more preferable that the oxide semiconductor film does not contain or contain a spinel crystal structure.

  Here, the oxide semiconductor is an oxide semiconductor containing indium, for example. When the oxide semiconductor contains indium, for example, carrier mobility (electron mobility) increases. The oxide semiconductor preferably contains the element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The oxide semiconductor preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc. Here, an oxide containing indium, the element M, and zinc is referred to as an In-M-Zn oxide.

[Atom ratio]
A ratio of the number of atoms of the In-M-Zn oxide film which is the oxide semiconductor film of one embodiment of the present invention is expressed as In: M: Zn = x: y: z. A preferable range of x, y, and z will be described with reference to FIGS. 1 and 2.

  Here, the ratio of the number of atoms of each element will be described with reference to FIG. FIG. 3 is a diagram illustrating a range of x, y, and z when the ratio of the number of atoms of the elements X, Y, and Z in the XYZ oxide film is x: y: z. Note that the atomic ratio of oxygen is not shown in FIG. FIG. 3 may be called an equilibrium diagram. 3A and 3B show an equilateral triangle whose vertices are X, Y, and Z, and a coordinate R (4: 2: 1) as an example of the coordinate. Here, each vertex represents the elements X, Y, and Z, respectively. The value of each term in the ratio of the number of atoms is higher as the coordinates are closer to each vertex, and lower as the coordinates are farther away. Further, as shown in FIG. 3A, the value of each term in the ratio of the number of atoms is expressed by the length of a perpendicular line from the coordinate to the opposite side of the apex of the triangle. For example, in the case of element X, it is represented by the length of perpendicular line 21 from the coordinate to the opposite side of vertex X, that is, side YZ. Therefore, the coordinate R shown in FIG. 3 is such that the atomic ratio of the element X, the element Y, and the element Z is the ratio of the lengths of the vertical line 21, the vertical line 22, and the vertical line 23, that is, x: y: z = 4: 2: 1. Represents something. Further, a point where a straight line passing through the vertex X and the coordinate R intersects the side YZ is represented by γ. At this time, if the ratio of the length of the line segment Yγ and the length of the line segment γZ is Yγ: γZ, Yγ: γZ = (number of atoms of element Z) :( number of atoms of element Y).

  Further, as shown in FIG. 3B, three straight lines that pass through the coordinate R and are parallel to the three sides of the triangle are drawn. At this time, x, y, and z can be expressed as shown in FIG. 3B by using the intersections of the three straight lines and the three sides.

  In FIG. 6, in the case where x: y: z satisfies the following formula in the In-M-Zn oxide film, the range is indicated by a broken line.

  x: y: z = (1-α) :( 1 + α): m (−1 ≦ α ≦ 1)

  Here, FIG. 6 shows the case of m = 1, 2, 3, 4, 5.

As described in Non-Patent Document 1, it is known that an In-M-Zn oxide has a homologous phase (homologus series) represented by InMO ₃ (ZnO) _m (m is a natural number). Yes. Here, a case where the element M is Ga is considered as an example. The region shown by a thick straight line in FIG. 6 can be a single-phase solid solution region when, for example, powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and fired at 1350 ° C. Is a known composition. It is known that the solid solution region becomes wider as the value of m is increased, that is, the ratio of zinc is increased.

In addition, the coordinates indicated by the square symbols in FIG. 6 are obtained when, for example, In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and fired at 1350 ° C. as described in Non-Patent Document 1. The composition is known to easily contain spinel crystal structures. As shown in FIG. 6, when the composition in the vicinity of ZnGa ₂ O ₄ , that is, when x, y, and z have values close to (x, y, z) = (0, 2, 1), a spinel crystal Non-Patent Document 1 describes that structures are easily formed or mixed.

  The In-M-Zn oxide film that is an oxide semiconductor film of one embodiment of the present invention preferably has a high indium ratio. In the In-M-Zn oxide film, s orbitals of metal atoms mainly contribute to carrier conduction, and by increasing the indium content, more s orbitals overlap, so that the indium content is high. Carrier mobility is higher. By manufacturing a transistor using such a film for a channel region, for example, a transistor having high field-effect mobility can be realized. For example, x / y> 0.5 is preferable, x / y ≧ 0.75 is more preferable, and x / y ≧ 1 is more preferable. Further, (x + y) ≧ z is preferable.

  Therefore, x, y, and z preferably have a ratio of the number of atoms in the region 11 shown in FIG. 1, and more preferably have a ratio of the number of atoms in the region 12 shown in FIG. Here, the region 11 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate. L (x: y: z = 2: 5: 7), the fourth coordinate M (x: y: z = 51: 149: 300), and the fifth coordinate N (x: y: z = 46: 288: 833), the sixth coordinate O (x: y: z = 0: 2: 11), the seventh coordinate P (x: y: z = 0: 0: 1), and the eighth coordinate It is within the region where Q (x: y: z = 1: 0: 0) and the first coordinate K are connected in order by a line segment. Note that the region 11 includes a line segment connecting eight points. Further, the coordinates 11 and the coordinates Q are excluded from the area 11, and other coordinates are included in the area 11. The region 12 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate L. (X: y: z = 2: 5: 7), the fourth coordinate S (x: y: z = 1: 0: 1), and the fifth coordinate Q (x: y: z = 1: 0) : 0) and the first coordinate K in a line segment in order. Note that the region 12 includes a line segment connecting five points. Further, the coordinate 12 is excluded from the region 12 and other coordinates are included in the region 12.

[Structure of oxide semiconductor film]
Next, the structure of the oxide semiconductor film is described.

  First, the CAAC-OS film is described.

  The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

  Confirming a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

  When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

  On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

  Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm to 30 nm is performed on the formation surface or the upper surface of the CAAC-OS film, spots are observed (FIG. 7B). reference.).

  From the high-resolution TEM image of the cross section and the high-resolution TEM image of the plane, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most crystal parts included in the CAAC-OS film fit in a cube whose one side is less than 100 nm. Therefore, the case where a crystal part included in the CAAC-OS film fits in a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm is included. Note that a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a planar high-resolution TEM image, a crystal region having a thickness of 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

On the other hand, in an analysis by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis on a CAAC-OS film, a peak may appear when 2θ is around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed in the vicinity of 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to the crystal plane equivalent to the (110) plane are observed. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when φ scan is performed with 2θ fixed at around 56 °.

  From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis is aligned, and the c-axis is a normal line of the formation surface or the top surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of metal atoms arranged in a layer shape confirmed by high-resolution TEM observation of the cross section described above is a plane parallel to the ab plane of the crystal.

  Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

  In the CAAC-OS film, the distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the ratio of the crystal part in which the region near the upper surface is c-axis aligned than the region near the formation surface May be higher. In addition, in the CAAC-OS film to which an impurity is added, a region to which the impurity is added may be changed, and a region having a different ratio of a partially c-axis aligned crystal part may be formed.

Note that when the CAAC-OS film including an InGaZnO ₄ crystal is analyzed by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to the peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

  The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

Further, for example, oxygen vacancies in the oxide semiconductor film may serve as carrier traps or serve as a carrier generation source by trapping hydrogen. The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Specifically, it is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and a carrier of 1 × 10 ⁻⁹ / cm ³ or more. A dense oxide semiconductor can be obtained.

  In addition, a transistor including a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

  Next, a polycrystalline oxide semiconductor film is described.

  In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in a high-resolution TEM image. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, high-resolution TEM images and often have a grain size of 2 nm to 300 nm, 3 nm to 100 nm, or 5 nm to 50 nm. In some cases, a polycrystalline oxide semiconductor film can confirm a crystal grain boundary using a high-resolution TEM image.

A polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation may be different between the plurality of crystal grains. Further, when structural analysis is performed on a polycrystalline oxide semiconductor film using an XRD apparatus, for example, in an analysis of a polycrystalline oxide semiconductor film including an InGaZnO ₄ crystal by an out-of-plane method, 2θ is 31 °. There may be a peak near 2 and a peak near 2θ of 36 ° or other peaks.

  Since a polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor including a polycrystalline oxide semiconductor film has high field effect mobility. However, in a polycrystalline oxide semiconductor film, impurities may segregate at a crystal grain boundary. Further, the crystal grain boundary of the polycrystalline oxide semiconductor film becomes a defect level. In a polycrystalline oxide semiconductor film, a crystal grain boundary may become a carrier trap or a carrier generation source. Therefore, a transistor using a polycrystalline oxide semiconductor film has a large variation in electrical characteristics and is a transistor with low reliability. There is a case.

  Next, a microcrystalline oxide semiconductor film is described.

  The microcrystalline oxide semiconductor film includes a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

  The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of the crystal part, in the analysis by the out-of-plane method, a peak near 31 ° indicating the crystal plane is obtained. Is not detected (see FIG. 8). Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region. For example, as shown in FIG. 9A, when nanobeam electron diffraction with a probe diameter of 30 nm, 20 nm, 10 nm, or 1 nm is performed on an nc-OS having a thickness of about 50 nm, a circle is drawn ( A bright area is observed (in a ring). It can also be seen that as the probe diameter is reduced, a ring-shaped region is formed from a plurality of spots.

  For further detailed structural analysis, the nc-OS film is thinned to several nm (about 5 nm), and a transmission electron diffraction pattern is obtained using an electron beam with a probe diameter of 1 nm. As a result, a transmission electron diffraction pattern having spots showing the crystallinity shown in FIG. 9B was obtained.

  Further, when nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions may be observed.

  The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film.

  In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with a high carrier density may have a high electron mobility. Therefore, a transistor including the nc-OS film may have high field effect mobility.

  The nc-OS film can be formed at a lower temperature than the CAAC-OS film. In some cases, the nc-OS film can be formed even when a relatively large amount of impurities is contained. Therefore, the nc-OS film may be easier to form than the CAAC-OS film. Therefore, a semiconductor device including a transistor including an nc-OS film can be manufactured with high productivity.

  In addition, the nc-OS film may have appropriate oxygen permeability. In the case of having appropriate oxygen permeability, for example, oxygen released from a film containing excess oxygen is likely to diffuse throughout the nc-OS film. Thus, in some cases, the nc-OS film can easily reduce oxygen vacancies.

  A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

  Next, an amorphous oxide semiconductor film is described.

  An amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

  In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image.

  When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

  An amorphous oxide semiconductor film is an oxide semiconductor film containing an impurity such as hydrogen at a high concentration. The amorphous oxide semiconductor film is an oxide semiconductor film with a high defect level density.

  An oxide semiconductor film with a high impurity concentration and a high density of defect states is an oxide semiconductor film with many carrier traps and carrier generation sources.

  Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. Therefore, a transistor including an amorphous oxide semiconductor film is likely to be normally on. Therefore, the transistor can be preferably used for a transistor that requires normally-on electrical characteristics. An amorphous oxide semiconductor film has a high density of defect states, and thus may have a large number of carrier traps. Therefore, a transistor including an amorphous oxide semiconductor film has a large variation in electrical characteristics and low reliability as compared with a transistor including a CAAC-OS film or an nc-OS film.

  Next, a single crystal oxide semiconductor film is described.

  A single crystal oxide semiconductor film is an oxide semiconductor film with low impurity concentration and low density of defect states (low oxygen vacancies). Therefore, the carrier density can be lowered. Accordingly, a transistor including a single crystal oxide semiconductor film is unlikely to be normally on. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, carrier traps may be reduced. Therefore, a transistor including a single crystal oxide semiconductor film has a small change in electrical characteristics and has high reliability.

  Note that the density of an oxide semiconductor film increases when the number of defects is small. In addition, the density of an oxide semiconductor film increases when crystallinity is high. In addition, the density of an oxide semiconductor film increases when the concentration of impurities such as hydrogen is low. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. In addition, the density of the CAAC-OS film is higher than that of the microcrystalline oxide semiconductor film. In addition, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. The microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

  Note that the oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

  In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

Note that the crystal part size of the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, it was considered that each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less. The maximum length in the region where the lattice fringes are observed is the size of the crystal part of the a-like OS film and the nc-OS film. Note that a crystal part having a size of 0.8 nm or more is selectively evaluated.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.

Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

[Nanobeam electron diffraction]
Next, nanobeam electron diffraction will be described.

  In the case where the oxide semiconductor film has a plurality of structures, the structure analysis may be possible by using nanobeam electron diffraction.

  FIG. 7C shows an electron gun chamber 610, an optical system 612 under the electron gun chamber 610, a sample chamber 614 under the optical system 612, an optical system 616 under the sample chamber 614, and an optical system 616. 1 shows a transmission electron diffraction measurement apparatus having an observation room 620 below, a camera 618 installed in the observation room 620, and a film room 622 below the observation room 620. The camera 618 is installed toward the inside of the observation room 620. Note that the film chamber 622 is not necessarily provided.

  FIG. 7D shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. Inside the transmission electron diffraction measurement apparatus, electrons emitted from the electron gun installed in the electron gun chamber 610 are irradiated to the substance 628 disposed in the sample chamber 614 via the optical system 612. The electrons that have passed through the substance 628 enter the fluorescent plate 632 installed in the observation chamber 620 through the optical system 616. In the fluorescent plate 632, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of incident electrons.

  The camera 618 is installed facing the fluorescent screen 632 and can capture a pattern that appears on the fluorescent screen 632. The angle formed between the center of the lens of the camera 618 and the straight line passing through the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15 ° to 80 °, 30 ° to 75 °, or 45 ° to 70 °. The following. As the angle is smaller, the transmission electron diffraction pattern photographed by the camera 618 is more distorted. However, if the angle is known in advance, the distortion of the obtained transmission electron diffraction pattern can be corrected. Note that the camera 618 may be installed in the film chamber 622 in some cases. For example, the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with less distortion can be taken from the back surface of the fluorescent plate 632.

  In the sample chamber 614, a holder for fixing the substance 628 as a sample is installed. The holder is structured to transmit electrons passing through the substance 628. For example, the holder may have a function of moving the substance 628 to the X axis, the Y axis, the Z axis, and the like. The movement function of the holder may have an accuracy of moving in the range of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, and the like. These ranges may be set to optimum ranges depending on the structure of the substance 628.

  Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

  For example, as illustrated in FIG. 7D, by changing (scanning) the irradiation position of the electron 624 that is a nanobeam in the substance, it is possible to confirm how the structure of the substance changes. At this time, when the substance 628 is a CAAC-OS film, a diffraction pattern as illustrated in FIG. 7B is observed. Alternatively, when the substance 628 is an nc-OS film, a diffraction pattern as illustrated in FIG. 7A, for example, a diffraction pattern having a plurality of bright spots arranged in a circle (a ring with bright spots) A diffraction pattern) is observed. In addition, the diffraction pattern shown in FIG. 7A has bright spots that are not symmetrically arranged (having no symmetry).

  As shown in FIG. 7B, in the diffraction pattern of the CAAC-OS film, for example, a spot positioned at the vertex of a hexagon is confirmed. In the CAAC-OS film, when the irradiation position is scanned, the direction of the hexagon is not uniform, and a state where the hexagon is rotating little by little can be seen. The angle of rotation has a certain width.

  Alternatively, in the diffraction pattern of the CAAC-OS film, a state where the irradiation position is scanned and the c-axis is rotated little by little is seen. This can be said that the surface formed by the a-axis and the b-axis is rotating, for example.

  By the way, a region where the same diffraction pattern as the CAAC-OS film is observed in the substance 628 (hereinafter referred to as a region having a CAAC structure) and a region where a diffraction pattern similar to the nc-OS film is observed (hereinafter referred to as an nc structure). May be referred to as a region having Here, a ratio of a region where a diffraction pattern of the CAAC-OS film in a certain range is observed can be represented by a CAAC ratio (also referred to as a CAAC conversion ratio). Similarly, the ratio of a region where a diffraction pattern similar to that of the nc-OS film is observed can be expressed as an nc ratio (also referred to as an nc conversion rate).

  A method for evaluating the CAAC ratio of the CAAC-OS film is described below. A measurement point is selected at random, a transmission electron diffraction pattern is obtained, and the ratio of the number of measurement points at which the diffraction pattern of the CAAC-OS film is observed is calculated with respect to the number of all measurement points. Here, the number of measurement points is preferably 50 points or more, and more preferably 100 points or more.

  As a method of randomly selecting measurement points, for example, the irradiation position may be scanned in a straight line, and a diffraction pattern may be acquired at regular intervals. Scanning the irradiation position is preferable because the boundary between the area having the CAAC structure and the other area can be confirmed. Similarly, the nc conversion rate can be calculated by selecting a measurement point at random and acquiring a transmission electron diffraction pattern.

  When such a measurement method is used, the structure analysis of an oxide semiconductor film having a plurality of structures may be possible.

  In the oxide semiconductor film which is one embodiment of the present invention, for example, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, and 95% or more and 100% or less. Preferably, it is 98% or more and 100% or less, more preferably 99% or more and 100% or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film having clear grain boundaries can be realized. By reducing the number of clear grain boundaries, for example, the carrier mobility of the oxide semiconductor film can be increased.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

  The nc-OS film can be formed even at a relatively low deposition temperature as compared to the CAAC-OS film in some cases. For example, the substrate may be formed without using heating to the substrate. Thus, a semiconductor device including a transistor including an nc-OS film can be manufactured with high productivity.

  Further, since the nc-OS film has appropriate oxygen permeability, oxygen may be easily diffused throughout the film, and oxygen vacancies may be more easily reduced. Therefore, an oxide semiconductor film with a low defect density may be realized. Thus, the characteristics of a semiconductor device including a transistor including an nc-OS film can be improved in some cases. In addition, reliability may be improved.

  Here, both the nc-OS film and the CAAC-OS film have an atomic arrangement in which the layers overlap each other. Such a layered atomic arrangement can be observed using, for example, a TEM.

  Here, with respect to the nc-OS film and the CAAC film, an image (also referred to as a TEM image) obtained by transmission electron microscopy (TEM) using a spherical aberration correction (Spherical Aberration Collector) function is observed. Note that a combined analysis image of a bright field image and a diffraction pattern by TEM observation is referred to as a high resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. In addition, acquisition of a Cs correction | amendment high resolution TEM image can be performed by JEOL Co., Ltd. atomic resolution analytical electron microscope JEM-ARM200F etc., for example.

  In CAAC-OS and nc-OS, the Cs-corrected high-resolution cross-sectional TEM image is analyzed in more detail to investigate the crystal size and orientation. Hereinafter, the crystal part of the nc-OS may be referred to as a pellet. For the size and orientation of the crystal, for example, a pellet is extracted in a range of 20 nm square or more in the cross-sectional TEM image, and the size and orientation are investigated.

  Note that FIG. 17A is a Cs-corrected high-resolution cross-sectional TEM image of a CAAC-OS. FIG. 17B is a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS. Note that the left and right figures are obtained by observing the same place, and the right figure is drawn with auxiliary lines indicating pellets.

  FIG. 18A is a cross-sectional TEM image of a CAAC-OS formed by a DC sputtering method. FIG. 18B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part thereof. In FIG. 18B, the number of pellets is counted and a frequency distribution is made with respect to the size and orientation (see FIG. 22A). Here, an arrow shown in FIG. 18A indicates a direction perpendicular to the sample surface. Further, the direction of the white line shown in FIG. 18B indicates the direction of the pellet, and the length of the white line indicates the size of the pellet.

  FIG. 19A is a cross-sectional TEM image of a CAAC-OS formed by an RF sputtering method. FIG. 19B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part thereof. In FIG. 19 (B), the number of pellets is counted, and a frequency distribution is made with respect to the size and orientation (see FIG. 22 (B)).

  FIG. 20A is a cross-sectional TEM image of nc-OS formed by a DC sputtering method. FIG. 20B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged. In FIG. 20B, the number of pellets is counted and a frequency distribution is made with respect to the size and orientation (see FIG. 22C).

  FIG. 21A is a cross-sectional TEM image of nc-OS formed by an RF sputtering method. FIG. 21B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part thereof. In FIG. 21B, the number of pellets is counted, and a frequency distribution is made with respect to the size and direction (see FIG. 22D).

  The table below summarizes the results of FIG. Here, the direction of the pellet indicates the absolute value of the angle with respect to the sample surface.

  The nc-OS preferably has a pellet having a size of preferably 0.5 nm to 3 nm, more preferably 1 nm to 3 nm. In nc-OS, it is found that the pellets are oriented in the direction perpendicular to the sample surface in the RF sputtering method than in the DC sputtering method. Here, the ratio that the orientation of the nc-OS pellet is 0 ° or more and less than 30 ° with respect to the sample surface is preferably, for example, 0% or more and 70% or less, and the rate that is 30 ° or more and less than 60 °, % To 60% is preferable, and the ratio of 60 ° to less than 90 ° is preferably, for example, 0% to 60%. It can be seen that nc-OS has a random orientation of pellets compared to CAAC-OS.

  An oxide semiconductor film having such a pellet can be described by, for example, the following film formation model.

[Film formation model]
Hereinafter, a film formation model of the nc-OS will be described.

  FIG. 24 is a schematic diagram of a film formation chamber in which a nc-OS film is formed by a sputtering method.

  The target 5130 is bonded on the backing plate. A plurality of magnets are disposed under the target 5130 and the backing plate. A magnetic field is generated on the target 5130 by the plurality of magnets. A sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method.

  The target 5130 has a polycrystalline structure, and any one of the crystal grains includes a cleavage plane. Details of the cleavage plane will be described later.

The substrate 5120 is disposed so as to face the target 5130, and the distance d (also referred to as target-substrate distance (T-S distance)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0. .5m or less. The film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 50% by volume or more) and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled. Here, by applying a voltage of a certain level or higher to the target 5130, discharge starts and plasma is confirmed. Note that a high-density plasma region is formed by the magnetic field on the target 5130. In the high-density plasma region, ions 5101 are generated by ionizing the deposition gas. The ions 5101 are, for example, oxygen cations (O ⁺ ), argon cations (Ar ⁺ ), and the like.

  The ions 5101 are accelerated toward the target 5130 by the electric field and eventually collide with the target 5130. At this time, the pellet 5100a and the pellet 5100b, which are flat or pellet-like sputtered particles, are peeled off from the cleavage plane and knocked out. Note that the pellets 5100a and 5100b may be distorted in structure due to the impact of collision of the ions 5101.

  The pellet 5100a is a flat or pellet-like sputtered particle having a triangular plane, for example, a regular triangular plane. The pellet 5100b is a flat or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. Note that flat or pellet-like sputtered particles such as the pellet 5100a and the pellet 5100b are collectively referred to as a pellet. The planar shape of the pellet is not limited to a triangle or a hexagon. For example, there may be a shape in which 2 or more and 6 or less triangles are combined. For example, there may be a quadrangle in which two equilateral triangles are combined.

  The thickness of the pellet is determined according to the type of film forming gas. The thickness of the pellet is preferably uniform. Moreover, it is more preferable that the sputtered particles are in the form of pellets with no thickness than in the form of thick dice.

  The pellet may be charged negatively or positively by receiving charges when passing through the plasma. The pellet has oxygen atoms on the side surfaces, and the oxygen atoms may be negatively charged.

  As shown in FIG. 24, for example, the pellets fly like a kite in the plasma and flutter up to the substrate 5120. Since the pellets are charged, repulsion occurs when an area where other pellets are already deposited approaches. Here, a magnetic field in a direction parallel to the upper surface of the substrate 5120 is generated on the upper surface of the substrate 5120. In addition, since a potential difference is applied between the substrate 5120 and the target 5130, a current flows from the substrate 5120 toward the target 5130. Therefore, the pellet receives a force (Lorentz force) on the upper surface of the substrate 5120 by the action of the magnetic field and the current. In order to increase the force applied to the pellets, the magnetic field in the direction parallel to the top surface of the substrate 5120 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more. It is good to provide the area | region which becomes. Alternatively, on the upper surface of the substrate 5120, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, the magnetic field in the direction perpendicular to the upper surface of the substrate 5120. More preferably, a region that is five times or more is provided.

  It is considered that pellets are deposited on the substrate 5120 by the above model. Therefore, unlike the epitaxial growth, it can be seen that the nc-OS can be formed even when the formation surface does not have a crystal structure. For example, the nc-OS can be formed even when the structure of the top surface (formation surface) of the substrate 5120 is an amorphous structure.

  Since the nc-OS film is formed using such a model, it is preferable that the sputtered particles have a thin pellet shape. Note that when the sputtered particles have a thick dice shape, the surface of the sputtered particles directed onto the substrate 5120 is not constant, and the thickness and crystal orientation may not be uniform.

  In addition, when the substrate 5120 is heated, resistance such as friction is smaller between the pellet and the substrate 5120. As a result, the pellet moves so as to glide on the upper surface of the substrate 5120. The movement of the pellet occurs in a state where the flat plate surface of the pellet faces the substrate 5120. After that, when reaching the side surfaces of another pellet 5100 which has already been deposited, the side surfaces are bonded to each other, and a CAAC-OS film is obtained.

  When the substrate 5120 is not heated, the resistance such as friction is larger between the pellet and the substrate 5120. As a result, the pellets are difficult to move so as to glide over the upper surface of the substrate 5120, and the nc-OS can be obtained by irregularly piled up.

The CAAC-OS forms a film by heating the substrate 5120, whereas the nc-OS can form a film without heating the substrate 5120.

  Further, for example, as shown in FIG. 25, the atmosphere in the chamber may be heated preferably at room temperature to 500 ° C., more preferably at 200 ° C. to 400 ° C. For heating the atmosphere, a lamp 5140 such as a halogen lamp may be used. By heating the atmosphere, for example, pellets flying in the chamber are heated, and defects may be reduced. In addition, the pellet size may increase. Further, by heating the atmosphere, for example, moisture in the chamber is easily evaporated, and the degree of vacuum can be further increased.

[Cleaved surface]
Hereinafter, the cleavage plane of the target described in the nc-OS film formation model will be described.

First, the cleavage plane of the target will be described with reference to FIG. FIG. 10 shows a crystal structure of InGaZnO ₄ . Note that FIG. 10A illustrates a structure in the case where an InGaZnO ₄ crystal is observed from a direction parallel to the b-axis with the c-axis facing upward. FIG. 10B shows a structure in the case where an InGaZnO ₄ crystal is observed from a direction parallel to the c-axis.

The energy required for cleavage in each crystal plane of the InGaZnO ₄ crystal is calculated by first-principles calculation. The calculation uses a pseudo-potential and a density functional program (CASTEP) using a plane wave basis. As the pseudopotential, an ultrasoft pseudopotential is used. Moreover, GGA PBE is used for the functional. The cut-off energy is 400 eV.

  The energy of the structure in the initial state is derived after performing the structure optimization including the cell size. In addition, the energy of the structure after cleavage on each surface is derived after structural optimization of atomic arrangement with the cell size fixed.

Based on the structure of the InGaZnO ₄ crystal shown in FIG. 10, a structure cleaved on any of the first surface, the second surface, the third surface, and the fourth surface is prepared, and the cell size is fixed. Perform structural optimization calculation. Here, the first plane is a crystal plane between the Ga—Zn—O layer and the In—O layer, and is a crystal plane parallel to the (001) plane (or the ab plane) (FIG. 10A )reference.). The second plane is a crystal plane between the Ga—Zn—O layer and the Ga—Zn—O layer, and is a crystal plane parallel to the (001) plane (or the ab plane) (FIG. 10A). reference.). The third plane is a crystal plane parallel to the (110) plane (see FIG. 10B). The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (see FIG. 10B).

  Under the above conditions, the energy of the structure after cleavage is calculated on each surface. Next, by dividing the difference between the energy of the structure after cleavage and the energy of the structure in the initial state by the area of the cleavage surface, the cleavage energy, which is a measure of the ease of cleavage on each surface, is calculated. The energy of the structure is an energy that takes into consideration the kinetic energy of electrons and the interaction between atoms, atoms-electrons, and electrons with respect to atoms and electrons contained in the structure.

As a result of the calculation, the cleavage energy of the first surface is 2.60 J / m ² , the cleavage energy of the second surface is 0.68 J / m ² , the cleavage energy of the third surface is 2.18 J / m ² , It was found that the cleavage energy of the 4th surface was 2.12 J / m ² (see the table below).

According to this calculation, the cleavage energy in the second surface is the lowest in the InGaZnO ₄ crystal structure shown in FIG. That is, it can be seen that the surface between the Ga—Zn—O layer and the Ga—Zn—O layer is the most easily cleaved surface (cleavage surface). Therefore, in this specification, the term “cleavage surface” indicates the second surface that is the most easily cleaved surface.

Since the second surface between the Ga—Zn—O layer and the Ga—Zn—O layer has a cleavage plane, the InGaZnO ₄ crystal shown in FIG. 10A is equivalent to two second surfaces. It can be separated on the other side. Therefore, when ions and the like collide with the target, it is thought that a wafer-like unit (we call this a pellet) cleaved at the surface with the lowest cleavage energy pops out as a minimum unit. In that case, the InGaZnO ₄ pellets are three layers of a Ga—Zn—O layer, an In—O layer, and a Ga—Zn—O layer.

  In addition, a third surface (a crystal plane between the Ga—Zn—O layer and the In—O layer, which is parallel to the (001) plane (or the ab plane)) (the third plane ( 110), and the fourth plane (the crystal plane parallel to the (100) plane (or bc plane)) has a low cleavage energy, so the planar shape of the pellet is mostly triangular or hexagonal. It is suggested.

[Film density]
Next, the density of the In-M-Zn oxide film was evaluated. An nc-OS film was formed by a DC sputtering method using a polycrystalline In—Ga—Zn oxide of In: Ga: Zn = 1: 1: 1 as a target. The pressure was 0.4 Pa, the deposition temperature was room temperature, the power source was 100 W, argon and oxygen were used as deposition gases, and the respective flow rates were 98 sccm for argon and 2 sccm for oxygen. The density of the obtained In—Ga—Zn oxide was 6.1 g / cm ³ . Here, from Non-Patent Document 2, the density of single-crystal InGaZnO ₄ is 6.357 g / cm ³ . Also, JCPDS card, No. As described in 00-038-1097, the density of single crystal In ₂ Ga ₂ ZnO ₇ is known to be 6.494 g / cm ³ . Thus, it is found that the obtained nc-OS film is an excellent film having a high density.

  The density of the In-M-Zn oxide film that is an oxide semiconductor film of one embodiment of the present invention is preferably, for example, 85% or more of the density of single crystals having substantially the same atomic ratio, more preferably 90% or more, More preferably 95% or more.

Or, when element M is gallium, the density of the oxide semiconductor film which is one embodiment of the present invention, for example 5.7 g / cm ³ or more 6.49 g / cm ³ or less are preferred, 5.75 g / cm ³ or more 6.49 g / cm ³ or less are preferred, 5.8 g / cm ³ or more 6.33 g / cm ³ and more preferably less, further preferably 5.85 g / cm ³ or more 6.33 g / cm ³ or less.

  Here, the substantially same atomic ratio means that, for example, the difference in the atomic ratio of each other is within 10%.

Here, for example, the density of the single crystal may be estimated from the density of two or more In-M-Zn oxide films having different atomic ratios. Here, the density of a single crystal having an atomic ratio of In: M: Zn = 1: 1: 1 is D ₁ , and the density of a single crystal having an atomic ratio of In: M: Zn = 2: 2: 1 is D ₂ . Indium atomic ratio of the element M and zinc is 1: 1: Density of In-M-Zn oxide film is 0.8, is expected to take values between _{D 1} and _{D 2.} Therefore, as the density of the single crystal, for example, an average value of D ₁ and D ₂ may be calculated and referred to, or a value of either D ₁ or D ₂ , for example, a value closer to the atomic ratio may be referred to. Good. When calculating the average value using D ₁ and D ₂ , for example, 0.6 × D ₁ + 0.4 × D ₂ may be used. The density of a single crystal whose atomic ratio is In: M: Zn = A: B: C is D _α , and the density of a single crystal whose atomic ratio is In: M: Zn = D: E: F is D _β To do. The density of a single crystal having an atomic ratio of In: M: Zn = X: Y: Z may be calculated as follows, for example.

First, α and β are determined so that (αA + βD) :( αB + βE) :( αC + βF) = X: Y: Z. Next, using the obtained α and β, the density of the single crystal may be calculated as {α / (α + β)} D _α + {β / (α + β)} D _β .

  Next, an example of a method for manufacturing the nc-OS film is described.

  As a general technique for forming an oxide semiconductor film, for example, a sputtering method, a chemical vapor deposition (CVD) method (a metal organic chemical deposition (MOCVD) method, an atomic layer deposition (ALD) method, or plasma chemistry) is used. Vapor deposition (including PECVD), vacuum evaporation, or pulsed laser deposition (PLD).

  The nc-OS film is preferably formed by a sputtering method. As a target used for the sputtering method, an In-M-Zn oxide can be used.

  The target preferably includes a polycrystalline In-M-Zn oxide. For example, in the case where a target including a polycrystalline In-M-Zn oxide is used, the target has cleavage properties and an nc-OS film can be easily formed, which is more preferable.

  As a target, an In-M-Zn oxide can be manufactured using a mixture of indium oxide, an oxide including the element M, and zinc oxide. A target including a polycrystalline In-M-Zn oxide may be used. It is preferable to use it.

  The nc-OS film can be formed at about room temperature, which is preferable. For example, it may be formed without heating the substrate, which is preferable. Further, for example, the atmosphere in the chamber may be heated preferably at room temperature to 500 ° C., more preferably at 200 ° C. to 400 ° C.

[Atom ratio]
Here, for example, an In-M-Zn oxide film is preferably used as the oxide semiconductor film which is one embodiment of the present invention. The atomic ratio of In, M, and Zn included in the In-M-Zn oxide is In: M: Zn = x: y: z.

  For the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention, for example, the ratio of indium is preferably increased.

  In addition, the number of grain boundaries in the oxide semiconductor film is preferably as small as possible. As examples of the non-single-crystal oxide semiconductor film with few grain boundaries, an nc-OS film and a CAAC-OS film can be given. The oxide semiconductor film may include both the nc-OS film and the CAAC-OS film.

  The oxide semiconductor film which is one embodiment of the present invention preferably includes a region (nc structure) where a diffraction pattern of the nc-OS film is observed when nanobeam electron diffraction is performed. The oxide semiconductor film which is one embodiment of the present invention includes a region where a diffraction pattern of the nc-OS film is observed and a region (CAAC structure) where the diffraction pattern of the CAAC-OS film is observed. May be.

  The oxide semiconductor film which is one embodiment of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. In the oxide semiconductor film which is one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, and 95% or more and 100% or less. It is preferably 98% or more and 100% or less, and more preferably 99% or more and 100% or less.

  The oxide semiconductor film which is one embodiment of the present invention may be a stack of a plurality of films. Further, the nc ratio and the CAAC ratio of each of the plurality of films may be different. In addition, at least one of the stacked films preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. Of the plurality of stacked films, at least one film preferably has a sum of the nc ratio and the CAAC ratio of 80% or more, preferably 90% or more and 100% or less, and 95% or more and 100 % Or less, preferably 98% or more and 100% or less, and more preferably 99% or more and 100% or less.

As shown in FIG. 6, when In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and fired at 1350 ° C., the solid solution region becomes wider by increasing the ratio of zinc. Is described in Non-Patent Document 1. Here, in some cases, the CAAC ratio of the oxide semiconductor film of one embodiment of the present invention is further increased by setting the atomic ratio of the In—Ga—Zn oxide in a range in which a solid solution region can be obtained. Therefore, in some cases, the nc ratio of the oxide semiconductor film of one embodiment of the present invention can be further increased by reducing the ratio of zinc. The atomic ratio of indium, element M, and zinc included in the oxide semiconductor film is indium: element M: zinc = x: y: z. For example, the nc ratio may be further increased by increasing the ratio of x + y to z, that is, (x + y) / z. Specifically, for example, (x + y)> z is preferable, (x + y) ≧ 1.5z is preferable, and (x + y) ≧ 2z is preferable.

  In addition, a crystal grain having a spinel structure is mixed with a CAAC-OS film or an nc-OS film, so that a clear grain boundary or boundary portion may be formed in some cases. Therefore, it is preferable to keep away from the number ratio of atoms in which a spinel crystal is more easily formed.

  Therefore, the atomic ratios x, y, and z of In, the element M, and zinc included in the In-M-Zn oxide film which is the oxide semiconductor film of one embodiment of the present invention are within the region 13 illustrated in FIG. The ratio of the number of atoms is preferably, and the ratio of the number of atoms in the region 14 shown in FIG. 4B is more preferable. Here, the region 13 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate. V (x: y: z = 1: 2: 3), fourth coordinate S (x: y: z = 1: 0: 1), and fifth coordinate T (x: y: z = 8: 0: 1), the sixth coordinates U (x: y: z = 6: 2: 1), and the first coordinates K are within a region connected in order by a line segment. Note that the region 13 includes a line segment connecting six points. The region 13 includes all coordinates. The region 14 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate. V (x: y: z = 1: 2: 3), fourth coordinate W (x: y: z = 7: 1: 8), and fifth coordinate X (x: y: z = 7: 1: 1), the sixth coordinates U (x: y: z = 6: 2: 1), and the first coordinates K are within a region connected in order by a line segment. Note that the region 14 includes a line segment connecting six points. The area 14 includes all coordinates.

  In the case where the oxide semiconductor film is formed by a sputtering method, the atomic ratio of the obtained film may deviate from the atomic ratio of the target. In particular, zinc may have a zinc ratio in the resulting film smaller than the target zinc ratio. Specifically, the ratio of zinc in the obtained film may be, for example, about 40 atomic% or more and about 90 atomic% or less of the ratio of target zinc.

  Here, when an In—Ga—Zn oxide film was formed by a sputtering method, the relationship between the atomic ratio of the target to be used and the atomic ratio of the obtained film was examined.

  As film forming conditions, argon and oxygen were used as the film forming gas, and the oxygen flow rate ratio was 33%. Here, the oxygen flow rate ratio is an amount represented by oxygen flow rate ÷ (oxygen flow rate + argon flow rate) × 100 [%]. The pressure was in the range of 0.4 Pa to 0.7 Pa, the substrate temperature was 200 ° C. to 300 ° C., and the power source power was 0.5 kW (DC).

  FIG. 23 shows the relationship between the ratio of the atomic ratio when focusing on the two elements of the target and the residual ratio of zinc. The numbers in the figure represent the target atomic ratio of In: Ga: Zn. Here, the residual ratio of zinc will be described. The value obtained by dividing the value of the zinc term in the atomic ratio of the obtained film by the sum of the values of the indium, gallium, and zinc terms of the film is defined as Zn (Film). In addition, a value obtained by dividing the value of the zinc term in the target atomic ratio by the sum of the values of the target indium, gallium, and zinc is Zn (Target). Here, the residual ratio of zinc is defined as a value represented by A = Zn (Film) ÷ Zn (Target) × 100 [%].

  In addition, the atomic ratio of indium, gallium, and zinc in the In—Ga—Zn oxide target to be used is represented as a: b: c.

  FIG. 23A shows the value (c / b) of the ratio of zinc to the target gallium on the horizontal axis, and FIG. 23B shows the value of the ratio of gallium to the atomic ratio of indium on the target (b / b) on the horizontal axis. FIG. 23C shows the value of a ratio of zinc to indium of the target (c / a) on the horizontal axis. Each vertical axis indicates the residual ratio A of zinc.

  Here, it can be seen from FIG. 23 that the residual ratio of zinc in the film obtained by the sputtering method is approximately 50% or more and 90% or less. Moreover, it can be said that indium and gallium do not change greatly from the atomic ratio of the target as compared with zinc. For example, when the value of the ratio of zinc to gallium (c / b) of the target is 1, the residual ratio A of zinc is about 66%, 2 is about 74%, and 3 is about 83%. is there.

  Further, FIG. 23A shows that there is a good correlation between the ratio of the ratio of zinc to the target gallium (c / b) and the residual ratio of zinc. That is, the residual rate is lower when the amount of zinc is smaller than that of gallium.

  In view of the above, in order to obtain the oxide semiconductor film in the region 13 illustrated in FIG. 4A by using the sputtering method, for example, the value of the ratio of the target zinc to the value of the target film zinc ratio Is preferably 1.7 times or more, more preferably 1.5 times or more. Therefore, it is preferable that the target indium, gallium, and zinc have the atomic ratio of the region 15 shown in FIG. Here, the region 15 includes a first coordinate K (a: b: c = 8: 14: 7), a second coordinate R (a: b: c = 2: 4: 3), and a third coordinate. Y (a: b: c = 1: 2: 5.1), fourth coordinate Z (a: b: c = 1: 0: 1.7), and fifth coordinate T (a: b: c = 8: 0: 1), the sixth coordinate U (a: b: c = 6: 2: 1), and the first coordinate K are within the region connected by line segments in order. . Note that the region 15 includes a line segment connecting six points. Region 15 includes all coordinates.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, an example of a transistor including an oxide semiconductor film which is one embodiment of the present invention will be described.

[Example 1 of a transistor]
An example of a transistor including an oxide semiconductor film will be described with reference to FIGS.

  12A shows a top view of the transistor 100. FIG. 12B shows a cross section taken along the alternate long and short dash line X-X ′ shown in FIG. 12A, and FIG. 12C shows a cross section taken along the alternate long and short dash line Y-Y ′. The transistor 100 illustrated in FIG. 12 includes a substrate 50, an insulating film 51 in contact with the upper surface of the substrate 50, an insulating film 114 in contact with the upper surface of the insulating film 51, a semiconductor layer 101 in contact with the upper surface of the insulating film 114, and a conductive layer 104a. And the conductive layer 104b, the gate insulating film 102 over the semiconductor layer 101, and the gate electrode 103 which overlaps with the semiconductor layer 101 with the gate insulating film 102 interposed therebetween. An insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100. In addition, the transistor 100 may include the conductive layer 105. Further, it is not necessary to provide an insulating film between the substrate 50 and the insulating film 114.

  The semiconductor layer 101 may be formed with a single layer, and more preferably with a stacked structure of first to third layers. The second layer is provided on and in contact with the first, and the third layer is provided on and in contact with the second layer. Here, in the transistor of one embodiment of the present invention, the first layer and the third layer have a region through which a current hardly flows as compared to the second layer. Therefore, the first layer and the third layer may be referred to as insulator layers. Therefore, as in the example illustrated in FIGS. 12A and 12B, the semiconductor layer 101 is preferably formed using a stacked structure of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c. Alternatively, a structure without any of the insulator layer 101a and the insulator layer 101c may be employed. In the example illustrated in FIG. 12, the semiconductor layer 101b is in contact with the upper surface of the insulator layer 101a. In addition, the conductive layer 104a and the conductive layer 104b are in contact with the top surface of the semiconductor layer 101b and are separated in a region overlapping with the semiconductor layer 101b. The insulator layer 101c is in contact with the upper surface of the semiconductor layer 101b. The gate insulating film 102 is in contact with the upper surface of the insulator layer 101c. The gate electrode 103 overlaps the semiconductor layer 101b with the gate insulating film 102 and the insulator layer 101c interposed therebetween.

  An insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100. The insulating film 112 and the insulating film 113 will be described in detail in an embodiment described later.

  The conductive layer 104a and the conductive layer 104b function as a source electrode or a drain electrode. Alternatively, a voltage lower or higher than that of the source electrode may be applied to the conductive layer 105 so that the threshold voltage of the transistor is changed in a positive direction or a negative direction. By varying the threshold voltage of the transistor in the positive direction, normally-off in which the transistor is turned off (off state) even when the gate voltage is 0 V may be realized. Note that the voltage applied to the conductive layer 105 may be variable or fixed. In the case where the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage may be connected to the conductive layer 105. Further, the conductive layer 105 may be connected to the gate electrode 103.

  The upper surface of the insulating film 114 is preferably planarized by a planarization process using a CMP (Chemical Mechanical Polishing) method or the like.

  The insulating film 114 preferably contains an oxide. In particular, an oxide material from which part of oxygen is released by heating is preferably included. It is preferable to use an oxide containing oxygen in excess of that in the stoichiometric composition. Part of oxygen is released by heating from the oxide film containing oxygen in excess of the stoichiometric composition. Oxygen released from the insulating film 114 is supplied to the semiconductor layer 101 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than that in the stoichiometric composition has, for example, a desorption amount of oxygen in terms of oxygen atoms in temperature-programmed desorption gas spectroscopy analysis (TDS analysis). The oxide film has a thickness of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  In order to contain excess oxygen in the insulating film 114, a region containing excess oxygen may be formed by introducing oxygen into the insulating film 114. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 which has been formed, so that a region containing excess oxygen is formed. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  The semiconductor layer 101 includes an oxide semiconductor. An oxide semiconductor is preferably formed using a semiconductor material having a wider band gap and lower carrier density than silicon because current in an off state of the transistor can be reduced. In addition, since the semiconductor layer 101 includes an oxide semiconductor, a change in electrical characteristics is suppressed and a highly reliable transistor can be realized.

  Here, as the semiconductor layer 101, for example, the oxide semiconductor described in Embodiment 1 or 2 can be used.

Note that in this specification and the like, the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁷ / cm ^3, less than 1 × 10 ¹⁵ / cm ³ , or less than 1 × 10 ¹³ / cm ³ when it is substantially intrinsic. It is. By making the oxide semiconductor layer highly purified and intrinsic, stable electrical characteristics can be imparted to the transistor.

  Here, the case where a stacked film of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c is used as the semiconductor layer 101 will be described in detail. The semiconductor layer 101b is preferably formed using an oxide having an electron affinity higher than those of the insulator layers 101a and 101c. For example, as the semiconductor layer 101b, the electron affinity of the insulator layer 101a and the insulator layer 101c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.000. An oxide larger than 4 eV is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

  When an electric field is applied to the gate electrode by using an oxide having higher electron affinity than the insulator layer 101a and the insulator layer 101c as the semiconductor layer 101b, the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c A channel is formed in the semiconductor layer 101b having a high electron affinity. Here, when a channel is formed in the semiconductor layer 101b, for example, since the channel formation region is separated from the interface with the gate insulating film 102, the influence of scattering at the interface with the gate insulating film can be reduced. Thus, the field-effect mobility of the transistor can be increased. Here, since the constituent elements are common between the semiconductor layer 101b and the insulator layer 101c as described later, interface scattering hardly occurs.

  In the case where a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or the like is used for the gate insulating film, silicon contained in the gate insulating film may be mixed into the oxide semiconductor film. When silicon is contained in the oxide semiconductor film, crystallinity of the oxide semiconductor film, carrier mobility, or the like may be reduced. Therefore, the insulator layer 101c is preferably provided between the semiconductor layer 101b and the gate insulating film in order to reduce the impurity concentration of the semiconductor layer 101b in which the channel is formed, for example, the silicon concentration. For the same reason, in order to reduce the influence of impurity diffusion from the insulating film 114, the insulator layer 101 a is preferably provided between the semiconductor layer 101 b and the insulating film 114.

  For example, an oxide semiconductor film containing indium, the element M, and zinc may be used as the semiconductor layer 101b. For example, the oxide semiconductor film described in Embodiment 1 or 2 is preferably used.

  For example, an oxide having a large energy gap is used for the semiconductor layer 101b. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.7 eV or less, more preferably 2.8 eV or more and 3.3 eV or less.

  Next, the insulator layer 101a and the insulator layer 101c will be described. For example, the insulator layer 101a and the insulator layer 101c are oxides including one or more elements other than oxygen included in the semiconductor layer 101b, or two or more elements. Since the insulator layer 101a and the insulator layer 101c are composed of one or more elements other than oxygen or two or more elements constituting the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b, and the semiconductor layer 101b Interface states are unlikely to be formed at the interface with the insulator layer 101c.

  Here, the band structure is shown in FIG. FIG. 11 shows the vacuum level (denoted as vacuum level), the energy at the lower end of the conduction band (denoted as Ec) and the energy at the upper end of the valence band (denoted as Ev).

  Here, in some cases, there is a mixed region of the insulator layer 101a and the semiconductor layer 101b between the insulator layer 101a and the semiconductor layer 101b. Further, in some cases, there is a mixed region of the semiconductor layer 101b and the insulator layer 101c between the semiconductor layer 101b and the insulator layer 101c. In the mixed region, the interface state density is low. Therefore, the stack of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c has a band structure in which energy continuously changes (also referred to as a continuous junction) in the vicinity of each interface.

  At this time, electrons move mainly in the semiconductor layer 101b, not in the insulator layer 101a and the insulator layer 101c. As described above, by reducing the interface state density at the interface between the insulator layer 101a and the semiconductor layer 101b and the interface state density at the interface between the semiconductor layer 101b and the insulator layer 101c, electrons in the semiconductor layer 101b are reduced. The movement is hardly hindered, and the on-state current of the transistor can be increased.

  Note that although FIG. 11 illustrates the case where the insulator layers 101a and 101c have the same Ec, they may be different from each other. For example, the insulator layer 101c may have higher energy than the insulator layer 101a.

  As shown in FIG. 12B, the side surface of the semiconductor layer 101b is in contact with the conductive layer 104a and the conductive layer 104b. In addition, as illustrated in FIG. 12C, the semiconductor layer 101b can be electrically surrounded by an electric field of the gate electrode 103 (a structure of a transistor in which the semiconductor is electrically surrounded by an electric field of a conductor is a surrounded channel). (S-channel structure). When the gate electrode 103 is provided so as to face the upper surface and the side surface of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the upper surface of the semiconductor layer 101b but also in the whole (bulk). In the s-channel structure, a large current can flow between the source and the drain of the transistor, and a current (on-state current) during conduction can be increased.

  Since a high on-state current can be obtained, the s-channel structure can be said to be a structure suitable for a miniaturized transistor. Since a transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high integration. For example, the transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more. Preferably, it has a region of 20 nm or less. In particular, the smaller the channel width, the wider the region in which the channel is formed inside the semiconductor layer 101b. Therefore, the finer the contribution, the higher the contribution to the on-current.

  As the insulator layer 101a and the insulator layer 101c, for example, an In-M-Zn oxide can be used.

  Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, for example, the insulator layer 101c may include indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

  The insulator layer 101c more preferably contains gallium oxide. When the insulator layer 101c contains gallium oxide, a lower off-state current may be realized in some cases.

  The insulator layer 101a and the insulator layer 101c are preferably formed using an nc-OS film or a CAAC-OS film. Here, by increasing the nc ratio or the CAAC ratio of the insulator layer 101a or the insulator layer 101c, for example, defects can be reduced. Further, for example, a region having a spinel crystal can be reduced. Further, for example, carrier scattering can be reduced. Further, for example, a film having a high blocking ability against impurities can be obtained. In addition, entry of impurities into the semiconductor layer 101b can be suppressed, and the impurity concentration in the semiconductor layer 101b can be reduced.

  The nc ratio of the insulator layer 101a and the insulator layer 101c is preferably 10% or more, preferably 30% or more, preferably 50% or more, preferably 80% or more, preferably 90% or more, and preferably 95% or more. .

Here, a case where the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are In-M-Zn oxide is considered. In having the insulator layer 101a, the atomic ratio of the element M and Zn and _{x a, y} a, and _{z a.} Similarly, In having the semiconductor layer 101b, the atomic ratio of the element M and Zn and _x b, _{y b} and _{z b.} Similarly, the atomic ratio of In, the element M, and Zn included in the insulator layer 101c is x _c , y _c, and z _c . Each preferable value will be described below.

x _b , y _b, and z _b preferably take one of the ranges of the region 11, the region 12, the region 13, and the region 14 shown in FIGS. 1, 2A, and 4.

It is preferable that the insulator layer 101a and the insulator layer 101c have no or few spinel crystal structures. Therefore, it is preferable that x _a : y _a : z _a and x _c : y _c : z _c are within the range of the region 11 in FIG. 1, for example, and have values with a lower electron affinity than the semiconductor layer 101b. .

  Here, in order to make the electron affinity of the semiconductor layer 101b larger than that of the insulator layer 101a and the insulator layer 101c, for example, the indium content of the semiconductor layer 101b is preferably higher than that of the insulator layer 101a and the insulator layer 101c. .

For _{example, x b / (x b +} y b + z b)> x a / (x a + y a + z a), and _{x b / (x b + y} b + z b)> x c / (x c + y c + z c) It is preferable to satisfy.

For example, x _a / (x _a + y _a ) <0.5 is preferable, x _a / (x _a + y _a ) <0.33 is more preferable, and x _a / (x _a + y _a is more preferable. ) <0.25. Preferably, x _b / (x _b + y _b ) ≧ 0.25, and more preferably x _b / (x _b + y _b ) ≧ 0.34. Further, preferably, x _c / (x _c + y _c ) <0.5, more preferably x _c / (x _c + y _c ) <0.33, and further preferably x _c / (x _c + y _c ). <0.25.

Alternatively, x _a , y _a , z _a , and x _c , y _c , z _c preferably have a ratio of the number of atoms in the region 16 illustrated in FIG. Here, the region 16 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate. L (x: y: z = 2: 5: 7), the fourth coordinate M (x: y: z = 51: 149: 300), and the fifth coordinate B (x: y: z = 1: 4:10), the sixth coordinates C (x: y: z = 1: 1: 4), the seventh coordinates A (x: y: z = 2: 2: 1), and the first coordinates This is an area in which the coordinates K are connected by line segments in order. The region 16 includes all coordinates.

  Note that in the case where the transistor has an s-channel structure, a channel is formed in the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-state current of the transistor. For example, the semiconductor layer 101b may have a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, for example, the semiconductor layer 101b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used.

  In order to increase the on-state current of the transistor, the thickness of the insulator layer 101c is preferably as small as possible. For example, the insulator layer 101c may have a region less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the insulator layer 101c has a function of blocking entry of elements other than oxygen (hydrogen, silicon, and the like) included in the adjacent insulator into the semiconductor layer 101b where a channel is formed. Therefore, the insulator layer 101c preferably has a certain thickness. For example, the insulator layer 101c may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. The insulator layer 101c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the gate insulating film 102 and the like.

  In order to increase reliability, it is preferable that the insulator layer 101a is thick and the insulator layer 101c is thin. For example, the insulator layer 101a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulator layer 101a, the distance from the interface between the adjacent insulator and the insulator layer 101a to the semiconductor layer 101b where a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, the insulator layer 101a having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

  When the oxide semiconductor film contains a large amount of hydrogen or moisture, donor levels due to hydrogen may be formed. The formation of the donor level may shift the threshold value of the transistor in the negative direction. Therefore, it is preferable that dehydration treatment (dehydrogenation treatment) be performed after the oxide semiconductor film is formed so that hydrogen or moisture is removed so that impurities are included as little as possible.

  Note that oxygen may be reduced at the same time due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to supply oxygen after the dehydration treatment to fill oxygen vacancies in the oxide semiconductor film. In this specification and the like, supplying oxygen to an oxide semiconductor film may be referred to as oxygenation treatment. Alternatively, increasing the proportion of oxygen contained in the oxide semiconductor film higher than the stoichiometric composition may be referred to as peroxygenation treatment.

In this way, hydrogen or water is removed by dehydration treatment, and oxygen deficiency is compensated by oxygenation treatment, so that i-type (intrinsic) or substantially i-type (intrinsic) is almost unlimited. The oxide semiconductor film can be realized. Note that substantially intrinsic means that the number of carriers derived from a donor in the oxide semiconductor film is extremely small (near zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It means 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ³ or less.

A transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current. For example, the off-state current of a transistor including an oxide semiconductor film is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 × 10 ⁻²⁴ A at room temperature (about 25 ° C.). 1 × 10 ⁻¹⁵ A or less, preferably 1 × 10 ⁻¹⁸ A or less, more preferably 1 × 10 ⁻²¹ A or less at 85 ° C. Here, the off-state current refers to a drain current when the transistor is off. A transistor in an off state refers to a state where the gate voltage is sufficiently smaller than a threshold value in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or higher, 2 V or higher, or 3 V or lower than the threshold value, the transistor is turned off.

  One of the conductive layer 104a and the conductive layer 104b functions as a source electrode, and the other functions as a drain electrode.

  The conductive layer 104a and the conductive layer 104b each have a single-layer structure or a stacked structure using a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the metal as a main component. Used as For example, a single layer structure of an aluminum film containing silicon, a two layer structure in which an aluminum film is stacked on a titanium film, a two layer structure in which an aluminum film is stacked on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film Two-layer structure to stack, two-layer structure to stack a copper film on a titanium film, two-layer structure to stack a copper film on a tungsten film, a titanium film or a titanium nitride film, and an overlay on the titanium film or titanium nitride film A three-layer structure in which an aluminum film or a copper film is stacked and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper layer stacked on the molybdenum film or the molybdenum nitride film There is a three-layer structure in which films are stacked and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

  The gate insulating film 102 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn-based metal oxide, or silicon nitride, and is stacked or formed as a single layer.

As the gate insulating film 102, hafnium silicate (HfSiO _x ), hafnium silicate added with nitrogen (HfSi _x O _y N _z ), hafnium aluminate added with nitrogen (HfAl _x O _y N _z ), yttrium oxide High-k materials such as

  As the gate insulating film 102, an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide is used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material thereof can be used.

  As the gate insulating film 102, as with the insulating film 114, an oxide insulating film containing more oxygen than that in the stoichiometric composition is preferably used.

  Note that when a specific material is used for the gate insulating film, electrons can be trapped in the gate insulating film under specific conditions, and the threshold voltage can be shifted in the positive direction. For example, a material having a high electron capture level such as hafnium oxide, aluminum oxide, or tantalum oxide is used for a part of the gate insulating film, such as a stacked film of silicon oxide and hafnium oxide, and a higher temperature (use of a semiconductor device) The temperature of the gate electrode is higher than the potential of the source electrode or the drain electrode at a temperature higher than the temperature or storage temperature, or 125 ° C. to 450 ° C., typically 150 ° C. to 300 ° C. By maintaining for 1 second or more, typically 1 minute or more, electrons move from the semiconductor layer toward the gate electrode, and some of them are captured by the electron capture level.

  The gate electrode 103 is formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy including the above-described metal, or an alloy combining the above-described metals. Can do. Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used. The gate electrode 103 may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film is stacked on the titanium film, and a titanium film is further formed thereon is there. Alternatively, an alloy film or a nitride film in which one or more metals selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.

  The gate electrode 103 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal can be used.

  In addition, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, and an In—Zn-based film are provided between the gate electrode 103 and the gate insulating film 102. An oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, or the like), or the like may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and have a value larger than the electron affinity of the oxide semiconductor. Therefore, the threshold voltage of the transistor including the oxide semiconductor is increased in the positive direction. Therefore, a switching element having a so-called normally-off characteristic can be realized. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of the semiconductor layer 101, specifically, 7 atomic% or more is used.

  The above is the description of the transistor 100.

  Note that the channel length means, for example, in a top view of a transistor, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed , The distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate electrode overlap, or a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as an “enclosed channel width (SCW : Surrounded Channel Width) ”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

  Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

[Transistor example 2]
An example of a structure which is different from that in FIG. 12 of the transistor including an oxide semiconductor film which is one embodiment of the present invention will be described with reference to FIGS. 13A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 13C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG.

  The transistor 100 includes a gate electrode 203a that functions as a gate electrode over the substrate 50, a gate insulating film 202 over the substrate 50 and the gate electrode 203a, a semiconductor layer 201 over the gate insulating film 202, and the semiconductor layer 201 electrically. The conductive layer 204a and the conductive layer 204b function as a source electrode and a drain electrode to be connected. Further, the insulating film 214, the insulating film 216, and the insulating film 218 are sequentially stacked over the transistor 100, more specifically, over the conductive layer 204a, the conductive layer 204b, and the semiconductor layer 201.

  Next, components included in the transistor of this embodiment will be described.

  For the gate electrode 203a functioning as the gate electrode of the transistor 100, the description of the gate electrode 103 may be referred to.

  For the gate insulating film 202 which functions as the gate insulating film of the transistor 100, the description of the gate insulating film 102 may be referred to. Alternatively, a stacked film including two or more layers may be used as the gate insulating film 202. For example, as shown in FIG. 13, a two-layer structure of a gate insulating film 202a and a gate insulating film 202b may be used. In that case, for example, a film having a function as a blocking film for suppressing permeation of oxygen may be used for the lower layer, here the gate insulating film 202a. As a film having a function as a blocking film, for example, a barrier film 111 described later may be referred to.

  As the semiconductor layer 201, the oxide semiconductor film described in Embodiment 1 or 2 may be used. For the semiconductor layer 201, the description of the semiconductor layer 101 may be referred to. The semiconductor layer 201 may be a stacked film including two or more layers.

  The insulating film 214, the insulating film 216, and the insulating film 218 have a function as a protective insulating film of the transistor 100. The insulating film 214 also functions as a damage mitigating film for the semiconductor layer 201 when the insulating film 216 is formed.

  For example, the insulating film 214 and the insulating film 216 preferably have a region containing oxygen in excess of the stoichiometric composition (oxygen-excess region) like the above-described insulating film 114.

The insulating film 214 preferably has a small amount of defects. Typically, the ESR measurement shows that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 3 × 10 ¹⁷ spins / cm. It is preferable that it is ³ or less. When the density of defects included in the insulating film 214 is large, oxygen is bonded to the defects, so that the amount of oxygen transmitted through the insulating film 214 is reduced.

  Note that in the insulating film 214, all oxygen that enters the insulating film 214 from the outside does not move to the outside of the insulating film 214, and some oxygen remains in the insulating film 214. In addition, oxygen enters the insulating film 214 and oxygen contained in the insulating film 214 may move to the outside of the insulating film 214, whereby oxygen may move in the insulating film 214. When an oxide insulating film which can transmit oxygen is formed as the insulating film 214, oxygen released from the insulating film 216 provided over the insulating film 214 is transferred to the semiconductor layer 201 through the insulating film 214. Can do.

The insulating film 214 includes an oxide insulating film in which the level density of nitrogen oxide is low between the energy (E _{v — os} ) at the upper end of the valence band of the oxide semiconductor film and the energy (E _{c — os} ) at the lower end of the conduction band. Can be used. As an oxide insulating film having a low nitrogen oxide level density between E _{v — os} and E _{c — os,} a silicon oxynitride film with a low nitrogen oxide emission amount, an aluminum oxynitride film with a low nitrogen oxide emission amount, or the like Can be used.

Note that a silicon oxynitride film with a small amount of released nitrogen oxides is a film having a larger amount of released ammonia molecules than a released amount of nitrogen oxides in the temperature programmed desorption gas analysis method. The discharge amount is 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. Note that the amount of ammonia molecules released is the amount released by heat treatment at a film surface temperature of 50 ° C. or higher and 650 ° C. or lower, preferably 50 ° C. or higher and 550 ° C. or lower.

Nitrogen oxide (NO _x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO forms a level in the insulating film 214 or the like. The level is located in the energy gap of the semiconductor layer 201. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 214 and the semiconductor layer 201, the level may trap electrons on the insulating film 214 side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating film 214 and the semiconductor layer 201, so that the threshold voltage of the transistor is shifted in the positive direction.

  Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating film 214 reacts with ammonia contained in the insulating film 216 in the heat treatment, nitrogen oxide contained in the insulating film 214 is reduced. Therefore, electrons are not easily trapped at the interface between the insulating film 214 and the semiconductor layer 201.

  Note that the insulating film 214 has a function of protecting the back channel region of the semiconductor layer 201 by being in contact with the semiconductor layer 201 on a side opposite to a region where a channel is formed (hereinafter referred to as a back channel region) in the semiconductor layer 201. Have

By using an oxide insulating film having a low nitrogen oxide level density between E _{v — os} and E _{c — os} as the insulating film 214, a shift in threshold voltage of the transistor can be reduced. Variations in electrical characteristics can be reduced.

In addition, the oxide insulating film in which the level density of nitrogen oxide is low between E _{v — os} and E _{c — os} has a nitrogen concentration measured by SIMS of 6 × 10 ²⁰ atoms / cm ³ or less.

The insulating film 216 preferably has a small amount of defects. Typically, the ESR measurement indicates that the spin density of a signal appearing at g = 2.001 derived from a dangling bond of silicon is 1.5 × 10 ^18. It is preferably less than spins / cm ³ and more preferably 1 × 10 ¹⁸ spins / cm ³ or less. Note that the insulating film 216 is farther from the semiconductor layer 201 than the insulating film 214, and thus has a higher defect density than the insulating film 214.

  The transistor 100 may have a structure illustrated in FIGS. Here, the transistor 100 illustrated in FIGS. 13A and 13B is a channel-etched transistor, but the transistor 100 illustrated in FIGS. 14 and 15 is a channel-protective transistor.

  14A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 14C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. A transistor 100 illustrated in FIG. 14 includes a gate electrode 203a provided over a substrate 50, a gate insulating film 202 formed over the substrate 50 and the gate electrode 203a, and a semiconductor overlapping with the gate electrode 203a with the gate insulating film 202 interposed therebetween. A pair of layers 201, an insulating film 214 over the gate insulating film 202 and the semiconductor layer 201, an insulating film 216 over the insulating film 214, and a pair of contacts with the semiconductor layer 201 in the openings 141 a and 141 b of the insulating film 214 and the insulating film 216. A conductive layer 204a and a conductive layer 204b are included. The insulating film 218 may be provided over the transistor 100, more specifically, over the conductive layer 204a, the conductive layer 204b, and the insulating film 216.

  15A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 15C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. The transistor 100 illustrated in FIG. 15 is different from the transistor 100 illustrated in FIG. 14 in the shapes of the insulating films 214 and 216. Specifically, the insulating films 214 and 216 of the transistor 100 illustrated in FIG. 15 are provided in an island shape over the channel region of the semiconductor layer 101. Other structures are similar to those of the transistor 100 illustrated in FIG. 14 and have the same effects.

  In each of the transistors 100 illustrated in FIGS. 14 and 15, since the semiconductor layer 201 is covered with the insulating film 214 and the insulating film 216 when the pair of conductive layers 204 a and 204 b is formed, the pair of conductive layers 204 a In addition, the semiconductor layer 201 is not damaged by the etching for forming the conductive layer 204b. Further, when the insulating film 214 and the insulating film 216 are formed using an oxide insulating film containing nitrogen and having a small amount of defects, a transistor in which variation in electrical characteristics is suppressed and reliability is improved can be manufactured. it can.

  In addition, the transistor 100 may include an electrode 203b over the insulating film 218 as illustrated in FIG. 16A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. FIG. 16C corresponds to a drawing, and FIG. 16C corresponds to a cross-sectional view of a cross-sectional surface taken along the alternate long and short dash line Y1-Y2 in FIG. FIG. 16 illustrates a structure in which the electrode 203b is connected to the gate electrode 203a through the opening 142c and the opening 142d provided in the insulating film 214 and the insulating film 216, but the electrode 203b and the gate electrode 203a are not connected. It is good also as a structure. When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the respective electrodes.

  As shown in FIG. 16, the side surface of the semiconductor layer 201 and the electrode 203b face each other in the channel width direction, and further, in the channel width direction, the gate electrode 203a and the electrode 203b are connected to the gate insulating film 202 and the insulating film. 214, by surrounding the semiconductor layer 201 with the insulating film 216 and the insulating film 218 interposed therebetween, the region in which the carrier flows in the semiconductor layer 201 is not only the interface between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201, but also the semiconductor. Since carriers also flow inside the layer 201, the amount of carrier movement in the transistor 100 increases. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is increased. In addition, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201 or an end including the side surface and the vicinity thereof, generation of a parasitic channel on the side surface or the end of the semiconductor layer 201 can be suppressed.

  FIG. 16 illustrates a structure in which the semiconductor layer 201b is stacked over the semiconductor layer 201a as an example of the semiconductor layer 201. Here, for example, the energy of the lower end of the conduction band of the semiconductor layer 201b is closer to the vacuum level than the semiconductor layer 201a. Typically, the energy of the lower end of the conduction band of the semiconductor layer 201b and the conduction band of the semiconductor layer 201a are The difference from the energy at the lower end is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, 2 eV or less, 1 eV or less, 0 .5 eV or less, or 0.4 eV or less.

  As the semiconductor layer 201a, the semiconductor layer 101b described in Embodiment 3 may be referred to. For example, you may refer about the preferable range of the atomic ratio of indium, the element M, and zinc which the semiconductor layer 101b has. For the semiconductor layer 201b, the insulator layer 101c described in Embodiment 3 may be referred to. For example, you may refer about the preferable range of atomic ratio of the indium which the insulator layer 101c has, the element M, and zinc.

[Modification of transistor]
Modification examples of the transistor 100 are illustrated in FIGS. For example, the transistor 100 may have a structure illustrated in FIG. 30 is different from FIG. 12 in the shapes of the conductive layer 104a and the conductive layer 104b. Note that FIG. 30B illustrates a cross section of a plane that passes through the alternate long and short dash line AB illustrated in FIG. 30A and is perpendicular to FIG.

  The transistor 100 may have a structure illustrated in FIG. In FIG. 12, the insulator layer 101c is in contact with the upper surfaces of the conductive layers 104a and 104b, whereas in FIG. 31, it is in contact with the lower surfaces of the conductive layers 104a and 104b. Note that FIG. 31B illustrates a cross section of a plane that passes through the alternate long and short dash line AB illustrated in FIG. 31A and is perpendicular to FIG. With such a structure, when each film forming the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c is formed, the film can be continuously formed without being exposed to the air. , Each interface defect can be reduced.

The transistor 100 may have a structure illustrated in FIG. Note that FIG. 32B illustrates a cross section of a plane that passes through the alternate long and short dash line AB illustrated in FIG. 32A and is perpendicular to FIG. 32 differs from FIG. 12 in that the conductive layer 104a and the conductive layer 104b are not provided. Here, as illustrated in FIG. 32C, the transistor 100 may include a low-resistance layer 171a and a low-resistance layer 171b. The low resistance layer 171a and the low resistance layer 171b preferably function as a source region or a drain region. The low resistance layer 171a and the low resistance layer 171b may be doped with impurities. By adding impurities, the resistance of the semiconductor layer 101 can be reduced. Examples of impurities to be added include argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, zirconium, niobium. It is preferable to add one or more selected from molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. The low resistance layer 171a and the low resistance layer 171b include, for example, the above-described impurity element in the semiconductor layer 101 of 5 × 10 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, and more preferably 2 ×. It is a region including 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ atoms / cm ³ or more. FIG. 32D is an enlarged view of a region 324 in FIG.

  Note that an impurity such as unnecessary hydrogen may be trapped in such a low-resistance region. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region can be lowered, and favorable characteristics can be obtained as the characteristics of the transistor 100.

  The transistor 100 may have a structure illustrated in FIG. 33 differs from FIG. 32 in the shapes of the insulator layer 101c and the gate insulating film 102. In FIG. Note that FIG. 33B illustrates a cross section of a plane that passes through the alternate long and short dash line AB illustrated in FIG. 33A and is perpendicular to FIG.

  In the structure illustrated in FIGS. 30 to 33, the structure in which the insulator layer 101a and the insulator layer 101c are provided in contact with the semiconductor layer 101b has been described; however, either the insulator layer 101a or the insulator layer 101c, or It is good also as a structure which does not provide both.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described as an example in the above embodiment will be described below with reference to FIGS.

  FIG. 34 is a top view illustrating an example of the display device. A display device 700 illustrated in FIG. 34 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702, a source The driver circuit portion 704 and the gate driver circuit portion 706 are provided so as to surround the sealant 712 and the second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Note that although not illustrated in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705.

  The display device 700 includes a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion in a region different from the region surrounded by the sealant 712 over the first substrate 701. An FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the 706 is provided. In addition, an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. A signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708. Various signals and the like supplied from the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the signal line 710.

  In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. . Note that a method for connecting a separately formed driver circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

  The pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a wiring portion or a plurality of transistors, and the semiconductor device of one embodiment of the present invention can be applied. it can.

  In addition, the display device 700 can include various elements. The element includes, for example, a liquid crystal element, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), transistor (Transistor that emits light in response to current), electron-emitting device, electronic ink, electrophoretic device, grating light valve (GLV), plasma display (PDP), display device using MEMS (micro electro mechanical system), Digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electro Potting element, a piezoelectric ceramic display, has at least one such display device using a carbon nanotube. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action may be included. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like. As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

  Note that as a display method in the display device 700, a progressive method, an interlace method, or the like can be used. Further, the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a pen tile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. Note that the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

  In addition, a colored layer (also referred to as a color filter) may be used to display a full color display device using white light (W) in a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like). Good. For example, red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer. By using the colored layer, the color reproducibility can be increased as compared with the case where the colored layer is not used. At this time, white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer. By disposing a region that does not have a colored layer in part, a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having respective emission colors. . By using a self-luminous element, power consumption may be further reduced as compared with the case where a colored layer is used.

  In this embodiment, a structure in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. Note that FIG. 35 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 34, in which a liquid crystal element is used as a display element. FIG. 36 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 34 and has a configuration using an EL element as a display element.

  First, common parts shown in FIGS. 35 and 36 will be described first, and then different parts will be described below.

[Description of common parts of display device]
A display device 700 illustrated in FIGS. 35 and 36 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790 (the capacitor 790a or the capacitor 790b). In addition, the source driver circuit portion 704 includes a transistor 752.

  In addition, the signal line 710 is formed in the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752. Note that the signal line 710 may be a conductive film formed in a different process from the source and drain electrodes of the transistors 750 and 752, for example, a conductive film functioning as a gate electrode. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.

  As the transistor 750 and the transistor 752, the above-described transistor can be used. Although an example in which the structure of the transistor 100 illustrated in FIGS. 13A and 13B is used for the transistor 750 and the transistor 752 is shown here, other transistors described above may be used.

  Further, for the transistor 750 and the transistor 752, for example, the structure of the transistor 100 illustrated in FIGS. In this case, the electrode 203b can be formed using, for example, the same process as the formation of the conductive layer 772 and the conductive layer 784. By using the structure of the transistor 100 illustrated in FIG. 16, for example, the on-state current of the transistor 750 and the transistor 752 can be increased, and the circuit operation speed can be increased. In some cases, the channel width of the transistor 750 or the transistor 752 can be reduced, so that the circuit can be integrated.

  The transistor used in this embodiment includes an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies. The transistor can reduce a current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

  In addition, the transistor used in this embodiment can have a relatively high field-effect mobility, and thus can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, the switching transistor in the pixel portion and the driver transistor used in the driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. In the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

  The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive layer 780, and an FPC 716. Note that the connection electrode 760 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive layer 780.

  In addition, as the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

  By using a flexible substrate, a flexible display device can be manufactured. Since the display device has flexibility, it can be bonded on a curved surface or an irregular shape, and a wide variety of uses can be realized.

  For example, by using a flexible substrate such as a plastic substrate, the display device can be made thinner and lighter. In addition, for example, a display device using a flexible substrate such as a plastic substrate is not easily broken, and can improve durability against an impact when dropped, for example.

  On the second substrate 705 side, a light-blocking film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the colored film 736 are provided.

  A structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure body 778. 35 illustrates the structure in which the structure body 778 is provided on the second substrate 705 side, the present invention is not limited thereto. For example, a structure in which the structure body 778 is provided on the first substrate 701 side as illustrated in FIG. 36, or a structure in which the structure body 778 is provided on both the first substrate 701 and the second substrate 705 may be employed.

  In FIGS. 35 and 36, insulating films 764, 766, and 768 are provided over the transistor 750 and the transistor 752.

  The insulating films 764, 766, and 768 can be formed using a material and a manufacturing method similar to those of the insulating films 214, 216, and 218 described in the above embodiment, respectively.

[Configuration Example of Display Device Using Liquid Crystal Element as Display Element]
A display device 700 illustrated in FIG. 35 includes a capacitor 790a. The capacitor 790a has a structure having a dielectric between a pair of electrodes. In more detail, as one electrode of the capacitor 790a, a highly conductive oxide semiconductor film formed through the same process as the oxide semiconductor film functioning as the semiconductor layer of the transistor 750 is used. As the other electrode, a conductive layer 772 electrically connected to the transistor 750 is used. An insulating film 768 is used as a dielectric sandwiched between the pair of electrodes.

  Here, the highly conductive oxide semiconductor film functioning as one of the pair of electrodes of the capacitor 790a is described below.

[Highly conductive oxide semiconductor film]
When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed, hydrogen enters oxygen vacancy sites and donor levels are formed in the vicinity of the conduction band. As a result, the oxide semiconductor has high conductivity and becomes a conductor. A conductive oxide semiconductor can be referred to as an oxide conductor. In general, an oxide semiconductor has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption due to the donor level is small, and the light transmittance is comparable to that of an oxide semiconductor with respect to visible light.

  Here, in each of a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film (OC)). Next, the temperature dependence of resistivity will be described.

  The temperature dependence of the resistivity in the oxide conductor film (OC) is smaller than the temperature dependence of the resistivity in the oxide semiconductor film (OS). Typically, the rate of change in resistivity of the oxide semiconductor film (OC) at 80 K or more and 290 K or less is less than ± 20%. Or the change rate of the resistivity in 150K or more and 250K or less is less than +/- 10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level match or substantially match. Therefore, the oxide conductor film can be used for one electrode of the capacitor 790a. Here, the oxide conductor film can be formed, for example, by forming silicon nitride over In-M-Zn oxide.

  35 includes a liquid crystal element 775. The display device 700 illustrated in FIG. The liquid crystal element 775 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776. The conductive layer 774 is provided on the second substrate 705 side and functions as a counter electrode. A display device 700 illustrated in FIG. 35 can display an image by controlling transmission and non-transmission of light by changing the alignment state of the liquid crystal layer 776 depending on voltages applied to the conductive layers 772 and 774.

  The conductive layer 772 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive layer 772 is formed over the insulating film 768 and functions as a pixel electrode, that is, one electrode of a display element.

  Examples of the conductive layer 772 include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.

  Note that although not illustrated in FIG. 35, an alignment film may be provided on each of the conductive layers 772 and 774 in contact with the liquid crystal layer 776. Although not shown in FIG. 35, an optical member (optical substrate) such as a polarizing member, a retardation member, or an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

  When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

  In the case of employing a horizontal electric field method, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, in order to improve the temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral agent is used for the liquid crystal layer. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic, so that alignment treatment is unnecessary and viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. .

  When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axial Symmetrical Aligned MicroB cell) mode, A Compensated Birefringence (FLC) mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti-Ferroelectric Liquid Crystal) mode, and the like can be used.

  Alternatively, a normally black liquid crystal display device such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. There are several examples of the vertical alignment mode. For example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV mode, and the like can be used.

[Display device using light-emitting element as display element]
A display device 700 illustrated in FIG. 36 includes a capacitor 790b. The capacitor 790b has a structure having a dielectric between a pair of electrodes. More specifically, a conductive film formed in the same step as the conductive film functioning as the gate electrode of the transistor 750 is used as one electrode of the capacitor 790b, and the source of the transistor 750 is used as the other electrode of the capacitor 790b. A conductive film functioning as an electrode or a drain electrode is used. As the dielectric sandwiched between the pair of electrodes, an insulating film functioning as a gate insulating film of the transistor 750 is used.

  In FIG. 36, a planarization insulating film 770 is provided over the insulating film 768.

  As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Alternatively, as illustrated in FIG. 35, the planarization insulating film 770 may not be provided.

  A display device 700 illustrated in FIG. 36 includes a light-emitting element 782. The light-emitting element 782 includes a conductive layer 784, an EL layer 786, and a conductive layer 788. The display device 700 illustrated in FIG. 36 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.

  The conductive layer 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750. The conductive layer 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive layer 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. As the conductive film that transmits visible light, for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflectivity in visible light, for example, a material containing aluminum or silver is preferably used.

  In the display device 700 illustrated in FIG. 36, the insulating film 730 is provided over the planarization insulating film 770 and the conductive layer 784. The insulating film 730 covers part of the conductive layer 784. Note that the light-emitting element 782 has a top emission structure. Therefore, the conductive layer 788 has a light-transmitting property and transmits light emitted from the EL layer 786. In the present embodiment, the top emission structure is illustrated, but is not limited thereto. For example, the present invention can be applied to a bottom emission structure in which light is emitted to the conductive layer 784 side and a dual emission structure in which light is emitted to both the conductive layer 784 and the conductive layer 788.

  A colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 36, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, a display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  A display device illustrated in FIG. 26A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter, referred to as a pixel portion 502) which is disposed outside the pixel portion 502 and includes a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.

  A part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced. When part or all of the driver circuit portion 504 is not formed over the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.

  The pixel portion 502 includes a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The driver circuit portion 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (a data signal). Hereinafter, it has a drive circuit such as a source driver 504b).

  The gate driver 504a includes a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can supply another signal.

  The source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like. The source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can supply another signal.

  The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

  Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scanning lines GL to which the scanning signal is applied, and receives the data signal through one of the plurality of data lines DL to which the data signal is applied. Entered. Also. In each of the plurality of pixel circuits 501, writing and holding of data signals are controlled by the gate driver 504a. For example, the pixel circuit 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a through the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n Is a natural number less than or equal to Y), a data signal is input from the source driver 504b.

  The protection circuit 506 illustrated in FIG. 26A is connected to, for example, the scanning line GL which is a wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to a data line DL that is a wiring between the source driver 504 b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507. Note that the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.

  The protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

  As shown in FIG. 26A, by providing a protection circuit 506 in each of the pixel portion 502 and the driver circuit portion 504, resistance of the display device to overcurrent generated by ESD (Electro Static Discharge) or the like is increased. be able to. However, the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

  FIG. 26A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure. For example, only the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

  In addition, the plurality of pixel circuits 501 illustrated in FIG. 26A can have the structure illustrated in FIG.

  A pixel circuit 501 illustrated in FIG. 26B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be applied to the transistor 550.

  One potential of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Further, a different potential may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

  For example, a driving method of a display device including the liquid crystal element 570 includes a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric mode). , AFLC (Anti Ferroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode, etc. may be used. In addition to the above-described driving methods, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Host mode), and other driving methods for the display device. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

  In the pixel circuit 501 in the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of the data signal by being turned on or off.

  One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter, potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

  For example, in a display device including the pixel circuit 501 in FIG. 26B, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write data.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 550 is turned off. By sequentially performing this for each row, an image can be displayed.

  In addition, the plurality of pixel circuits 501 illustrated in FIG. 26A can have a structure illustrated in FIG.

  A pixel circuit 501 illustrated in FIG. 26C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The transistor described in any of the above embodiments can be applied to one or both of the transistor 552 and the transistor 554.

  One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a signal line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).

  The transistor 552 has a function of controlling data writing of the data signal by being turned on or off.

  One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.

  The capacitor 562 functions as a storage capacitor that stores written data.

  One of a source electrode and a drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

  One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

  As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

  Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

  In the display device including the pixel circuit 501 in FIG. 26C, for example, the pixel circuits 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. Write.

  The pixel circuit 501 in which data is written is brought into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
An example of a semiconductor device using the oxide semiconductor of one embodiment of the present invention is described below.

[Example of semiconductor device]
FIG. 37A is an example of a circuit diagram of the semiconductor device of one embodiment of the present invention. A semiconductor device illustrated in FIG. 37A includes a transistor 100, a transistor 130, a capacitor 150, a wiring WBL, a wiring RBL, a wiring WL, a wiring CL, a wiring BG, and a wiring SL. .

  In the transistor 130, one of a source and a drain is electrically connected to the wiring RBL, the other is electrically connected to the wiring SL, and a gate is electrically connected to one of the source and drain of the transistor 100 and one electrode of the capacitor 150. Connect. In the transistor 100, the other of the source and the drain is electrically connected to the wiring WBL, and the first gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. The wiring BG is electrically connected to the second gate of the transistor 100. Note that a node between the gate of the transistor 130, one of the source and the drain of the transistor 100, and one electrode of the capacitor 150 is referred to as a node FN.

  In the semiconductor device illustrated in FIG. 37A, a potential corresponding to the potential of the wiring WBL is supplied to the node FN when the transistor 100 is in a conductive state (on state). In addition, the transistor 100 has a function of holding the potential of the node FN when the transistor 100 is off (off state). That is, the semiconductor device illustrated in FIG. 37A functions as a memory cell of the memory device. By arranging the semiconductor devices illustrated in FIG. 37A in a matrix, a memory device (memory cell array) can be formed.

  Note that in the case where a display element such as a liquid crystal element or an organic EL (Electroluminescence) element which is electrically connected to the node FN is included, the semiconductor device in FIG. 37A can also function as a pixel of the display device.

  The selection of the conduction state and the non-conduction state of the transistor 100 can be controlled by a potential applied to the wiring WL or the wiring BG. Further, the threshold value of the transistor 100 can be controlled by a potential applied to the wiring WL or the wiring BG. By using a transistor with low off-state current as the transistor 100, the potential of the node FN in a non-conduction state can be held for a long time. Accordingly, the refresh frequency of the semiconductor device can be reduced, and a semiconductor device with low power consumption can be realized. By using, for example, a transistor including an oxide semiconductor film as the transistor 100, a transistor with low off-state current can be realized.

  Note that a constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Information on the potential held in the node FN can be read as data by utilizing the change in the conduction state and the non-conduction state of the transistor 130 due to the change in the apparent threshold voltage.

Note that in order to hold the potential held at the node FN at 85 ° C. for 10 years (3.15 × 10 ⁸ seconds), the value of the off-current per capacitance of 1 fF per channel width of the transistor is 4.3 yA ( It is preferable that the yoct ampere: 1yA is less than 10 ⁻²⁴ A). At this time, it is preferable that the allowable fluctuation of the potential of the node FN is within 0.5V. Alternatively, at 95 ° C., the off-state current is preferably less than 1.5 yA.

  Further, by increasing the capacitance, the potential can be held in the node FN for a longer time. That is, the holding time can be extended.

  In the semiconductor device illustrated in FIG. 37A, information can be written, held, and read as follows by utilizing the feature that the potential of the gate electrode of the transistor 130 can be held.

  Information writing and holding will be described. First, the potential of the wiring WL is set to a potential at which the transistor 100 is turned on, so that the transistor 100 is turned on. Accordingly, the potential of the wiring WBL is supplied to the gate electrode of the transistor 130 and the capacitor 150. That is, predetermined charge is given to the gate electrode of the transistor 130 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as low level charge and high level charge) that gives two different potential levels is given. After that, the potential of the wiring WL is changed to a potential at which the transistor 100 is turned off and the transistor 100 is turned off, whereby the charge given to the gate electrode of the transistor 130 is held (held).

  Since the off-state current of the transistor 100 is extremely small, the charge of the gate electrode of the transistor 130 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the wiring CL in a state where a predetermined potential (constant potential) is applied to the wiring RBL, the wiring SL has different potentials depending on the amount of charge held in the gate electrode of the transistor 130. Take. In general, when the transistor 130 is an n-channel transistor, the apparent threshold V _{th_H} when a high level charge is applied to the gate electrode of the transistor 130 is a low level charge applied to the gate electrode of the transistor 130. This is because it becomes lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the wiring CL necessary for turning on the transistor 130. Therefore, the charge given to the gate electrode of the transistor 130 can be determined by _setting the potential of the wiring CL to a potential V ₀ between V _{th_H} and V _{th_L} . For example, in the case where a high-level charge is applied in writing, the transistor 130 is turned “on” when the potential of the wiring CL becomes V ₀ (> V _{th_H} ). When the low-level charge is _supplied , the transistor 130 remains in the “off state” even when the potential of the wiring CL becomes V ₀ (<V _{th_L} ). Therefore, the stored information can be read by determining the potential of the wiring SL. In order to reduce the number of wirings, for example, WBL and RBL shown in FIG.

Note that in the case of using memory cells arranged in an array, it is necessary to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential at which the transistor 130 is turned off regardless of the state of the gate electrode, that is, a potential smaller than V _{th_H} may be _supplied to the wiring CL. _{Alternatively} , a potential at which the transistor 130 is turned on regardless of the state of the gate electrode, that is, a potential higher than V _{th_L} may be _supplied to the wiring CL.

  The semiconductor device illustrated in FIG. 37B is mainly different from FIG. 37A in that the transistor 130 is not provided. In this case, information can be written and held by the same operation as described above.

  Next, reading of information will be described. When the transistor 100 is turned on, the floating wiring BL and the capacitor 150 are brought into conduction, and charge is redistributed between the wiring BL and the capacitor 150. As a result, the potential of the wiring BL changes. The amount of change in the potential of the wiring BL varies depending on the potential of one electrode of the capacitor 150 (or the charge accumulated in the capacitor 150).

  For example, when the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, the capacitance component of the wiring BL is CB, and the potential of the wiring BL before the charge is redistributed is VB0, the charge is The potential of the wiring BL after the redistribution is (CB × VB0 + C × V) / (CB + C). Therefore, if the potential of one electrode of the capacitor 150 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the potential of the wiring BL when the potential V1 is held (= ( It can be seen that (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the wiring BL (= (CB × VB0 + C × V0) / (CB + C)) when the potential V0 is held.

  Then, information can be read by comparing the potential of the wiring BL with a predetermined potential.

  The semiconductor device illustrated in FIGS. 37A and 37B can be used as a memory device of a CPU, for example.

  FIG. 38 illustrates an example of a cross-sectional structure of a semiconductor device that can realize the circuit illustrated in FIG. FIG. 38 shows an example in which WBL and RBL are made conductive to reduce the number of wirings. Note that FIG. 38B illustrates a cross section of a plane that passes through the alternate long and short dash line AB illustrated in FIG. 38A and is perpendicular to FIG. 38C illustrates a cross section of a plane that passes through the alternate long and short dash line CD illustrated in FIG. 38A and is perpendicular to FIG.

  The transistor 100 is preferably provided above the transistor 130. By stacking the transistor 100 and the transistor 130, for example, the circuit area can be reduced. As the transistor 100, for example, the transistor described in Embodiment 3 can be used. FIG. 38 illustrates an example in which the transistor 100 illustrated in FIG. 12 is used.

  The transistor 130 includes a first semiconductor material. In addition, the transistor 100 includes a second semiconductor material. Examples of semiconductors that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium, and arsenic, and compound semiconductor materials including silicon, germanium, gallium, arsenic, aluminum, and the like, An organic semiconductor material, an oxide semiconductor material, or the like can be given.

  The first semiconductor material and the second semiconductor material may be the same material, but are preferably different semiconductor materials. Here, the case where single crystal silicon is used as the first semiconductor material and an oxide semiconductor is used as the second semiconductor material is described.

[First transistor]
The transistor 130 is provided over the semiconductor substrate 131, and includes a semiconductor layer 132 formed of part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and a low resistance layer 133a and a low resistance layer 133b that function as a source region or a drain region. Have

  The transistor 130 may be either a p-channel type or an n-channel type, but an appropriate transistor may be used depending on a circuit configuration and a driving method.

  The region in which the channel of the semiconductor layer 132 is formed, a region in the vicinity thereof, the low resistance layer 133a and the low resistance layer 133b which serve as a source region or a drain region, and the like preferably include a semiconductor such as a silicon-based semiconductor. It is preferable to include silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon having distortion in the crystal lattice may be employed. Alternatively, the transistor 130 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The transistor 130 may include a region 176a and a region 176b which are LDD (Lightly Doped Drain) regions.

  The low resistance layer 133a and the low resistance layer 133b include an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron, in addition to the semiconductor material applied to the semiconductor layer 132. Including.

  The gate electrode 135 includes a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity, such as phosphorus, or an element imparting p-type conductivity, such as boron. A conductive material such as can be used.

  Here, instead of the transistor 130, a transistor 190 as illustrated in FIGS. 29A and 29B may be used. FIG. 29B illustrates a cross section of a plane that passes through the alternate long and short dash line E-F illustrated in FIG. 29A and is perpendicular to FIG. In the transistor 190, a semiconductor layer 132 (a part of a semiconductor substrate) where a channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along a side surface and an upper surface thereof. An element isolation layer 181 is provided between the transistors. Such a transistor 190 is also referred to as a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulating film functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI (Silicon on Insulator) substrate may be processed to form a semiconductor layer having a convex shape.

  An insulating film 136, an insulating film 137, and an insulating film 138 are sequentially stacked to cover the transistor 130.

  The insulating film 136 functions as a protective film in activation of an element imparting conductivity added to the low resistance layer 133a and the low resistance layer 133b in the manufacturing process of the semiconductor device. The insulating film 136 is not necessarily provided if not necessary.

  In the case where a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably includes an insulating material containing hydrogen. By performing heat treatment, dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137, whereby the reliability of the transistor 130 can be improved.

  The insulating film 138 functions as a planarization layer that planarizes a step caused by the transistor 130 or the like provided thereunder. The upper surface of the insulating film 138 may be planarized by a CMP method or the like.

  The insulating film 136, the insulating film 137, and the insulating film 138 include a plug 140 that is electrically connected to the low resistance layer 133a, the low resistance layer 133b, and the like, a plug 139 that is electrically connected to the gate electrode 135 of the transistor 130, and the like. It may be embedded.

  A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film 111 is a layer having a function of suppressing diffusion of water and hydrogen from the lower layer to the upper layer. The barrier film 111 preferably has low oxygen permeability. Here, that water and hydrogen are difficult to diffuse indicates that the permeability of water and hydrogen is low as compared with, for example, silicon oxide generally used as an insulating film. Further, the low oxygen permeability means that the oxygen permeability is low as compared with, for example, silicon oxide generally used as an insulating film.

Examples of materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), and (Ba, Sr) TiO ₃ (BST). An insulating film containing a so-called high-k material such as a single layer or a stacked layer can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided to form an oxynitride film. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulating film. In particular, aluminum oxide is more preferable because it has excellent barrier properties against water and hydrogen.

  In addition to hydrogen and water, the above-described materials are materials excellent in oxygen barrier properties. Therefore, oxygen released when the insulating film 114 is heated can be prevented from diffusing below the barrier film 111. As a result, the amount of oxygen released from the insulating film 114 and supplied to the semiconductor layer of the transistor 100 can be increased.

  Here, in the lower layer than the barrier film 111, it is preferable to reduce hydrogen, water, or the like by, for example, heat treatment. The heat treatment condition may be set to 170 ° C. or higher in an inert gas atmosphere or a reduced pressure atmosphere, for example.

  In the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment includes treatment for terminating a dangling bond of silicon (also referred to as dangling bond) with hydrogen (also referred to as hydrogenation treatment). I can also serve.

  A conductive layer 151, a conductive layer 152a, and a conductive layer 152b are provided so as to sandwich the barrier film 111, and the capacitor 150 is formed. The conductive layer 151 is electrically connected to the conductive layer 104a of the transistor 100.

  An insulating film 114 is provided so as to cover the barrier film 111, the conductive layer 152a, the conductive layer 152b, the conductive layer 105, and the like. For the insulating film 114, refer to the description of the insulating film 114 in FIG.

[Second transistor]
A transistor 100 is provided over the insulating film 114. In the example illustrated in FIG. 38, the transistor illustrated in FIG.

  In addition, the transistor 100 illustrated in FIGS. 38A and 38B includes a conductive layer 105 functioning as a second gate electrode. The conductive layer 105 may be formed at the same time as the conductive layers 152 a and 152 b that form part of the capacitor 150. By forming these conductive layers simultaneously, for example, the process can be simplified.

  Further, an insulating film 112, an insulating film 113, and an insulating film 116 are provided so as to cover the transistor 100.

  As with the barrier film 111, the insulating film 112 is preferably made of a material in which water and hydrogen are difficult to diffuse. It is particularly preferable to use a material that does not easily transmit oxygen.

  Note that the insulating film 112 may have a stacked structure of two or more layers. In that case, for example, the insulating film 112 is preferably formed to have a two-layer structure, and a material in which water or hydrogen hardly diffuses is preferably used for the upper layer. In addition, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride may be used for the lower layer. The insulating film provided in the lower layer may have a structure in which oxygen is supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102 as an insulating film from which oxygen is released by heating, similarly to the insulating film 114.

  By covering the semiconductor layer 101 with the insulating film 112, release of oxygen from the semiconductor layer 101 to the upper side of the insulating film 112 can be suppressed. Furthermore, oxygen released from the insulating film 114 and the like can be confined below the insulating film 112, so that the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

  In addition, by providing the insulating film 112, entry of water and hydrogen into the oxide semiconductor from the outside can be suppressed. Therefore, a highly reliable transistor in which variation in electrical characteristics is suppressed can be realized.

  As the insulating film 113, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

  The insulating film 116 that covers the transistor 100 functions as a planarization layer that covers the underlying uneven shape. The insulating film 113 may function as a protective film when the insulating film 116 is formed. The insulating film 113 is not necessarily provided if not necessary. As the insulating film 116, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

  A plug 321, a plug 322, and a plug 123 that are electrically connected to the conductive layer 104 b are embedded in the insulating film 112, the insulating film 113, and the insulating film 116.

  Over the insulating film 116, a wiring 124 and the like electrically connected to the plug 322 are provided.

  As shown in FIG. 38, an insulating film 137 containing a material similar to that of the barrier film 111 may be provided over the insulating film 136 containing hydrogen. With such a structure, water and hydrogen remaining in the insulating film 136 containing hydrogen can be effectively suppressed from diffusing upward.

  Wiring 124, wiring 166, etc., conductive layer 143, conductive layer 151, conductive layer 152a, conductive layer 152b, conductive layer 251 and other conductive layers, plug 123, plug 139, plug 140, plug 164, plug 165, etc. The plug can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, a material such as titanium nitride or titanium may be stacked with another material.

[Example of production method]
Next, an example of a method for manufacturing the semiconductor device in FIG. 38 is described with reference to FIGS.

  First, the semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Further, an SOI substrate may be used as the semiconductor substrate 131. Hereinafter, a case where single crystal silicon is used as the semiconductor substrate 131 will be described.

  Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer may be formed using a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

  In the case where a p-type transistor and an n-type transistor are formed over the same substrate, an n well or a p well may be formed in part of the semiconductor substrate 131. For example, an n-type semiconductor substrate 131 may be doped with an impurity element such as boron that imparts p-type conductivity to form a p-well, and an n-type transistor and a p-type transistor may be formed on the same substrate. Good.

  Subsequently, an insulating film to be the gate insulating film 134 is formed over the semiconductor substrate 131. For example, the surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, a silicon oxide film and a silicon oxynitride film may be stacked by nitriding the surface of the silicon oxide film by performing nitriding after forming silicon oxide by a thermal oxidation method. Alternatively, silicon oxide, silicon oxynitride, tantalum oxide which is a high dielectric constant material (also referred to as a high-k material), hafnium oxide, hafnium oxide silicate, zirconium oxide, aluminum oxide, titanium oxide, or other metal oxide, or oxidation Rare earth oxides such as lanthanum may be used.

  The insulating film includes a sputtering method, a CVD (Chemical Vapor Deposition) method (including a thermal CVD method, a MOCVD (Metal Organic CVD) method, a PECVD (Plasma Enhanced CVD) method, etc.), an MBE (Molecular Beam Epitaxy) method, and the like. You may form by forming into a film by the atomic layer deposition (PLA) method or the PLD (Pulsed Laser Deposition) method.

  Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like, or an alloy material or a compound material containing these metals as a main component. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. Alternatively, a stacked structure of a metal nitride film and the above metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

  The conductive film can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like). In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Subsequently, a resist mask is formed over the conductive film using a lithography method or the like, and unnecessary portions of the conductive film are removed. After that, the gate electrode 135 can be formed by removing the resist mask.

  Here, a method for processing a film to be processed will be described. Various fine processing techniques can be used as the processing method. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Alternatively, a dummy pattern may be formed by photolithography or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the film to be processed may be etched using the remaining sidewall as a resist mask. In order to realize a high aspect ratio, it is preferable to use anisotropic dry etching as etching of the film to be processed. Further, a hard mask made of an inorganic film or a metal film may be used.

  As light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing them can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  Further, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed before forming the resist film to be a resist mask. The organic resin film can be formed by, for example, spin coating so as to cover the level difference of the lower layer and planarize the surface, and variations in the thickness of the resist mask provided on the upper layer of the organic resin film Can be reduced. In particular, when fine processing is performed, a material that functions as an antireflection film for light used for exposure is preferably used as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed or after the resist mask is removed.

  Thereafter, for the description of processing using a resist mask, for example, the processing method described for the gate electrode 135 may be referred to. In this specification, description of resist removal after etching of a film to be processed may be omitted.

  After the formation of the gate electrode 135, a sidewall that covers the side surface of the gate electrode 135 may be formed. The sidewall can be formed by depositing an insulating film thicker than the thickness of the gate electrode 135 and then performing anisotropic etching so that only the side surface portion of the gate electrode 135 remains.

  FIG. 39 shows an example in which the gate insulating film is not etched when the sidewall is formed, but the insulating film which becomes the gate insulating film 134 may also be etched at the same time when the sidewall is formed. In this case, the gate insulating film 134 is formed below the gate electrode 135 and the sidewall.

  Subsequently, an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron is added to a region of the semiconductor substrate 131 where the gate electrode 135 (and sidewall) is not provided. To do. A schematic cross-sectional view at this stage corresponds to FIG.

  Subsequently, after the insulating film 136 is formed, for example, heat treatment for activating the above-described element imparting conductivity is performed. The heat treatment can be performed in an inert gas atmosphere such as a rare gas or a nitrogen gas, or in a reduced pressure atmosphere, for example, at 400 ° C. or higher and lower than the strain point of the substrate.

  For the insulating film 136, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and the insulating film 136 is provided as a stacked layer or a single layer. The insulating film 136 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  At this stage, the transistor 130 is formed. Alternatively, the third transistor 160 may be formed by a method similar to that for forming the transistor 130.

  Subsequently, an insulating film 137 and an insulating film 138 are formed.

  The insulating film 137 may be formed using silicon nitride (SiNOH) containing oxygen and hydrogen in addition to a material that can be used for the insulating film 136. The insulating film 138 has a step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide, in addition to materials that can be used for the insulating film 136. It is preferable to use good silicon oxide.

  The insulating film 137 and the insulating film 138 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Subsequently, the upper surface of the insulating film 138 is planarized using a CMP method or the like. Further, a planarization film may be used as the insulating film 138. In that case, the planarization is not necessarily performed by the CMP method or the like. For example, an atmospheric pressure CVD method or a coating method can be used to form the planarizing film. Examples of the film that can be formed using the atmospheric pressure CVD method include BPSG (Boron Phosphorus Silicate Glass). Moreover, as a film | membrane which can be formed using the apply | coating method, HSQ (hydrogen silsesquioxane) etc. are mentioned, for example. After that, heat treatment for terminating dangling bonds in the semiconductor layer 132 with hydrogen desorbed from the insulating film 137 may be performed.

  Subsequently, openings that reach the low resistance layer 133a, the low resistance layer 133b, the gate electrode 135, and the like are formed in the insulating film 136, the insulating film 137, and the insulating film 138 (see FIG. 39B). After that, a conductive film is formed so as to fill the opening (see FIG. 39C). After that, the conductive film is planarized so that the upper surface of the insulating film 138 is exposed, whereby the plug 139, the plug 140, and the like are formed (see FIG. 39D). The conductive film can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method.

  Subsequently, an insulating film 215 is formed over the insulating film 138. The insulating film 215 can be formed using a material and a method similar to those of the insulating film 136 and the like. Heat treatment may be performed after the insulating film 215 is formed.

  The third heat treatment can be performed under the conditions exemplified in the description of the stacked structure. For example, the conditions described in the first heat treatment can be used.

  Subsequently, an opening is formed in the insulating film 215. After that, a conductive film is formed so as to fill the opening, and a planarization process is performed on the conductive film so that an upper surface of the insulating film 215 is exposed, so that the conductive layer 251, the conductive layer 143, the conductive layer 151, and the like are formed. (See FIG. 39E). In the case where a conductive film is formed in the opening, for example, a material such as titanium nitride or titanium may be formed in the opening, and then another conductive material may be stacked. For example, the adhesion to the opening can be improved by using titanium nitride or titanium for the lower layer of the laminated film.

  Subsequently, a barrier film 111 is formed to form an opening (see FIG. 40A). The barrier film 111 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Subsequently, a conductive film to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b is formed. After that, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see FIG. 40B).

  Next, an insulating film 114 is formed. The insulating film 114 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  In order to make the insulating film 114 contain excessive oxygen, for example, the insulating film 114 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after film formation to form a region containing excess oxygen, or both means may be combined.

  For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 which has been formed, so that a region containing excess oxygen is formed. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Further, after the insulating film 114 is molded, a planarization process using a CMP method or the like may be performed in order to improve the flatness of the upper surface.

  Next, a semiconductor film to be the insulator layer 101a and a semiconductor film to be the semiconductor layer 101b are formed in this order (see FIG. 40C). The semiconductor film is preferably formed continuously without being exposed to the air. The semiconductor to be the insulator layer 101a and the semiconductor to be the semiconductor layer 101b may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Note that in the case where an In—Ga—Zn oxide layer is formed by a MOCVD method as a semiconductor to be the insulator layer 101a and a semiconductor to be the semiconductor layer 101b, trimethylindium, trimethylgallium, dimethylzinc, or the like is used as a source gas. That's fine. The combination of the source gases is not limited, and triethylindium or the like may be used instead of trimethylindium. Further, triethylgallium or the like may be used instead of trimethylgallium. Further, diethyl zinc or the like may be used instead of dimethyl zinc.

  Here, oxygen may be introduced into the insulator layer 101a after the insulator layer 101a is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  Heat treatment may be performed after the insulator layer 101a and the semiconductor layer 101b are formed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the semiconductor film is formed, or may be performed after the semiconductor film is processed to form the island-shaped insulator layers 101a and 101b. By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film, so that oxygen vacancies in the semiconductor film can be reduced.

  After that, a stacked structure of the island-shaped insulator layer 101a and the island-shaped semiconductor layer 101b is formed using a resist mask (see FIG. 40D). Note that when the semiconductor film is etched, part of the insulating film 114 is etched, and the insulating film 114 in a region not covered with the insulator layer 101a and the semiconductor layer 101b may be thinned. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 is not lost by the etching.

  Note that since the resist may disappear during the etching process depending on the etching conditions of the semiconductor film, a so-called hard mask made of a material having high etching resistance, for example, an inorganic film or a metal film may be used. Here, an example in which a conductive film is used as the hard mask 281 is described. FIG. 41A illustrates an example in which a semiconductor film is processed using the hard mask 281 to form the insulator layer 101a and the semiconductor layer 101b. Here, when a material that can be used for the conductive layer 104a and the conductive layer 104b is used for the hard mask 281, the hard mask 281 can be processed to form the conductive layer 104a and the conductive layer 104b. By using such a method, for example, the transistor 100 illustrated in FIG. 30 can be manufactured.

  After the structure shown in FIG. 40D is formed, an opening reaching the conductive layer 151, the conductive layer 251, and the like is provided in the insulating film 114 (see FIG. 41B). After that, a conductive film to be the conductive layer 104a, the conductive layer 104b, or the like is formed so as to fill the opening provided in the insulating film 114. The conductive film to be the conductive layer 104a, the conductive layer 104b, or the like is formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method. can do. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Next, unnecessary portions of the conductive film to be the conductive layers 104a, 104b, and the like are removed by etching using a resist mask, so that the conductive layers 104a and 104b and the like are formed (see FIG. 41C). . Here, when the conductive film is etched, part of the upper portion of the semiconductor layer 101b or the insulating film 114 is etched, and a portion that does not overlap with the conductive layer 104a or the conductive layer 104b may be thinned. Accordingly, it is preferable that the thickness of the semiconductor film or the like to be the semiconductor layer 101b is formed thick in advance in consideration of the etching depth.

  Next, the insulator layer 101c and the gate insulating film 102 are formed. After that, etching is performed using a resist mask (see FIG. 42A). Next, a conductive film to be the gate electrode 103 is formed, and the conductive film is processed using a resist mask, so that the gate electrode 103 is formed (see FIG. 42B).

  Note that the insulating layer 101a may be referred to for the deposition method of the insulating layer 101c, for example.

  Alternatively, oxygen may be introduced into the insulator layer 101c after the insulator layer 101c is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating layer 101c after deposition to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, for example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, or the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

  At this stage, the transistor 100 is formed.

  Next, the insulating film 112 is formed. The insulating film 112 can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Heat treatment may be performed after the insulating film 112 is formed. By the heat treatment, oxygen can be supplied from the insulating film 114 or the like to the semiconductor layer 101, so that oxygen vacancies in the semiconductor layer 101 can be reduced.

  The insulating film 112 may have a stacked structure of two or more layers.

  Subsequently, an insulating film 113 is formed. The insulating film 113 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, a CVD method, preferably a plasma CVD method, is preferable because coverage can be improved. In order to reduce plasma damage, thermal CVD, MOCVD or ALD is preferred.

  Subsequently, an opening reaching the conductive layer 104a and the like is provided in the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulator layer 101c. Next, after forming a conductive film so as to fill the opening, unnecessary portions are removed using a resist mask, and a plug 321 and a plug 322 are formed.

  Subsequently, an insulating film 116 is formed. The insulating film 116 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In the case where an organic insulating material such as an organic resin is used for the insulating film 116, a coating method such as a spin coating method may be used. In addition, after the insulating film 116 is formed, planarization treatment is preferably performed on the upper surface thereof. Further, as the insulating film 116, a material shown in the insulating film 138 or a formation method thereof may be used.

  Subsequently, a plug 123 reaching the plug 322 is formed in the insulating film 116 by a method similar to the above.

  Subsequently, a conductive film is formed over the insulating film 116. After that, unnecessary portions of the conductive film are removed by etching using a resist mask in the same manner as described above, whereby the wiring 124 and the like can be formed.

  Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, an example of a circuit using the transistor of one embodiment of the present invention will be described with reference to drawings.

[Circuit configuration example]
In the structure shown in the semiconductor device to which Embodiment 1 is applied, various circuits can be formed by changing connection structures of transistors, wirings, and electrodes. An example of a circuit configuration that can be realized by using the semiconductor device of one embodiment of the present invention will be described below.

[CMOS circuit]
The circuit diagram shown in FIG. 37C illustrates a structure of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and gates thereof are connected. Note that in the drawing, a transistor to which the second semiconductor material is applied is denoted by a symbol “OS”. Here, the CMOS circuit described in this embodiment can be used as a basic element of a logic circuit such as a NAND circuit, a NOR circuit, an encoder, a decoder, a MUX (multiplemplifier), or a DEMUX (demultiplexer).

[Analog switch]
A circuit diagram illustrated in FIG. 37D illustrates a structure in which the sources and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, it can function as a so-called analog switch.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 8)
In this embodiment, a display module including the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  A display module 8000 shown in FIG. 27 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, a battery, between an upper cover 8001 and a lower cover 8002. 8011.

  The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

  The shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.

  As the touch panel 8004, a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function. In addition, an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.

  The backlight 8007 has a light source 8008. Note that although FIG. 27 illustrates the configuration in which the light source 8008 is provided over the backlight 8007, the present invention is not limited to this. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

  The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006. The frame 8009 may have a function as a heat sink.

  The printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used. The battery 8011 can be omitted when a commercial power source is used.

  The display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.

The display module 8000 described in this embodiment may have flexibility. By having flexibility, it can be bonded on a curved surface or an irregular shape, and various uses can be realized.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 9)
In this embodiment, an RF tag including the transistor or the memory device described in the above embodiment will be described with reference to FIGS.

  The RF tag in this embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. Because of these characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading individual information about the article. Note that extremely high reliability is required for use in these applications.

  The configuration of the RF tag will be described with reference to FIG. FIG. 28 is a block diagram illustrating a configuration example of an RF tag.

  As shown in FIG. 28, the RF tag 800 includes an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator or a reader / writer). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. Note that a material that can sufficiently suppress a reverse current, such as an oxide semiconductor, may be used for the transistor including the rectifying action included in the demodulation circuit 807. Thereby, the fall of the rectification effect | action resulting from a reverse current can be suppressed, and it can prevent that the output of a demodulation circuit is saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. Note that there are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RF tag 800 described in this embodiment can be used for any of the methods.

  Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double voltage rectification, and the signal rectified by a capacitive element provided in the subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

  The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

  The demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804.

  A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.

  Note that the above-described circuits can be appropriately disposed as necessary.

  Here, the memory circuit described in the above embodiment can be used for the memory circuit 810. Since the memory circuit of one embodiment of the present invention can retain information even when the power is turned off, the memory circuit can be preferably used for an RF tag. Further, the memory circuit of one embodiment of the present invention does not cause a difference in maximum communication distance between data reading and writing because power (voltage) necessary for data writing is significantly smaller than that of a conventional nonvolatile memory. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power during data writing.

  The memory circuit of one embodiment of the present invention can also be applied to the ROM 811 because it can be used as a nonvolatile memory. In that case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command. By shipping the product after the producer writes the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped, rather than assigning a unique number to all the produced RF tags, The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 10)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book, a video camera, a camera such as a digital still camera, or a goggle type Display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, etc. . Specific examples of these electronic devices are shown in FIGS.

  FIG. 57A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 57A includes two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

  FIG. 57B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device to which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

  FIG. 57C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

  FIG. 57D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

  FIG. 57E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. The video on the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

  FIG. 57F illustrates an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953, lights 954, and the like.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 11)
In this embodiment, an example of using an RF tag according to one embodiment of the present invention will be described with reference to FIGS. Applications of RF tags are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 56A), packaging containers (wrapping paper, 56 (C)), recording medium (DVD, video tape, etc., see FIG. 56 (B)), vehicles (bicycles, etc., see FIG. 56 (D)), personal items (bags, glasses, etc.) , Articles such as foods, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), Alternatively, it can be used by being provided on a tag attached to each article (see FIGS. 56E and 56F).

  The RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to the surface or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article. In addition, by providing the RF tag 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. Can be planned. Even in the case of vehicles, the security against theft or the like can be improved by attaching the RF tag according to one embodiment of the present invention.

  As described above, by using the RF tag according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced, so the maximum communication distance can be increased. Is possible. In addition, since the information can be held for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing and reading is low.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

  Note that a drawing (or a part thereof) described in one embodiment may be another part of the drawing, another drawing (may be a part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment.

  In addition, about the content which is not prescribed | regulated in the drawing and text in a specification, the one aspect | mode of the invention which prescribed | regulated removing the content can be comprised. Or, when a numerical value range indicated by an upper limit value and a lower limit value is described for a certain value, the range is unified by arbitrarily narrowing the range or by removing one point in the range. One aspect of the invention excluding a part can be defined. Thus, for example, it can be defined that the prior art does not fall within the technical scope of one embodiment of the present invention.

  As a specific example, a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it can be specified as an invention that the circuit does not include the sixth transistor. Alternatively, it can be specified that the circuit does not include a capacitor. Furthermore, the invention can be configured by specifying that the circuit does not have the sixth transistor having a specific connection structure. Alternatively, the invention can be configured by specifying that the circuit does not include a capacitor having a specific connection structure. For example, the invention can be defined as having no sixth transistor whose gate is connected to the gate of the third transistor. Alternatively, for example, it can be specified that the first electrode does not include a capacitor connected to the gate of the third transistor.

  As another specific example, it is assumed that the property of a certain substance is described as, for example, “a certain film is an insulating film”. In that case, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an organic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an inorganic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a conductive film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a semiconductor film.

  As another specific example, it is assumed that a certain laminated structure is described as “a film is provided between the A film and the B film”, for example. In that case, for example, the invention can be defined as excluding the case where the film is a laminated film of four or more layers. Alternatively, for example, the invention can be defined as excluding the case where a conductive film is provided between the A film and the film.

  Note that in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the present invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitance elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, operating methods, manufacturing methods It is possible to extract one part of a drawing or a sentence on which one or more of the above are described and constitute one embodiment of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, M (M is an integer and M <N) layers are extracted from a cross-sectional view including N layers (N is an integer) to form one embodiment of the invention. It is possible to do. As another example, M elements (M is an integer and M <N) are extracted from a flowchart including N elements (N is an integer) to form one aspect of the invention. It is possible to do. As another example, a part of the elements is arbitrarily extracted from the sentence “A has B, C, D, E, or F”. "A has E and F", "A has C, E and F", or "A has B, C, D and E" It is possible to constitute one aspect of the invention.

  Note that in this specification and the like, when at least one specific example is described in a drawing or text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. To be understood. Therefore, in the case where at least one specific example is described in a drawing or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. One embodiment of the invention is clear.

  Note that in this specification and the like, at least the contents shown in the drawings (may be part of the drawings) are disclosed as one embodiment of the invention, and can constitute one embodiment of the invention It is. Therefore, if a certain content is described in the figure, even if it is not described using sentences, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention. Is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. And it can be said that one aspect of the invention is clear.

  In this example, evaluation results of an oxide semiconductor film which is one embodiment of the present invention will be described.

[Production method]
A silicon wafer was thermally oxidized to form a 100 nm silicon oxide film. After that, an In—Ga—Zn oxide with a thickness of 100 nm was formed as the oxide semiconductor film by a sputtering method. As conditions for the sputtering method, a polycrystalline In—Ga—Zn oxide of In: Ga: Zn = 1: 1: 1 (atomic ratio) was used as a target, a power source was 0.5 kW (DC), The distance between the targets was 60 mm. Further, argon and oxygen were used as film forming gases, and the respective flow rates were 30 sccm for argon and 15 sccm for oxygen. The pressure was 0.4 Pa. The substrate temperature was 170 ° C. for sample E1-1 and 300 ° C. for sample F1-1.

  Next, heat treatment was performed. The heat treatment was performed at 450 ° C. for 1 hour in a nitrogen atmosphere and then in the same treatment chamber for 1 hour at 450 ° C. in an oxygen atmosphere.

[XRD evaluation]
Next, the results of evaluation using an XRD apparatus will be described. The XRD apparatus evaluated each sample using multi-functional thin film material evaluation X-ray diffractometer D8 DISCOVER Hybrid (manufactured by Bruker AXS). FIG. 43 shows the result of analysis by the Out-Of-Plane method. FIG. 43A shows the result of the sample E1-1, and FIG. 43B shows the result of the sample F1-1. In any sample, a peak was observed in the vicinity of 2θ = 31 °. The conditions for film formation at 170 ° C. showed a broad peak, and the conditions for film formation at 300 ° C. tended to be sharper. This peak is attributed to the (009) plane of the InGaZnO ₄ crystal, which suggests that the crystal of the oxide semiconductor film having c-axis orientation is increased by increasing the deposition temperature.

[Film density evaluation]
Next, the film density was measured. For evaluation of the film density, XRR (X-ray reflectometry) was used. The obtained film densities were 6.18 [g / cm ³ ] for sample E1-1 and 6.36 [g / cm ³ ] for sample F1-1. A dense and good film was obtained under any conditions.

[Nanobeam electron diffraction]
Next, analysis by nanobeam electron diffraction was performed on sample E1-1 and sample F1-1. For acquisition of electron diffraction, “HF-2000” manufactured by Hitachi High-Technologies was used. The acceleration voltage was 200 kV.

  A transmission electron diffraction pattern was obtained while scanning by moving the sample stage little by little with respect to the upper surface of each sample having an oxide semiconductor film. A nanobeam electron beam having a probe diameter of 1 nm was used as the electron beam. Moreover, the same measurement was performed at three locations for each sample. That is, a total of three scans of scan1 to scan3 were performed on each sample.

  A diffraction pattern was observed while scanning at a speed of 5 nm / second, and a moving image was acquired. Next, the diffraction pattern observed in the obtained moving image was converted into a still image every 0.5 seconds. The converted still image was analyzed and classified into three patterns: an nc-OS film pattern, a CAAC-OS film pattern, and a spinel crystal structure pattern. Table 3 shows the number of images classified into each pattern in Scan1 to Scan3 for Sample E1-1 and Sample F1-1. Also, the results of scan1 of the electron diffraction pattern of sample E1-1 are shown in FIGS. 44 to 48, and the results of scan1 of sample F1-1 are shown in FIGS. In addition, among the electron diffraction results shown in FIGS. 44 to 48, the pattern determined to be a CAAC-OS film pattern is surrounded by a broken line and shown. In addition, among the electron diffraction results illustrated in FIGS. 49 to 53, a pattern determined to be the nc-OS film is surrounded by a broken line and illustrated.

  In sample E1-1, the nc ratio showed a high value of 90% or more. It was found that the nc ratio was further increased by lowering the film formation temperature. In all samples, the sum of the nc ratio and the CAAC ratio was 100%.

  In this example, the film density evaluation result of In—Ga—Zn oxide and the result of TDS (Thermal Desorption Spectroscopy) analysis are shown.

An In—Ga—Zn oxide film was formed by a sputtering method over a quartz substrate that had been cleaned in advance. As the target, a polycrystalline In—Ga—Zn oxide with In: Ga: Zn = 1: 1: 1 (atomic ratio) was used. The film forming conditions were such that the power supply was 100 W, argon and oxygen were used as the film forming gas, and the flow rate of oxygen gas was adjusted to 2% with respect to the total flow rate of argon gas and oxygen gas. The pressure was 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. Table 4 shows the film formation conditions and the film density. For sample B and sample D, an In—Ga—Zn oxide film was formed by a sputtering method, and then heat treatment was performed at 450 ° C. XRR was used for evaluation of the film density. As shown in Table 4, in sample C, the density was as high as 6 [g / cm ³ ] or more.

Next, TDS analysis was performed on sample A to sample D. 54A and 54B show the degassing release amount with a molecular weight of 18. FIG. The degassing with a molecular weight of 18 is considered to originate from H ₂ O. In sample A, the released amount was large, and in sample B which was heat-treated, the released amount decreased. In sample C having a high film density, it is considered that the amount of released gas is small without performing heat treatment, and the amount of water contained in the film is small.

Next, for sample A to sample D, the change in crystal size (crystal size) due to electron beam irradiation was evaluated. The crystal size was calculated by observing the cross section using TEM. FIG. 55 shows the results of performing electron beam irradiation using TEM and evaluating the relationship between the cumulative dose and the crystal size. In sample A, there was a tendency for crystals to become larger each time the electron beam was irradiated. Here, the crystal size before the electron beam irradiation may be set such that the cumulative irradiation amount is 0 [e ⁻ / nm ² ] in the approximate line shown in FIG. 55, for example. In sample B where the heat treatment was performed, the change in crystal size was small. In sample C and sample D having a high film density, no significant change was observed in the crystal size in the range of the cumulative electron beam irradiation dose up to 4.2 × 10 ⁸ [e ⁻ / nm ² ].

In this example, the stability of the oxide semiconductor film was evaluated. A method for manufacturing Sample 1, Sample 2, and Sample 3 is described below.

First, an In—Ga—Zn oxide film with a thickness of 100 nm is formed over a quartz substrate by an RF sputtering method. As the target, a polycrystalline In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]) was used. The deposition gas was oxygen gas at 2 sccm and argon gas at 98 sccm. The power was 100 W. The substrate temperature during film formation was room temperature. Here, Sample 1 has a deposition pressure of 0.4 Pa. Sample 2 had a film forming pressure of 1.0 Pa.

In Sample 3, a 100-nm-thick In—Ga—Zn oxide film is formed over a quartz substrate by a DC sputtering method. As a target, an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]) was used. The deposition gas was 10 sccm for oxygen gas and 20 sccm for argon gas. The power was 200W. The substrate temperature during film formation was 300 ° C. The film forming pressure was 0.4 Pa.

Next, heat treatment was performed for 1 hour in an atmosphere containing oxygen and nitrogen. The heat treatment temperature was five conditions of 250 ° C., 300 ° C., 350 ° C., 400 ° C., and 450 ° C. Thereafter, the film densities of Sample 1, Sample 2 and Sample 3 were measured including the conditions where heat treatment was not performed. For measurement of the film density, XRR using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS was used. The result of Sample 1 is shown in FIG. 58 (A), the result of Sample 2 is shown in FIG. 58 (B), and the result of Sample 3 is shown in FIG. 58 (C). The horizontal axis is the temperature of the heat treatment. The film density of Sample 1 was 5.9 g / cm ³ to 6.1 g / cm ³ . The film density of Sample 2 was in the range of 5.6 g / cm ³ to 5.8 g / cm ³ . The film density of Sample 3 was in the range of 6.2 g / cm ³ to 6.4 g / cm ³ .

Next, Sample 1, Sample 2, and Sample 3 were etched using an aqueous solution in which phosphoric acid was diluted 100 times with pure water. And the etching rate was measured by measuring the thickness before and behind etching. The result of Sample 1 is shown in FIG. 59 (A), the result of Sample 2 is shown in FIG. 59 (B), and the result of Sample 3 is shown in FIG. 59 (C). It was found that the etching rate of Sample 1 and Sample 2 was lower as the temperature of the heat treatment was higher. Sample 3 was found to have a small difference due to the temperature of the heat treatment. Moreover, it turned out that the etching rate of the sample 1 which is not heat-processed becomes lower than the sample 2 which heat-processed. Moreover, it turned out that the etching rate of the sample 3 which is not heat-processed becomes lower than the sample 1 which heat-processed.

Next, Sample 1, Sample 2 and Sample 3 were subjected to TDS analysis, and the amount of degassed (water) released with a mass to charge ratio of 18 was measured. For the TDS analysis, a thermal desorption analyzer TDS-1200 manufactured by Electronic Science Co., Ltd. was used. The result of Sample 1 is shown in FIG. 60 (A), the result of Sample 2 is shown in FIG. 60 (B), and the result of Sample 3 is shown in FIG. 60 (C). It was found that the amount of degassing with a mass-to-charge ratio of 18 decreased as Sample 1, Sample 2, and Sample 3 were heated. In addition, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in Sample 1 that was not heat-treated than Sample 2 that was heat-treated. Further, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in the sample 3 not subjected to the heat treatment than in the sample 1 subjected to the heat treatment.

Next, the hydrogen concentration of Sample 1 and Sample 2 was measured. The hydrogen concentration was measured by SIMS. For SIMS, IMS 7fR manufactured by CAMECA was used. The results of Sample 1 are shown in FIGS. 61 (A) and 68 (A), and the results of Sample 2 are shown in FIGS. 61 (B) and 68 (B). Here, in FIGS. 68A and 68B, the horizontal axis indicates the depth from the film surface, and the vertical axis indicates the hydrogen concentration. FIGS. 61A and 61B show average values of hydrogen concentration from a depth of 10 nm to 60 nm. In FIGS. 68A and 68B, the quartz substrate was measured without the In—Ga—Zn oxide film remaining after the region where the hydrogen concentration suddenly changed near a depth of 80 nm. There is a possibility. Further, in the region of less than 10 nm, there is a possibility of being affected by the surface state. Therefore, the hydrogen concentration of the In—Ga—Zn oxide film is preferably expressed by, for example, an average value from a depth of 10 nm to 60 nm. Sample 1 and Sample 2 were found to have a lower hydrogen concentration as the temperature of the heat treatment was higher. Moreover, it turned out that the hydrogen concentration of the sample 1 which is not heat-processed becomes lower than the sample 2 which heat-processed.

Next, changes in crystal size due to heat treatment of Sample 1, Sample 2 and Sample 3 were measured by TEM. The crystal size is shown as an average value from 20 points to 45 points. As the TEM, Hitachi transmission electron microscope H-9000NAR was used. FIG. 62 (A) shows the result of Sample 1, FIG. 62 (B) shows the result of Sample 2, and FIG. 62 (C) shows the result of Sample 3. Sample 1 was found to have a crystal size of about 1.4 nm regardless of the temperature of the heat treatment. Sample 2 had a crystal size of about 1.2 nm when heat treatment was not performed (see FIG. 67), but grew to about 1.3 nm by heat treatment at 250 ° C., and further heated at 300 ° C. It grew to about 1.6 nm by the process. Further, no change in crystal size was observed in the range of 300 ° C to 450 ° C. In sample 3, the crystal size was 1.5 to 1.6 nm regardless of the temperature of the heat treatment.

Next, changes in crystal size of sample 1, sample 2 and sample 3 due to electron beam irradiation were measured by TEM. The result of Sample 1 is shown in FIG. 63 (A), the result of Sample 2 is shown in FIG. 63 (B), and the result of Sample 3 is shown in FIG. 63 (C). Samples 1 and 3 showed almost no change in crystal size regardless of the temperature of the heat treatment and also by electron beam irradiation. Sample 2 showed an increase in crystal size due to electron beam irradiation. Moreover, this tendency was more remarkable as the temperature of the heat treatment was lower.

From the change in crystal size due to heat treatment and the change in crystal size due to electron beam irradiation, it can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When the sample 1, the sample 2, and the sample 3 are collated with the above-described structure classification, the sample 1 is an nc-OS film, the sample 2 is an a-like OS film, and the sample 3 is a CAAC-OS.

Thus, the nc-OS film has a higher film density, a lower etching rate, less degassing of water, and a lower hydrogen concentration than the a-like OS film. In addition, the difference cannot be filled by heat treatment after film formation. In other words, it is important to use an oxide semiconductor film which is an nc-OS film for the transistor when forming the transistor.

In this example, the localized level of the nc-OS film was evaluated. The localization level was evaluated by CPM (Constant photocurrent method) measurement.

For the CPM measurement, a gate electrode (tungsten) on a glass substrate, an nc-OS film on the gate electrode, a gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film, and nc-OS A pair of electrodes in contact with the film (a stacked body formed in the order of tungsten, aluminum, and titanium) and an insulator on the nc-OS film and the pair of electrodes (a stacked body formed in the order of silicon oxynitride and silicon nitride) Were prepared. Note that the nc-OS film was formed at a thickness of 35 nm by an AC sputtering method. As a target, an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1.2 [atomic ratio]) was used. The deposition gas was 10% by volume of oxygen gas and 90% by volume of argon gas. The power was 2.5 kW. The substrate temperature during film formation was room temperature. The film forming pressure was 0.6 Pa.

Next, heat treatment was performed on the manufactured sample. The heat treatment was performed for 1 hour in a nitrogen atmosphere, and then for 1 hour in an atmosphere containing oxygen and nitrogen.

In the CPM measurement, the amount of light applied to the sample surface between the terminals is adjusted so that the photocurrent value is constant while a voltage is applied between a pair of electrodes provided in contact with the nc-OS film. The absorption coefficient is derived. Here, the absorption coefficient was derived at each wavelength. In CPM measurement, the absorption coefficient in energy (converted from wavelength) corresponding to the localized level density increases. By multiplying the increase in the absorption coefficient by a constant, the local level density of the sample can be derived.

Further, by removing light absorption (Earback tail) due to the band tail from the curve of the light absorption spectrum, the absorption coefficient α due to the localized level can be calculated from the following equation.

α = ∫ [(α (E) −α _u ) / E] dE

Here, E represents energy, α (E) represents an absorption coefficient at each energy, and α _u represents an absorption coefficient due to the Arbach tail.

The tilt of the back tail is called the back energy. It can be said that the lower the Arbach energy, the fewer the defects and the higher the orderly semiconductor film having the steep slope of the level tail at the band edge of the valence band.

FIG. 64 shows a result of fitting an absorption coefficient (dotted line) measured by a spectrophotometer and an absorption coefficient (solid line) measured by CPM in an energy range equal to or larger than the energy gap of the oxide semiconductor film. 64A shows the result of the sample heat-treated at 300 ° C. after film formation, FIG. 64B shows the result of the sample heat-treated at 400 ° C. after film formation, and FIG. 64C shows the result of film formation. The result of the sample heat-processed at 450 degreeC later is each shown. The Arbach energy obtained from the absorption coefficient measured by CPM was 72.65 meV, 69.45 meV and 70.32 meV, respectively.

In FIG. 64, the background (thin dotted line) was subtracted from the absorption coefficient derived by CPM measurement, and the integrated value of the absorption coefficient was derived. The results are shown in FIG. The absorption coefficients due to the localized levels were 6.27 × 10 ⁻¹ cm ⁻¹ , 4.19 × 10 ⁻¹ cm ⁻¹ and 2.29 × 10 ⁻¹ cm ⁻¹ , respectively. FIG. 66 shows the relationship between the heat treatment temperature and the absorption coefficient. FIG. 66 shows that the higher the heat treatment temperature is, the smaller the absorption coefficient is, so that the localized level density is also reduced.

11 region 12 region 13 region 14 region 15 region 16 region 21 perpendicular line 22 perpendicular line 23 perpendicular line 50 substrate 51 insulating film 100 transistor 101 semiconductor layer 101a insulating layer 101b semiconductor layer 101c insulating layer 102 gate insulating film 103 gate electrode 104a conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 116 Insulating film 123 Plug 124 Wiring 130 Transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating film 137 Insulating film 138 Insulating film 139 Plug 140 Plug 143 Conductive layer 150 Capacitance element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 Transistor 164 Plug 165 Plug 166 Wiring 171a Low resistance Layer 171b low resistance layer 176a region 176b region 181 element isolation layer 190 transistor 191 transistor 201 semiconductor layer 201a semiconductor layer 201b semiconductor layer 202 gate insulating film 202a gate insulating film 202b gate insulating film 203a gate electrode 203b electrode 204a conductive layer 204b conductive layer 214 Insulating film 215 Insulating film 216 Insulating film 218 Insulating film 251 Conductive layer 281 Hard mask 321 Plug 322 Plug 324 Region 501 Pixel circuit 502 Pixel unit 504 Driver circuit unit 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal unit 550 Transistor 552 Transistor 554 Transistor 560 Capacitance element 562 Capacitance element 570 Liquid crystal element 572 Light emitting element 610 Electron gun chamber 612 Optical system 614 Sample chamber 616 Light System 618 camera 620 viewing chamber 622 film chamber 624 e-632 fluorescent plate 700 display device 701 substrate 702 a pixel portion 704 source driver circuit portion 705 substrate 706 gate driver circuit unit 708 FPC terminal portion 710 signal line 711 wiring portion 712 sealing material 716 FPC
730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light shielding film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulating film 766 Insulating film 768 Insulating film 770 Planarized insulating film 772 Conductive layer 774 Conductive layer 775 Liquid crystal element 776 Liquid crystal layer 778 Structure 780 Anisotropic conductive layer 782 Light emitting element 784 Conductive layer 786 EL layer 788 Conductive layer 790 Capacitance element 790a Capacitance element 790b Capacitance element 800 RF tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM
901 Case 902 Case 903 Display unit 904 Display unit 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Case 913 Display unit 914 Display unit 915 Connection unit 916 Operation key 921 Case 922 Display unit 923 Keyboard 924 Pointing device 931 Enclosure 932 Refrigeration room door 933 Freezer compartment door 941 Enclosure 942 Enclosure 943 Display unit 944 Operation key 945 Lens 946 Connection unit 951 Car body 952 Wheel 953 Dashboard 954 Light 2100 Transistor 2200 Transistor 4000 RF tag 5100 Pellet 5100a Pellet 5100b Pellet 5101 Ion 5120 Substrate 5130 Target 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Back light 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (19)

An oxide semiconductor film containing indium, element M, and zinc,
The element M is an element selected from at least one of aluminum, gallium, yttrium, or tin,
The ratio of the number of atoms of the indium, the element M and the zinc is the indium: the element M
: Zinc = x: y: z is satisfied,
The x, y, and z are in an equilibrium diagram with the three elements of the indium, the element M, and the zinc as vertices,
The first coordinates (x: y: z = 8: 14: 7);
A second coordinate (x: y: z = 2: 4: 3);
Third coordinates (x: y: z = 2: 5: 7);
A fourth coordinate (x: y: z = 51: 149: 300);
The fifth coordinate (x: y: z = 46: 288: 833);
Sixth coordinates (x: y: z = 0: 2: 11),
The seventh coordinate (x: y: z = 0: 0: 1);
The eighth coordinate (x: y: z = 1: 0: 0);
Having a ratio of the number of atoms in a range connecting the first coordinates with a line segment in order;
The range includes the first coordinate to the sixth coordinate, does not include the seventh coordinate and the eighth coordinate,
Using an electron beam with a half width of the probe diameter of 1 nm,
A plurality of electron diffraction patterns were observed by irradiating the electron beam while moving the position of the oxide semiconductor film and the position of the electron beam relative to the formation surface of the oxide semiconductor film. In case
The plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at different locations,
Of the 50 or more electron diffraction patterns, the sum of the ratio having the first electron diffraction pattern and the ratio having the second electron diffraction pattern is 100%,
The first electron diffraction pattern has observation points that do not have symmetry, or a plurality of observation points arranged so as to draw a circle,
The oxide semiconductor film, wherein the second electron diffraction pattern has an observation point located at a vertex of a hexagon. Using an electron beam with a half width of the probe diameter of 1 nm,
A plurality of electron diffraction patterns were observed by irradiating the electron beam while moving the position of the oxide semiconductor film and the position of the electron beam relative to the formation surface of the oxide semiconductor film. In case
The plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at different locations,
Of the 50 or more electron diffraction patterns, the sum of the ratio having the first electron diffraction pattern and the ratio having the second electron diffraction pattern is 100%,
The proportion having the first electron diffraction pattern is 50% or more,
The first electron diffraction pattern has observation points that do not have symmetry, or a plurality of observation points arranged so as to draw a circle,
The oxide semiconductor film, wherein the second electron diffraction pattern has an observation point located at a vertex of a hexagon. In claim 2,
The oxide semiconductor film has indium, an element M, and zinc,
The element M is an element selected from at least one of aluminum, gallium, yttrium, or tin,
The ratio of the number of atoms of the indium, the element M and the zinc satisfies indium: element M: zinc = x: y: z,
The x, y, and z are in an equilibrium diagram with the three elements of the indium, the element M, and the zinc as vertices,
The first coordinates (x: y: z = 8: 14: 7);
A second coordinate (x: y: z = 2: 4: 3);
Third coordinates (x: y: z = 2: 5: 7);
A fourth coordinate (x: y: z = 51: 149: 300);
The fifth coordinate (x: y: z = 46: 288: 833);
Sixth coordinates (x: y: z = 0: 2: 11),
The seventh coordinate (x: y: z = 0: 0: 1);
The eighth coordinate (x: y: z = 1: 0: 0);
Having a ratio of the number of atoms in a range in which the first coordinates are connected in order by line segments;
The range includes the first coordinate to the sixth coordinate, and does not include the seventh coordinate and the eighth coordinate. An oxide semiconductor film containing indium, element M, and zinc,
The oxide semiconductor film has a plurality of crystal parts arranged randomly,
The average diameter of the plurality of crystal parts in the longitudinal direction is 1 nm or more and 3 nm or less. An oxide semiconductor film containing indium, element M, and zinc,
The element M is an element selected from at least one of aluminum, gallium, yttrium, or tin.
The ratio of the number of atoms of the indium, the element M and the zinc satisfies indium: element M: zinc = x: y: z,
The x, y, and z are in an equilibrium diagram with the three elements of the indium, the element M, and the zinc as vertices,
The first coordinates (x: y: z = 8: 14: 7);
A second coordinate (x: y: z = 2: 4: 3);
Third coordinates (x: y: z = 2: 5: 7);
A fourth coordinate (x: y: z = 51: 149: 300);
The fifth coordinate (x: y: z = 46: 288: 833);
Sixth coordinates (x: y: z = 0: 2: 11),
The seventh coordinate (x: y: z = 0: 0: 1);
The eighth coordinate (x: y: z = 1: 0: 0);
Having a ratio of the number of atoms in a range in which the first coordinates are connected in order by line segments;
The range includes the first coordinate to the sixth coordinate, does not include the seventh coordinate and the eighth coordinate,
The oxide semiconductor film is characterized in that the density of the oxide semiconductor film is 90% or more of the density of single crystals having the same atomic ratio. An oxide semiconductor film containing indium, element M, and zinc,
The element M is an element selected from at least one of aluminum, gallium, yttrium, or tin,
The oxide semiconductor film has a plurality of crystal parts arranged randomly,
The plurality of crystal parts have no orientation,
A crystal having a diameter in the longitudinal direction of the plurality of crystal parts of 1 nm to 3 nm;
The oxide semiconductor film is characterized in that the density of the oxide semiconductor film is 90% or more of the density of single crystals having the same atomic ratio. An oxide semiconductor film having indium, gallium, and zinc,
The oxide semiconductor film has a plurality of crystal parts,
The plurality of crystal parts have no orientation,
The average diameter in the longitudinal direction of the plurality of crystal parts is 1 nm or more and 3 nm or less,
The density of the oxide semiconductor film, an oxide semiconductor film, wherein the 5.7 g / cm ³ or more 6.49 g / cm ³ or less. In claims 1 to 3,
The oxide semiconductor film is characterized in that the density of the oxide semiconductor film is 90% or more of the density of single crystals having the same atomic ratio. An oxide semiconductor film having indium, gallium, and zinc,
The oxide semiconductor film has a plurality of crystal parts arranged randomly,
The plurality of crystal parts have no orientation,
The average diameter A [nm] in the longitudinal direction of the plurality of crystal parts is 1 nm or more and 3 nm or less,
After the electron beam energy is irradiated to 1 × 10 ⁷ [e ⁻ / nm ² ] or more and less than 4 × 10 ⁸ [e ⁻ / nm ² ], the average B [nm] of the diameter in the longitudinal direction of the crystal part is An oxide semiconductor film that is larger than A × 0.7 and smaller than A × 1.3. In any one of Claims 1 thru | or 9,
The oxide semiconductor film is formed by a sputtering method,
The target used for the sputtering method has indium, element M, and zinc,
The atomic ratio of the indium, the element M, and the zinc of the target satisfies indium: element M: zinc = a: b: c,
The a, the b, and the c are in an equilibrium diagram with the three elements of the indium, the element M, and the zinc as vertices,
The first coordinates (a: b: c = 8: 14: 7);
The second coordinates (a: b: c = 2: 4: 3);
Third coordinates (a: b: c = 1: 2: 5.1);
Fourth coordinates (a: b: c = 1: 0: 1.7);
A fifth coordinate (a: b: c = 8: 0: 1);
Sixth coordinates (a: b: c = 6: 2: 1),
Having a ratio of the number of atoms in a range in which the first coordinates are connected in order by line segments;
The range includes the first coordinate to the sixth coordinate, and the oxide semiconductor film is characterized in that:   A semiconductor device comprising the oxide semiconductor film according to claim 1. In claim 11,
A first conductive layer;
A first insulating film in contact with an upper surface and a side surface of the first conductive layer;
A pair of electrodes in contact with the top surface of the oxide semiconductor film;
Have
The semiconductor device, wherein the oxide semiconductor film has a region in contact with an upper surface of the first insulating film. In claim 11,
A first conductive layer;
A first insulating film in contact with an upper surface and a side surface of the first conductive layer;
A second insulating film in contact with the upper surface of the oxide semiconductor film;
A pair of electrodes in contact with the top surface of the oxide semiconductor film and the top surface and side surfaces of the second insulating film;
The semiconductor device, wherein the oxide semiconductor film has a region in contact with an upper surface of the first insulating film. In claim 11,
A semiconductor device comprising a second oxide film in contact with an upper surface of the oxide semiconductor film. In claim 14,
The semiconductor device is characterized in that the oxide affinity of the oxide of the oxide semiconductor film is larger than the electron affinity of the oxide of the second oxide film. In claim 15,
The second oxide film includes indium, an element M, and zinc;
The element M is an element selected from at least one of aluminum, gallium, yttrium, or tin,
The ratio of the number of atoms of the indium, the element M, and the zinc of the second oxide film is represented by indium: element M: zinc = x ₂ : y ₂ : z ₂
The (x ₂ : y ₂ : z ₂ ) is an equilibrium diagram with the three elements of the indium, the element M and the zinc as vertices,
The first coordinates (8: 14: 7);
A second coordinate (2: 4: 3);
A third coordinate (2: 5: 7);
The fourth coordinate (51: 149: 300);
The fifth coordinate (1: 4: 10);
A sixth coordinate (1: 1: 4);
The seventh coordinate (2: 2: 1);
Having a ratio of the number of atoms in a range in which the first coordinates are connected in order by line segments;
The range includes the first coordinate to the seventh coordinate. A semiconductor device according to any one of claims 11 to 16,
A display element;
A display device comprising: A semiconductor device according to any one of claims 11 to 16, or a display device according to claim 17,
FPC,
A module comprising: A semiconductor device according to any one of claims 11 to 16, a display device according to claim 17, or a module according to claim 18.
Microphone, speaker, or operation keys,
An electronic device comprising: