JP2021168402A - Display device - Google Patents

Abstract

To provide a semiconductor device with excellent electric characteristics.SOLUTION: An electron beam is delivered using an electron beam whose half-width of a probe diameter is 1 nm while the position of an oxide semiconductor film and the position of the electron beam are moved relative to a plane where the oxide semiconductor film is formed, so that a plurality of electron diffraction patterns are observed. The electron diffraction patterns include 50 or more electron diffraction patterns observed at different places. Among the 50 or more electron diffraction patterns, the total of the ratio of first electron diffraction patterns and the ratio of second electron diffraction patterns is 100% and the ratio of the first electron diffraction patterns is 50% or more. The first electron diffraction patterns include a plurality of observation points without symmetry or a plurality of observation points disposed with a circular shape. The second electron diffraction patterns are formed of the oxide semiconductor film with observation points existing at corner points of a hexagon.SELECTED DRAWING: None

Description

The present invention relates to a product, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, manufacture, or composition (composition of matter). In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, a method for driving the same, or a method for manufacturing the same.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Transistors and semiconductor circuits are one aspect of semiconductor devices. Further, a computing device, a storage device, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

The physical characteristics of indium and oxides with zinc are interesting and have been studied a lot (
Non-Patent Document 1, Non-Patent Document 2). In Non-Patent Document 1, In _1-x Ga _{1 + x} O ₃ (ZnO)
_{It is stated that there is a homologous phase represented by m} (x is a number satisfying -1≤x≤1 and m is a natural number). In addition, the solid solution region of the homologous phase (solid solution r)
angle) is mentioned. For example, when In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and calcined at 1350 ° C., the solid solution region of the homologous phase when m = 1 is x.
There is a description of -0.33 to 0.08, and the solid solution region of the homologous phase when m = 2 is described as x of -0.68 to 0.32.

Further, as a compound having a spinel-type crystal structure, a compound represented by AB ₂ O ₄ (A and B are metals) is known. The Non-Patent Document _{1 In x Zn y Ga z O} w Example is shown in, x, y and z are ZnGa ₂ O ₄ composition in the vicinity, i.e. x, is y and z (x, y
, Z) = (0,1,2), it is described that a spinel-type crystal structure is likely to be formed or mixed when the value is close to (0,1,2).

In addition, a technique for constructing a transistor using a semiconductor material is drawing attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Document 1 and Patent Document 2).

Further, in recent years, with the increase in performance, miniaturization, or weight reduction of electronic devices, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density.

Japanese Unexamined Patent Publication No. 2007-123861 JP-A-2007-96055

M. Nakamura, N.M. Kimizuka, and T.K. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350 ° C.", J. Mol. Solid State Chem. , 1991, Vol. 93, pp. 298-315 M. Nespolo, A. Sato, T. et al. Osawa, and H. Ohashi, "Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. X-ray Structure Structure Study of 20kb Single Crystal Res. Technol. , 2000 Vol. 35, pp151-165

One of the problems of one aspect of the present invention is to impart good electrical characteristics to a semiconductor device.

Another issue is to provide a highly reliable semiconductor device.

Alternatively, one of the problems is to provide a good transistor with little variation in characteristics. Another object of the present invention is to provide a semiconductor device having a storage element having good holding characteristics. Another issue is to provide a semiconductor device suitable for miniaturization. Another issue is to provide a semiconductor device having a reduced circuit area. Alternatively, one of the issues is to provide a semiconductor device having a new configuration.

The description of these issues does not prevent the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc.
It is possible to extract problems other than these from the drawings, claims, and the like.

One aspect of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein the element M is at least one selected element of aluminum, gallium, yttrium, or tin. The ratio of the number of atoms of indium, element M and zinc is indium: element M.
: Zinc = x: y: z is satisfied, and x, y and z are the first coordinates (x: y: z = 8: 14) in the equilibrium state diagram with the three elements of indium, element M and zinc as the vertices. : 7), the second coordinate (x: y: z = 2: 4: 3), the third coordinate (x: y: z = 2: 5: 7), and the fourth coordinate (x: y: z = 51: 149: 300) and the fifth coordinate (x: y: z = 46: 288)
: 833), the sixth coordinate (x: y: z = 0: 2: 11), and the seventh coordinate (x: y: z =
The ratio of the number of atoms in the range in which 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the first coordinate are connected in order by a line segment. The range includes the first to sixth coordinates, does not include the seventh and eighth coordinates, and uses an electron beam having a probe diameter half-value width of 1 nm to form an oxide semiconductor film. When a plurality of electron diffraction patterns are observed by irradiating an electron beam while relatively moving the position of the oxide semiconductor film and the position of the electron beam with respect to the surface to be formed, a plurality of electron diffraction patterns are performed. The pattern has 50 or more electron diffraction patterns observed at different locations, and has a ratio of 50 or more electron diffraction patterns having a first electron diffraction pattern and a second electron diffraction pattern. The sum of the ratios is 100%, and the first
The electron diffraction pattern of is an observation point having no symmetry, or a plurality of observation points arranged in a circle, and the second electron diffraction pattern is an observation point located at the apex of the hexagon. It is an oxide semiconductor film having.

Alternatively, in one aspect of the present invention, the position of the oxide semiconductor film and the position of the electron beam are relative to the formed surface of the oxide semiconductor film by using an electron beam having a half-value width of the probe diameter of 1 nm. When a plurality of electron diffraction patterns are observed by irradiating an electron beam while moving the electron diffraction pattern, the plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at different locations, and 50. The sum of the ratio having the first electron diffraction pattern and the ratio having the second electron diffraction pattern among the number or more electron diffraction patterns is 100%, and the ratio having the first electron diffraction pattern is 50%. As described above, the first electron diffraction pattern has an observation point having no symmetry or a plurality of observation points arranged in a circle, and the second electron diffraction pattern is a hexagonal apex. It is an oxide semiconductor film having an observation point located at.

Alternatively, one aspect of the present invention is In: M (Al, Ga, Y, or Sn): Zn = x: y.
It is an oxide semiconductor film represented by the atomic number ratio of: z, and has coordinates x: y: z = 1: 0: 0, coordinates x: y: z = 0: 1: 0, and coordinates x: y. In the equilibrium state diagram with: z = 0: 0: 1, the first coordinate (x: y: z = 8: 14: 7) and the second coordinate (x: y: z = 2). :
4: 3), the third coordinate (x: y: z = 2: 5: 7), and the fourth coordinate (x: y: z = 51).
149: 300), the fifth coordinate (x: y: z = 46: 288: 833), the sixth coordinate (x: y: z = 0: 2: 11), and the seventh coordinate (x: y: z = 0: 2: 11). Within the range in which x: y: z = 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the first coordinate are connected in order by a line segment. By moving the position of the oxide semiconductor film and the position of the electron beam whose half-value width of the probe diameter is 1 nm relative to the surface to be formed of the oxide semiconductor film, 50 pieces are formed at different locations. Observing the above electron diffraction patterns, 50 or more electron diffraction patterns are at least an electron diffraction pattern having a plurality of asymmetrically arranged spots and an electron diffraction pattern having a plurality of spots arranged in a circle. And an electron diffraction pattern having spots arranged at the apex of the hexagon, the range including the first to sixth coordinates, and the seventh.
It is an oxide semiconductor film characterized by not including the coordinates of the above and the eighth coordinate.

Further, in the above configuration, the oxide semiconductor film has indium, an element M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, or tin, and is indium. , The ratio of the number of atoms of element M and zinc is indium: element M
: Zinc = x: y: z is satisfied, and x, y and z are the first coordinates (x: y: z = 8: 14) in the equilibrium state diagram with the three elements of indium, element M and zinc as the vertices. : 7), the second coordinate (x: y: z = 2: 4: 3), the third coordinate (x: y: z = 2: 5: 7), and the fourth coordinate (x: y: z = 51: 149: 300) and the fifth coordinate (x: y: z = 46: 288)
: 833), the sixth coordinate (x: y: z = 0: 2: 11), and the seventh coordinate (x: y: z =
0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the ratio of the number of atoms in the range connecting the first coordinate in order with a line segment. However, it is preferable that the range includes the first coordinate to the sixth coordinate and does not include the seventh coordinate and the eighth coordinate.

Alternatively, one aspect of the present invention is an oxide semiconductor film having indium, an element M, and zinc, and the oxide semiconductor film has a plurality of randomly arranged crystal portions and a plurality of crystals. The average diameter of the portions in the longitudinal direction is 1 nm or more and 3 nm or less, which is an oxide semiconductor film.

Alternatively, one aspect of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The ratio of the number of atoms of indium, element M and zinc satisfies indium: element M: zinc = x: y: z, and x, y and z have three elements of indium, element M and zinc as peaks. In the equilibrium state diagram, the first coordinates (x: y: z = 8: 14: 7)
And the second coordinate (x: y: z = 2: 4: 3) and the third coordinate (x: y: z = 2: 5: 7)
And the fourth coordinate (x: y: z = 51: 149: 300) and the fifth coordinate (x: y: z = 4).
6: 288: 833), the sixth coordinate (x: y: z = 0: 2: 11), and the seventh coordinate (x).
: Y: z = 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the first coordinate are connected in order by a line segment. It has a ratio of numbers, the range includes the first to sixth coordinates, does not include the seventh and eighth coordinates, and the density of the oxide semiconductor film is simple with the same atomic number ratio. It is an oxide semiconductor film having a crystal density of 90% or more.

Alternatively, one aspect of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. The oxide semiconductor film has a plurality of crystal portions arranged at random, and the plurality of crystal portions do not have orientation, and the diameter of the plurality of crystal portions in the longitudinal direction is 1 nm or more and 3 n.
The density of the oxide semiconductor film having crystals of m or less is 9 which is the density of single crystals having the same atomic number ratio.
It is an oxide semiconductor film having 0% or more.

Alternatively, one aspect of the present invention is an oxide semiconductor film having indium, gallium, and zinc, and the oxide semiconductor film has a plurality of crystal portions, and the plurality of crystal portions are oriented. the no, the average longitudinal diameter of the plurality of crystal parts is at 1nm or more 3nm or less, the density of the oxide semiconductor film is 5.7 g / cm ³ or more 6.49 g / cm ³ or less oxide It is a product semiconductor film. Further, in the above configuration, the density of the oxide semiconductor film is preferably 90% or more of the density of single crystals having the same atomic number ratio.

Alternatively, one aspect of the present invention is an oxide semiconductor film having indium, gallium, and zinc, and the oxide semiconductor film has a plurality of crystal portions arranged at random and a plurality of crystal portions. Has no orientation, and the average A [nm] of the longitudinal diameters of a plurality of crystal portions is 1 nm or more and 3
It is nm or less and the electron beam energy is 1 × 10 ⁷ [e ⁻ / nm ² ] or more 4 × 10 ⁸ [
The average diameter B [nm] in the longitudinal direction of the crystal portion after irradiation to less than e ⁻ / nm ^{2] is A ×.}
It is an oxide semiconductor film larger than 0.7 and smaller than A × 1.3.

Further, in the above configuration, the oxide semiconductor film is formed by a sputtering method, and the target used in the sputtering method has indium, element M, and zinc, and the target has indium, element M, and zinc atoms. The number ratio is indium: element M: zinc =
a: b: c is satisfied, and a, b, and c are the first coordinates (a: b: c = 8: 14:) in the equilibrium state diagram with the three elements of indium, element M, and zinc as the apex. 7), the second coordinate (a: b: c = 2: 4: 3), the third coordinate (a: b: c = 1: 2: 5.1), and the fourth coordinate (a). : B: c = 1: 0: 1.7), the fifth coordinate (a: b: c = 8: 0: 1), and the sixth coordinate (a: b: c = 6: 2: 1). ) And the first coordinate in order have a ratio of the number of atoms in the range connected by a line segment, and the range preferably includes the first coordinate to the sixth coordinate.

Alternatively, one aspect of the present invention is a semiconductor device having the oxide semiconductor film described above.
Further, in the above configuration, the oxide semiconductor has a first conductive layer, a first insulating film in contact with the upper surface and side surfaces of the first conductive layer, and a pair of electrodes in contact with the upper surface of the oxide semiconductor film. The membrane is the first
It is preferable to have a region in contact with the upper surface of the insulating film. Further, in the above configuration, the first conductive layer, the first insulating film in contact with the upper surface and the side surface of the first conductive layer, the second insulating film in contact with the upper surface of the oxide semiconductor film, and the oxide semiconductor film. It preferably has a pair of electrodes in contact with the upper surface and the upper surface and side surfaces of the second insulating film, and the oxide semiconductor film has a region in contact with the upper surface of the first insulating film. Further, in the above configuration, it is preferable to have a second oxide film in contact with the upper surface of the oxide semiconductor film. Further, in the above configuration, the electron affinity of the oxide of the oxide semiconductor film is preferably larger than the electron affinity of the oxide of the second oxide film. Further, in the above configuration, the second oxide film has indium, element M, and zinc, and has element M.
Is an element selected from at least one of aluminum, gallium, yttrium, or tin, and the ratio of the atomic numbers of indium, element M, and zinc contained in the second oxide film is indium: element M: zinc = x _{2: y} 2: is represented by _{z 2, (x 2: y} 2: z 2) is indium, at equilibrium diagram an apex three elements of the element M and zinc, the first coordinates (8: 1
4: 7), the second coordinate (2: 4: 3), the third coordinate (2: 5: 7), and the fourth coordinate (2: 5: 7).
51: 149: 300), the fifth coordinate (1: 4:10), and the sixth coordinate (1: 1: 4).
And the 7th coordinate (2: 2: 1) and the 1st coordinate in order have a ratio of the number of atoms in the range connected by a line segment, and the range is from the 1st coordinate to It is preferable to include the seventh coordinate.

Alternatively, one aspect of the present invention is a display device having the above-mentioned semiconductor device and a display element.

Alternatively, one aspect of the present invention is a module having the semiconductor device described above, or the display device described above, and an FPC.

Alternatively, one aspect of the present invention is an electronic device having the semiconductor device described above, the display device described above, or the module described above, and a microphone, a speaker, or an operation key.

According to one aspect of the present invention, good electrical characteristics can be imparted to the semiconductor device. again,
It is possible to provide a highly reliable semiconductor device.

Further, it is possible to provide a transistor with little variation. Further, it is possible to provide a semiconductor device having a storage element having good holding characteristics. Further, it is possible to provide a semiconductor device suitable for miniaturization. Further, it is possible to provide a semiconductor device having a reduced circuit area. Further, it is possible to provide a semiconductor device having a new configuration. The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not necessarily have to have all of these effects. In addition, effects other than these are self-evident from the description of the description, drawings, claims, etc., and from the description of the description, drawings, claims, etc.,
It is possible to extract effects other than these.

The figure explaining the atomic number ratio of the oxide film which concerns on one aspect of this invention. The figure explaining the atomic number ratio of the oxide film which concerns on one aspect of this invention. The figure explaining the atomic number ratio. The figure explaining the atomic number ratio of the oxide film which concerns on one aspect of this invention. The figure explaining the atomic number ratio of the target which concerns on one aspect of this invention. The figure explaining the atomic number ratio. The figure which shows the nanobeam electron diffraction pattern of an oxide semiconductor film, and the figure which shows an example of a transmission electron diffraction measuring apparatus. The figure which shows the analysis result by the X-ray diffractometer of nc-OS. The figure which shows the electron diffraction pattern of nc-OS. The figure explaining the crystal of _{InGaZnO 4.} The figure which shows the band structure of a part of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows the Cs correction high-resolution cross-sectional TEM image of CAAC-OS and nc-OS. The figure which shows the Cs correction high-resolution cross-sectional TEM image of CAAC-OS. The figure which shows the Cs correction high-resolution cross section TEM image of CAAC-OS. The figure which shows the Cs correction high-resolution cross-section TEM image of nc-OS. The figure which shows the Cs correction high-resolution cross-section TEM image of nc-OS. The figure which shows the pellet size observed by the Cs correction high-resolution cross-section TEM image of CAAC-OS and nc-OS, and the frequency thereof. The figure which shows the relationship between the atomic number ratio of a target, and the atomic number ratio of an oxide semiconductor film. The schematic diagram explaining the film formation model of nc-OS, and the figure which shows pellets. The schematic diagram explaining the film forming apparatus. A block diagram and a circuit diagram illustrating a display device. The figure of the display module which concerns on embodiment. A configuration example of an RF tag according to an embodiment. The figure which shows an example of a transistor. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. The figure which shows an example of the transistor which concerns on one aspect of this invention. Top view showing one aspect of a display device. A cross-sectional view showing one aspect of a display device. A cross-sectional view showing one aspect of a display device. The circuit diagram which concerns on embodiment. The figure which shows an example of the semiconductor device which concerns on one aspect of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the manufacturing method of the semiconductor device which concerns on one aspect of this invention. XRD evaluation result of the oxide semiconductor film according to one aspect of the present invention. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. TDS analysis result of oxide semiconductor film. The figure which shows the change of a crystal by electron beam irradiation. An example of using an RF tag according to an embodiment. An electronic device according to an embodiment. The figure which shows the film density of an oxide semiconductor film. The figure which shows the etching rate of an oxide semiconductor film. The figure which shows the amount of desorption gas emission of an oxide semiconductor film. The figure which shows the hydrogen concentration of the oxide semiconductor film. The figure which shows the crystal size of an oxide semiconductor film. The figure which shows the crystal size of an oxide semiconductor film. The figure which shows the CPM measurement result of the oxide semiconductor film. The figure which shows the CPM measurement result of the oxide semiconductor film. The figure which shows the CPM measurement result of the oxide semiconductor film. The figure which shows the Cs correction high-resolution cross-section TEM image of a-like OS. The figure which shows the hydrogen concentration of the oxide semiconductor film.

The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same parts or parts having similar functions, and the repeated description thereof will be omitted. Further, when referring to the same function, the hatch pattern may be the same and no particular sign may be added.

In addition, in each figure described in this specification, the size of each structure, the thickness of a layer, or a region is a term.
May be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

The ordinal numbers such as "first" and "second" in the present specification and the like are added to avoid confusion of the components, and are not limited numerically.

Further, in the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Also,"
"Approximately parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in the present specification is an IGBT (Insulated Gate Field Effect Transistor).
istor) and thin film transistor (TFT: Thin Film Transistor)
)including.

(Embodiment 1)
In this embodiment, an example of an oxide semiconductor film, which is one aspect of the present invention, will be described.

Oxide semiconductor films are roughly classified into non-single crystal oxide semiconductor films and single crystal oxide semiconductor films.
The non-single crystal oxide semiconductor film is CAAC-OS (C Axis Aligned Cry).
stalline Oxide Semiconductor) film, polycrystalline oxide semiconductor film, microcrystalline oxide semiconductor film, amorphous oxide semiconductor film, etc.

A single crystal may be formed by firing at a high temperature of, for example, about 1000 ° C. or higher. Therefore, from an industrial point of view, it can be said that it is preferable to use a non-single crystal oxide semiconductor film that can be formed at a lower temperature because a semiconductor device can be manufactured at a lower cost.

The smaller the grain boundary of the oxide semiconductor film, the more preferable. By reducing the grain boundaries, for example, the carrier mobility can be increased. By manufacturing a transistor using an oxide semiconductor film having a small grain boundary, for example, a transistor having a high field effect mobility may be realized. As will be described in detail later, examples of the non-single crystal oxide semiconductor film having a small grain boundary include an nc-OS film and a CAAC-OS film.

On the other hand, the oxide semiconductor film may have crystals having a spinel structure. Crystals with a spinel structure may be mixed in the CAAC-OS film or the nc-OS film to form a clear boundary (or grain boundary). At the boundary, for example, carrier scattering may increase and carrier mobility may decrease. Further, since the boundary portion tends to be a movement path for impurities and is considered to easily capture impurities, there is a concern that the concentration of impurities in the oxide semiconductor film may increase. again,
When a conductive film is formed on an oxide semiconductor film, elements contained in the conductive film, such as a metal, may diffuse to the boundary between the spinel and another region. Therefore, it is more preferable that the oxide semiconductor film does not contain or has a small amount of spinel-type crystal structure.

Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When the oxide semiconductor contains indium, for example, the carrier mobility (electron mobility) becomes high. Further, the oxide semiconductor preferably contains the element M. The element M is preferably aluminum, gallium,
Yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases. The element M is, for example, an element having a high binding energy with oxygen. For example, it is an element whose binding energy with oxygen is higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Further, the oxide semiconductor preferably contains zinc. Oxide semiconductors may be easily crystallized if they contain zinc. Here, an oxide containing indium, the element M, and zinc is referred to as an In-M-Zn oxide.

[About the ratio of the number of atoms]
The ratio of the number of atoms of the In—M—Zn oxide film, which is the oxide semiconductor film of one aspect of the present invention, is In:
It is expressed as M: Zn = x: y: z. The preferred ranges of x, y and z will be described with reference to FIGS. 1 and 2.

Here, the ratio of the number of atoms of each element will be described with reference to FIG. FIG. 3 shows x, y and z when the ratio of the number of atoms of the elements X, Y and Z in the XYZ oxide film is x: y: z.
It is a figure which shows the range of. The atomic number ratio of oxygen is not shown in FIG. Further, FIG. 3 may be referred to as an equilibrium phase diagram. 3 (A) and 3 (B) show an equilateral triangle having X, Y, and Z as vertices, and coordinates R (4: 2: 1) as an example of coordinates. Here, each vertex represents the elements X, Y and Z, respectively. The value of each term in the ratio of atomic numbers is higher as the coordinates are closer to each vertex and lower as the coordinates are farther away. Further, as shown in FIG. 3A, the value of each term in the ratio of the number of atoms is represented by the length of the perpendicular line from the coordinates to the opposite side of the apex of the triangle. For example, in the case of element X, it is represented by the length of the perpendicular line 21 from the coordinates to the opposite side of the vertex X, that is, the side YZ. Therefore, in the coordinate R shown in FIG. 3, the atomic number ratio of the element X, the element Y, and the element Z is the ratio of the lengths of the perpendicular line 21, the perpendicular line 22, and the perpendicular line 23, that is, x: y: z = 4: 2: 1. Indicates that there is. Further, let γ be the point where the straight line passing through the vertex X and the coordinate R intersects the side YZ. At this time, if the ratio of the length of the line segment Yγ to the length of the line segment γZ is Yγ: γZ, then Yγ: γZ = (the number of atoms of the element Z) :( the number of atoms of the element Y).

Further, as shown in FIG. 3B, three straight lines passing through the coordinates R and parallel to the three sides of the triangle are drawn. At this time, x, y, and z can be represented as shown in FIG. 3B by using the intersections of the three straight lines and the three sides.

In FIG. 6, the range of the case where x: y: z satisfies the following equation in the In—M—Zn oxide film is shown by a broken line.

x: y: z = (1-α): (1 + α): m (-1 ≦ α ≦ 1)

Here, FIG. 6 shows the case of m = 1, 2, 3, 4, 5.

As described in Non-Patent Document 1, in In—M—Zn oxide, InMO ₃ (Zn)
O) It is known that there is a homologous phase (homologas series) represented by _{m (m is a natural number).} Here, consider the case where the element M is Ga as an example. The region shown by the thick straight line in FIG. 6 can have a solid solution region of a single phase when _{, for example, powders of In 2} O ₃ , Ga ₂ O _{3, and Zn O are mixed and fired at 1350 ° C.} Is a known composition. The solid solution area is
It is known that it becomes wider as the value of m is increased, that is, the ratio of zinc is increased.

Further, the coordinates indicated by the square symbol in FIG. 6 are, as described in Non-Patent Document 1, when, for example _{, powders of In 2} O ₃ , Ga ₂ O ₃ , and Zn O are mixed and fired at 1350 ° C. ,
It is a composition known to easily mix spinel-type crystal structures. As shown in FIG. 6, when _{the composition in the vicinity of ZnGa 2} O ₄ , that is, x, y and z have values close to (x, y, z) = (0,2,1), a spinel-type crystal It is described in Non-Patent Document 1 that structures are easily formed or mixed.

The In—M—Zn oxide film, which is the oxide semiconductor film of one aspect of the present invention, preferably has an increased proportion of indium. In the In-M-Zn oxide film, the s orbitals of metal atoms mainly contribute to carrier conduction, and by increasing the indium content, more s orbitals overlap, so that the indium content is high. Carrier mobility is higher. By manufacturing a transistor using such a film in the channel region, for example, a transistor having high field effect mobility can be realized. For example, x / y> 0.5 is preferable.
x / y ≧ 0.75 is more preferable, and x / y ≧ 1 is even more preferable. Also, (x + y) ≧ z
Is preferable.

Therefore, x, y and z preferably have a ratio of the number of atoms in the region 11 shown in FIG. 1, and more preferably have a ratio of the number of atoms in the region 12 shown in FIG. 2 (A). Here, the area 11 is
The first coordinate K (x: y: z = 8: 14: 7) and the second coordinate R (x: y: z = 2: 4: 3)
), The third coordinate L (x: y: z = 2: 5: 7), and the fourth coordinate M (x: y: z = 51:).
149: 300), the fifth coordinate N (x: y: z = 46: 288: 833), the sixth coordinate O (x: y: z = 0: 2: 11), and the seventh coordinate. P (x: y: z = 0: 0: 1), the eighth coordinate Q (x: y: z = 1: 0: 0), and the first coordinate K are sequentially arranged by a line segment. Within the connected area. The region 11 includes a line segment connecting eight points. Further, the coordinates P and the coordinates Q are excluded from the region 11, and the other coordinates are included in the region 11. Further, the area 12 has the first coordinate K.
(X: y: z = 8: 14: 7), the second coordinate R (x: y: z = 2: 4: 3), and the third coordinate L (x: y: z = 2: 5). : 7), the fourth coordinate S (x: y: z = 1: 0: 1), the fifth coordinate Q (x: y: z = 1: 0: 0), and the first coordinate. It is in the area connecting K in order with a line segment. The region 12 includes a line segment connecting five points. Further, the coordinate Q is excluded from the area 12, and the other coordinates are included in the area 12.

[Structure of oxide semiconductor film]
Next, the structure of the oxide semiconductor film will be described.

First, the CAAC-OS film will be described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis oriented crystal portions.

Transmission electron microscope (TEM)
By oscopy), a plurality of crystal portions can be confirmed by observing a bright-field image of the CAAC-OS film and a composite analysis image (also referred to as a high-resolution TEM image) of the diffraction pattern. On the other hand, even with a high-resolution TEM image, a clear boundary between crystal portions, that is, a grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, the CAAC-OS film is
It can be said that the decrease in electron mobility due to the grain boundaries is unlikely to occur.

By observing the high-resolution TEM image of the cross section of the CAAC-OS film from a direction substantially parallel to the sample surface, it can be confirmed that the metal atoms are arranged in layers in the crystal portion. Each layer of the metal atom has a shape that reflects the unevenness of the surface (also referred to as the surface to be formed) or the upper surface of the CAAC-OS film, and is arranged parallel to the surface to be formed or the upper surface of the CAAC-OS film. ..

On the other hand, when observing the high-resolution TEM image of the plane of the CAAC-OS film from a direction substantially perpendicular to the sample plane, it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape in the crystal portion. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When electron diffraction is performed on the CAAC-OS film, spots (bright spots) showing orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of 1 nm or more and 30 nm or less is performed on the surface to be formed or the upper surface of the CAAC-OS film, spots are observed (FIG. 7 (B)). reference.).

From the high-resolution TEM image of the cross section and the high-resolution TEM image of the plane, it can be seen that the crystal portion of the CAAC-OS film has orientation.

Most of the crystal parts contained in the CAAC-OS film have a size that fits in a cube having a side of less than 100 nm. Therefore, the crystal portion contained in the CAAC-OS film has 10 sides.
It also includes cases where the size fits within a cube of less than nm, less than 5 nm, or less than 3 nm. However, one large crystal region may be formed by connecting a plurality of crystal portions contained in the CAAC-OS film. For example, in a flat high-resolution TEM image, a ^{crystal region having a size of 2500 nm 2} or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

X-ray diffraction (XRD: X-Ray Diffraction) with respect to the CAAC-OS film
When structural analysis is performed using the device, for example, CAAC-OS having crystals of _{InGaZnO 4}
In the analysis of the film by the out-of-plane method, a peak may appear in the vicinity of the diffraction angle (2θ) of 31 °. Since this peak is _{attributed to the (009) plane of the InGaZnO 4} crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the upper surface. It can be confirmed that

On the other hand, in-pl in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis.
In the analysis by the ane method, a peak may appear near 56 ° in 2θ. This peak is attributed to the (110) plane of _{the InGaZnO 4 crystal.} In the case of _{a single crystal oxide semiconductor film of InGaZnO 4} , 2θ is fixed in the vicinity of 56 °, and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis). 110) Six peaks attributed to the crystal plane equivalent to the plane are observed. On the other hand, in the case of CAAC-OS film, 2θ is 5
Even when fixed at around 6 ° and φ-scanned, no clear peak appears.

From the above, in the CAAC-OS film, the a-axis and b-axis orientations are irregular between different crystal portions, but they have c-axis orientation and the c-axis is the normal of the surface to be formed or the upper surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of the metal atoms arranged in layers confirmed by the high-resolution TEM observation of the cross section described above is a plane parallel to the ab plane of the crystal.

The crystal portion is formed when a CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film.

Further, the distribution of the c-axis oriented crystal portion in the CAAC-OS film does not have to be uniform. For example, when the crystal portion of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region near the upper surface is the ratio of the crystal portion oriented in the c-axis rather than the region near the surface to be formed. May be high. Further, in the CAAC-OS film to which impurities have been added, the region to which the impurities have been added may be altered to form regions having different proportions of crystal portions that are partially c-axis oriented.

The out-of-plane of the CAAC-OS film having InGaZnO _{4 crystals.}
In the analysis by the method, in addition to the peak where 2θ is in the vicinity of 31 °, the peak may appear in the vicinity where 2θ is in the vicinity of 36 °. The peak in which 2θ is in the vicinity of 36 ° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. In the CAAC-OS film, it is preferable that 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 °.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger bond with oxygen than the metal elements constituting the oxide semiconductor film, disturb the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and have crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc. have a large atomic radius (or molecular radius), so if they are contained inside the oxide semiconductor film, they disturb the atomic arrangement of the oxide semiconductor film and are crystalline. It becomes a factor to reduce. The impurities contained in the oxide semiconductor film may serve as a carrier trap or a carrier generation source.

Further, for example, oxygen deficiency in the oxide semiconductor film may become a carrier trap or a carrier generation source by capturing hydrogen. The CAAC-OS film is an oxide semiconductor film having a low defect level density. Specifically, it is ^{less than 8 × 10 11} / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 ×.
It may be an oxide semiconductor of 10 ^-9 / cm ³ or more carrier density.

Further, the transistor using the CAAC-OS film has a small fluctuation in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, the polycrystalline oxide semiconductor film will be described.

Crystal grains can be confirmed in the high-resolution TEM image of the polycrystalline oxide semiconductor film.
The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, 2 nm or more in a high-resolution TEM image.
It often has a particle size of 00 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less. Further, in the polycrystalline oxide semiconductor film, the crystal grain boundaries may be confirmed in a high-resolution TEM image.

The polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation may be different between the plurality of crystal grains. Further, when the structure of the polycrystalline oxide semiconductor film is analyzed using the XRD device, for example, the ou of the polycrystalline oxide semiconductor film having crystals of _{InGaZnO 4 is obtained.}
In the analysis by the t-of-plane method, a peak in which 2θ is in the vicinity of 31 °, a peak in which 2θ is in the vicinity of 36 °, or other peaks may appear.

Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, the transistor using the polycrystalline oxide semiconductor film has high field effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may segregate at the grain boundaries. again,
The grain boundaries of the polycrystalline oxide semiconductor film are defect levels. Since the crystal grain boundaries of a polycrystalline oxide semiconductor film may be a carrier trap or a carrier generation source, a transistor using a polycrystalline oxide semiconductor film has a large fluctuation in electrical characteristics and is not reliable. May become.

Next, the microcrystalline oxide semiconductor film will be described.

The microcrystalline oxide semiconductor film has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in the microcrystalline oxide semiconductor film often has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, an oxide semiconductor film having nanocrystals (nc: nanocrystals) which are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less,
c-OS (nanocrystalline Oxide Semiconductor Ductor)
) Called a membrane. Further, in the nc-OS film, for example, the crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, the nc-OS film does not show regularity in crystal orientation between different crystal portions. Therefore, no orientation is observed in the entire film.
Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, an XRD that uses X-rays having a diameter larger than that of the crystal portion for the nc-OS film.
When the structural analysis is performed using the apparatus, the peak near 31 ° indicating the crystal plane is not detected in the analysis by the out-of-plane method (see FIG. 8). Further, when electron diffraction (also referred to as selected area electron diffraction) using an electron beam having a probe diameter larger than that of the crystal portion (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Will be done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter close to the size of the crystal portion or smaller than the crystal portion, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS film, a region having high brightness (in a ring shape) may be observed in a circular motion. Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region. For example, as shown in FIG. 9A, when nanobeam electron diffraction with probe diameters of 30 nm, 20 nm, 10 nm or 1 nm is performed on an nc-OS having a thickness of about 50 nm, a circle is drawn ( A region with high brightness (in a ring shape) is observed. Further, as the probe diameter is reduced, it can be seen that the ring-shaped region is formed from a plurality of spots.

For more detailed structural analysis, the nc-OS film is sliced to a thickness of several nm (about 5 nm), and a transmitted electron diffraction pattern is obtained using an electron beam having a probe diameter of 1 nm. As a result, a transmitted electron diffraction pattern having a spot showing crystallinity shown in FIG. 9B was obtained.

Further, when nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions may be observed.

The nc-OS film is an oxide semiconductor film having higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower defect level density than the amorphous oxide semiconductor film.

In addition, the nc-OS film does not show regularity in crystal orientation between different crystal portions. for that reason,
The nc-OS film has a higher defect level density than the CAAC-OS film. Therefore, nc-O
The S film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film having a high carrier density may have a high electron mobility. Therefore, the transistor using the nc-OS film may have high field effect mobility.

The nc-OS film can be formed at a lower temperature than the CAAC-OS film. Also, nc-OS
The film may be able to be formed even if it contains a relatively large amount of impurities. Therefore, n
The c-OS film may be easier to form than the CAAC-OS film. Therefore, nc-
A semiconductor device having a transistor using an OS film may be manufactured with high productivity.

In addition, the nc-OS membrane may have appropriate oxygen permeability. When it has an appropriate oxygen permeability, for example, oxygen released from a membrane having excess oxygen tends to diffuse throughout the nc-OS membrane. Therefore, in the nc-OS membrane, it may be easy to reduce oxygen deficiency.

A low impurity concentration and a low defect level density (less oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. Since the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has few carrier sources, the carrier density can be lowered. Therefore, the transistor using the oxide semiconductor film rarely has electrical characteristics (also referred to as normal on) in which the threshold voltage becomes negative. Further, the oxide semiconductor film having high purity intrinsicity or substantially high purity intrinsicity has few carrier traps. Therefore, the transistor using the oxide semiconductor film is a highly reliable transistor with little fluctuation in electrical characteristics. The charge captured by the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor film having a high impurity concentration and a high defect level density may have unstable electrical characteristics.

Next, the amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal portion. An example is an oxide semiconductor film having an amorphous state such as quartz.

The crystal part of the amorphous oxide semiconductor film cannot be confirmed in the high-resolution TEM image.

A structural analysis of the amorphous oxide semiconductor film using an XRD device shows that out-of-
In the analysis by the plane method, the peak indicating the crystal plane is not detected. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration.
The amorphous oxide semiconductor film is an oxide semiconductor film having a high defect level density.

An oxide semiconductor film having a high impurity concentration and a high defect level density is an oxide semiconductor film having many carrier traps and carrier generation sources.

Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, it may be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high defect level density, carrier traps may increase. Therefore, the transistor using the amorphous oxide semiconductor film is compared with the transistor using the CAAC-OS film or the nc-OS film.
The transistor has a large fluctuation in electrical characteristics and has low reliability.

Next, the single crystal oxide semiconductor film will be described.

The single crystal oxide semiconductor film is an oxide semiconductor film having a low impurity concentration and a low defect level density (less oxygen deficiency). Therefore, the carrier density can be lowered. Therefore, a transistor using a single crystal oxide semiconductor film is unlikely to have normally-on electrical characteristics. Further, since the single crystal oxide semiconductor film has a low impurity concentration and a low defect level density, carrier traps may be reduced. Therefore, a transistor using a single crystal oxide semiconductor film is a highly reliable transistor with little fluctuation in electrical characteristics.

The density of the oxide semiconductor film increases when there are few defects. In addition, the oxide semiconductor film is
The higher the crystallinity, the higher the density. Further, the density of the oxide semiconductor film increases when the concentration of impurities such as hydrogen is low. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. Further, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. Moreover, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. Further, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

The oxide semiconductor film may have a structure showing physical properties between the nc-OS film and the amorphous oxide semiconductor film. Oxide semiconductor films having such a structure are particularly suitable for amorphous-like oxide semiconductors (amorphous-like oxide semiconductors).
: A-like OS) Membrane.

In the a-like OS film, voids (also referred to as voids) may be observed in a high-resolution TEM image. Further, in the high-resolution TEM image, it has a region where the crystal portion can be clearly confirmed and a region where the crystal portion cannot be confirmed. The a-like OS film may be crystallized by a small amount of electron irradiation as observed by TEM, and the growth of the crystal portion may be observed. On the other hand, if it is a good quality nc-OS film, crystallization by a small amount of electron irradiation as observed by TEM is hardly observed.

The size of the crystal part of the a-like OS film and the nc-OS film can be measured by using a high-resolution TEM image. For example, _{the crystal of InGaZnO 4} has a layered structure, and has two Ga-Zn-O layers between the In-O layers. The unit cell of the crystal of InGaZnO ₄ has a structure in which a total of 9 layers are stacked in a layered manner in the c-axis direction, which has 3 In-O layers and 6 Ga-Zn-O layers. Therefore, the distance between these adjacent layers is about the same as the grid plane distance (also referred to as d value) of the (009) plane, and the value is 0.29 n from the crystal structure analysis.
It is required to be m. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe is In in the place where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.
It was considered to correspond to the ab plane of the crystal of _{GaZnO 4.} The maximum length of the plaid in the observed region is defined as the size of the crystal part of the a-like OS film and the nc-OS film. The size of the crystal portion is selectively evaluated with a size of 0.8 nm or more.

Further, since it has a void, the a-like OS has a structure having a lower density than that of the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition.

In some cases, single crystals having the same composition do not exist. In that case, the density corresponding to the single crystal in the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

The oxide semiconductor film may be, for example, a laminated film having two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film. ..

[Nanobeam electron diffraction]
Next, nanobeam electron diffraction will be described.

When the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nanobeam electron diffraction.

FIG. 7C shows an electron gun chamber 610, an optical system 612 under the electron gun chamber 610, and an optical system 61.
The sample chamber 614 under the sample chamber 614, the optical system 616 under the sample chamber 614, the observation chamber 620 under the optical system 616, the camera 618 installed in the observation chamber 620, and the film chamber under the observation chamber 620. A transmission electron diffraction measuring device having 622 and is shown. The camera 618 is installed toward the inside of the observation room 620. It is not necessary to have the film chamber 622.

Further, FIG. 7 (D) shows the internal structure of the transmitted electron diffraction measuring device shown in FIG. 7 (C). Inside the transmitted electron diffraction measuring device, the electrons emitted from the electron gun installed in the electron gun chamber 610 are irradiated to the substance 628 arranged in the sample chamber 614 via the optical system 612. Matter 628
The electrons that have passed through the observing chamber 620 enter the fluorescent plate 632 installed inside the observation chamber 620 via the optical system 616. In the fluorescent plate 632, the transmitted electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of the incident electrons.

The camera 618 is installed facing the fluorescent plate 632, and can photograph the pattern appearing on the fluorescent plate 632. The angle formed by the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15 ° or more and 80 ° or less, 30 ° or more and 75 ° or less, or 45 ° or more and 70 °. It is as follows. The smaller the angle, the greater the distortion of the transmitted electron diffraction pattern captured by the camera 618. However, if the angle is known in advance, it is possible to correct the distortion of the obtained transmitted electron diffraction pattern. The camera 618 may be installed in the film chamber 622. For example, the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmitted electron diffraction pattern with less distortion can be photographed from the back surface of the fluorescent plate 632.

In the sample chamber 614, a holder for fixing the substance 628 as a sample is installed.
The holder has a structure that allows electrons passing through the substance 628 to pass through. The holder may have, for example, a function of moving the substance 628 to the X-axis, the Y-axis, the Z-axis, or the like. The movement function of the holder may have an accuracy of moving in a range of, for example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less. The optimum range may be set according to the structure of the substance 628.

Next, a method of measuring the transmitted electron diffraction pattern of a substance using the above-mentioned transmitted electron diffraction measuring device will be described.

For example, as shown in FIG. 7D, by changing (scanning) the irradiation position of electron 624, which is a nanobeam in a substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 7B is observed. Alternatively, if the substance 628 is an nc-OS film, a diffraction pattern as shown in FIG. 7A, for example, a diffraction pattern having a plurality of bright spots arranged in a circle (ring with bright spots). Diffraction pattern) is observed. Further, the diffraction pattern shown in FIG. 7A has bright spots that are not symmetrically arranged (have no symmetry).

As shown in FIG. 7B, in the diffraction pattern of the CAAC-OS film, for example, a spot located at the apex of the hexagon is confirmed. In the CAAC-OS film, by scanning the irradiation position, it can be seen that the orientation of the hexagon is not uniform and is rotating little by little. Also, the angle of rotation has a certain width.

Alternatively, in the diffraction pattern of the CAAC-OS film, by scanning the irradiation position,
It can be seen that it rotates little by little around the c-axis. It can be said that, for example, the surface formed by the a-axis and the b-axis is rotating.

By the way, a region in which the substance 628 has a diffraction pattern similar to that of the CAAC-OS film (hereinafter referred to as a region having a CAAC structure) and a region in which a diffraction pattern similar to that of the nc-OS film is observed (hereinafter referred to as an nc structure). It may have (referred to as a region having). Here, the ratio of the region where the diffraction pattern of the CAAC-OS film is observed in a certain range is defined as the CAAC ratio (CAAC ratio).
Also called CAAC conversion rate. ) Can be expressed. Similarly, the ratio of the region where the diffraction pattern similar to that of the nc-OS film is observed can be expressed by the nc ratio (also referred to as the nc conversion rate).

The method for evaluating the CAAC ratio of the CAAC-OS film will be described below. The measurement points are randomly selected, the transmitted electron diffraction pattern is acquired, and the ratio of the number of measurement points where the diffraction pattern of the CAAC-OS film is observed to the total number of measurement points is calculated. Here, the number of measurement points is preferably 50 points or more, and more preferably 100 points or more.

As a method of randomly selecting measurement points, for example, the irradiation position may be scanned linearly and a diffraction pattern may be acquired at regular intervals of time. CAAC by scanning the irradiation position
It is preferable because the boundary between the region having a structure and other regions can be confirmed. In addition, nc
Similarly, the conversion rate can be calculated by randomly selecting a measurement point and acquiring a transmitted electron diffraction pattern.

By using such a measurement method, it may be possible to analyze the structure of an oxide semiconductor film having a plurality of structures.

In the oxide semiconductor film according to one aspect of the present invention, for example, the sum of the nc ratio and the CAAC ratio is 80%.
It is preferably 90% or more and 100% or less, 95% or more and 100% or less, 98% or more and 100% or less, and 9
More preferably, it is 9% or more and 100% or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film having a clear grain boundary with few grain boundaries can be realized. By reducing the clear grain boundaries, for example, the carrier mobility of the oxide semiconductor film can be increased.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor film, which is one aspect of the present invention, will be described.

The nc-OS film may be formed even at a relatively low film formation temperature as compared with the CAAC-OS film. For example, it may be possible to form the substrate without heating the substrate. Therefore, a semiconductor device having a transistor using an nc-OS film may be manufactured with high productivity.

Further, since the nc-OS membrane has an appropriate oxygen permeability, oxygen can be easily diffused to the entire membrane, and oxygen deficiency may be more easily reduced. Therefore, it may be possible to realize an oxide semiconductor film having a low defect density. Therefore, it may be possible to improve the characteristics of the semiconductor device having the transistor using the nc-OS film. In addition, reliability may be improved.

Here, both the nc-OS film and the CAAC-OS film have a layered atomic arrangement. Such layered atomic arrangements can be observed using, for example, TEM.

Here, for the nc-OS film and the CAAC film, spherical aberration correction (Spherical)
Transmission electron microscopy (TEM:) using the Aberration Corrector function
An image (also referred to as a TEM image) obtained by (Transmission Electron Microscope) is observed. A composite analysis image of a bright field image and a diffraction pattern by TEM observation is called a high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM
The image can be obtained, for example, by the atomic resolution analysis electron microscope JEM-ARM20 manufactured by JEOL Ltd.
It can be done by 0F or the like.

Crystal size and orientation will be investigated by analyzing Cs-corrected high-resolution cross-sectional TEM images in more detail in CAAC-OS and nc-OS. Hereinafter, the crystal portion of nc-OS may be referred to as a pellet. For the size and orientation of crystals, pellets are extracted in a range of, for example, 20 nm square or more in a cross-sectional TEM image, and the size and orientation thereof are investigated.

FIG. 17A is a Cs-corrected high-resolution cross-sectional TEM image of the CAAC-OS. Further, FIG. 17B is a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS. The left and right figures are observations of the same location, and the right figure has an auxiliary line indicating the pellets.

FIG. 18A is a cross-sectional TEM image of the CAAC-OS film formed by the DC sputtering method. Further, FIG. 18B is an enlarged Cs-corrected high-resolution cross-sectional TEM image thereof.
In FIG. 18B, the number of pellets is counted and a frequency distribution is made for the size and orientation thereof (see FIG. 22A). Here, the arrow shown in FIG. 18A indicates the direction perpendicular to the sample surface. The direction of the white line shown in FIG. 18B indicates the direction of the pellet, and the length of the white line indicates the size of the pellet.

FIG. 19A is a cross-sectional TEM image of the CAAC-OS film formed by the RF sputtering method. Further, FIG. 19B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged.
In FIG. 19B, the number of pellets is counted and a frequency distribution is made for the size and orientation thereof (see FIG. 22B).

FIG. 20A is a cross-sectional TEM image of the nc-OS formed by the DC sputtering method.
Further, FIG. 20B is an enlarged Cs-corrected high-resolution cross-sectional TEM image thereof. Figure 2
At 0 (B), the number of pellets is counted and a frequency distribution is made for their size and orientation (see FIG. 22 (C)).

FIG. 21 (A) is a cross-sectional TEM image of the nc-OS formed by the RF sputtering method.
Further, FIG. 21B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged. Figure 2
In 1 (B), the number of pellets is counted and a frequency distribution is made for the size and orientation thereof (see FIG. 22 (D)).

The table below is the result of summarizing FIG. 22. Here, the orientation of the pellet indicates the absolute value of the angle with respect to the sample surface.

The nc-OS preferably has pellets having a size of, for example, preferably 0.5 nm or more and 3 nm or less, more preferably 1 nm or more and 3 nm or less. Also, in nc-OS,
As for the orientation of the pellets, it can be seen that the RF sputtering method is more oriented in the direction perpendicular to the sample plane than the DC sputtering method. Here, the ratio of the nc-OS pellet orientation to the sample surface is preferably 0 ° or more and less than 30 °, for example, 0% or more and 70% or less, and the ratio of 30 ° or more and less than 60 ° is, for example, 10. % Or more and 60% or less are preferable, and the ratio of 60 ° or more and less than 90 ° is preferably 0% or more and 60% or less, for example. nc-OS is CAAC-OS
It can be seen that the orientation of the pellets is random compared to.

An oxide semiconductor film having such pellets can be described by, for example, the following film formation model.

[Film film model]
The nc-OS film formation model will be described below.

FIG. 24 is a schematic view of a film forming chamber showing how the nc-OS is formed by the sputtering method.

The target 5130 is glued onto the backing plate. Target 5130
And under the backing plate, a plurality of magnets are arranged. A magnetic field is generated on the target 5130 by the plurality of magnets. A sputtering method that uses the magnetic field of a magnet to increase the film formation speed is called a magnetron sputtering method.

The target 5130 has a polycrystalline structure, and any of the crystal grains includes a cleavage plane.
The details of the cleavage plane will be described later.

The substrate 5120 is arranged so as to face the target 5130, and the distance d (
It is also called the target-board distance (TS-S distance). ) Is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. Most of the film formation chamber is a film formation gas (for example,
It is filled with oxygen, argon, or a mixed gas containing oxygen in a proportion of 50% by volume or more), and 0.
It is controlled to 01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage above a certain level to the target 5130, discharge starts and plasma is confirmed. A high-density plasma region is formed by the magnetic field on the target 5130. In the high-density plasma region, ions 5101 are generated by ionizing the film-forming gas. The ion 5101 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar).
⁺ ) And so on.

The ion 5101 is accelerated toward the target 5130 by the electric field and eventually collides with the target 5130. At this time, the pellets 5100a and the pellets 5100b, which are flat or pellet-shaped sputtered particles, are peeled off from the cleaved surface and beaten out. The structures of the pellets 5100a and the pellets 5100b may be distorted due to the impact of the collision of the ions 5101.

Pellet 5100a is a flat or pellet-shaped sputtered particle having a triangular, for example, equilateral triangular plane. Further, the pellet 5100b is a flat plate-shaped or pellet-shaped sputtered particle having a hexagonal, for example, a regular hexagonal flat surface. Plate-shaped or pellet-shaped sputtered particles such as pellets 5100a and pellets 5100b are collectively referred to as pellets. The planar shape of the pellet is not limited to triangles and hexagons, for example, triangles are 2.
The shape may be a combination of 6 or more. For example, it may be a quadrangle in which two equilateral triangles are combined.

The thickness of the pellet is determined according to the type of film-forming gas and the like. The thickness of the pellets is preferably uniform. Further, it is preferable that the sputtered particles are in the form of pellets having no thickness, rather than in the form of thick dice.

The pellets may be negatively or positively charged on the sides by receiving a charge as they pass through the plasma. The pellet has oxygen atoms on the sides, which can be negatively charged.

As shown in FIG. 24, for example, the pellet flies in the plasma like a kite and flutters up to the top of the substrate 5120. Since the pellets are charged, repulsive force is generated when the area where other pellets have already been deposited approaches. Here, on the upper surface of the substrate 5120, a magnetic field in a direction parallel to the upper surface of the substrate 5120 is generated. Further, since a potential difference is given between the substrate 5120 and the target 5130, the substrate 5120 to the target 5
A current is flowing toward 130. Therefore, the pellet receives a force (Lorentz force) on the upper surface of the substrate 5120 by the action of a magnetic field and an electric current. In order to increase the force applied to the pellets, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more on the upper surface of the substrate 5120. It is advisable to provide an area of Alternatively, on the upper surface of the substrate 5120, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more the magnetic field in the direction perpendicular to the upper surface of the substrate 5120. More preferably, it is preferable to provide a region that is 5 times or more.

It is considered that pellets are deposited on the substrate 5120 by the above model.
Therefore, unlike epitaxial growth, it can be seen that nc-OS can be formed even when the surface to be formed does not have a crystal structure. For example, even if the structure of the upper surface (surface to be formed) of the substrate 5120 is an amorphous structure, it is possible to form an nc-OS film.

Since nc-OS is formed by such a model, it is preferable that the sputtered particles are in the form of pellets having no thickness. If the sputtered particles are in the shape of a thick dice,
The surface of the sputtered particles directed onto the substrate 5120 may not be constant, and the thickness and crystal orientation may not be uniform.

Further, when the substrate 5120 is heated, the resistance such as friction between the pellet and the substrate 5120 is smaller. As a result, the pellets glide over the top surface of the substrate 5120. The movement of the pellet occurs with the flat plate surface of the pellet facing the substrate 5120. After that, when it reaches the side surface of another pellet 5100 that has already been deposited, the side surfaces are bonded to each other to obtain a CAAC-OS film.

When the substrate 5120 is not heated, the resistance such as friction between the pellet and the substrate 5120 is large. As a result, it is difficult for the pellets to move so as to glide over the upper surface of the substrate 5120, and nc-OS can be obtained by irregularly accumulating the pellets.

CAAC-OS heats the substrate 5120 to form a film, whereas nc-OS heats the substrate 51.
The film can be formed without heating 20.

Further, for example, as shown in FIG. 25, the atmosphere in the chamber is preferably 500 at room temperature or higher.
It may be heated at ° C. or lower, more preferably 200 ° C. or higher and 400 ° C. or lower. A lamp 5140 such as a halogen lamp may be used for heating the atmosphere. Heating the atmosphere, for example, heats pellets flying in the chamber, which can reduce defects. Also, the pellet size may increase. Further, by heating the atmosphere, for example, the moisture in the chamber is easily evaporated, and the degree of vacuum can be further increased.

[Cleavage surface]
In the following, the cleavage surface of the target described in the film formation model of nc-OS will be described.

First, the cleavage plane of the target will be described with reference to FIG. In FIG. 10, InGaZ
showing the structure of a crystal of nO _4. Note that FIG. 10A shows a structure when the crystal of _{InGaZnO 4} is observed from a direction parallel to the b-axis with the c-axis facing upward. Further, FIG. 10 (B) shows c.
The structure when the crystal of _{InGaZnO 4} is observed from the direction parallel to the axis is shown.

The energy required for cleavage at each crystal plane of the _{InGaZnO 4 crystal is calculated by first-principles calculation.} For the calculation, a density functional theory program (CASTEP) using a pseudopotential and a plane wave basis is used. An ultra-soft pseudopotential is used as the pseudopotential. Moreover, GGA PBE is used as a functional. The cutoff energy is 400 eV.

The energy of the structure in the initial state is derived after the structure optimization including the cell size is performed. Further, the energy of the structure after cleavage on each surface is derived after the structural optimization of the atomic arrangement is performed with the cell size fixed.

_{Based on the crystal structure of InGaZnO 4} shown in FIG. 10, a structure cleaved on any of the first surface, the second surface, the third surface, and the fourth surface is produced, and the cell size is fixed. Perform the structural optimization calculation. Here, the first plane is a crystal plane between the Ga—Zn—O layer and the In—O layer, and (
It is a crystal plane parallel to the 001) plane (or ab plane) (see FIG. 10 (A)). The second plane is the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and is the (001) plane (or a).
It is a crystal plane parallel to the b-plane (see FIG. 10 (A)). The third plane is a crystal plane parallel to the (110) plane (see FIG. 10B). The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (see FIG. 10 (B)).

Under the above conditions, the energy of the structure after cleavage is calculated on each surface. Next, the cleavage energy, which is a measure of the ease of cleavage on each surface, is calculated by dividing the difference between the energy of the structure after cleavage and the energy of the structure in the initial state by the area of the cleavage surface. The energy of the structure is the energy considering the kinetic energy of the electrons and the interaction between the atoms, between the atoms and the electrons, and between the electrons with respect to the atoms and electrons contained in the structure.

As a result of the calculation, the cleavage energy of the first surface is 2.60 J / m ² , the cleavage energy of the second surface is 0.68 J / m ² , the cleavage energy of the third surface is 2.18 J / m ² , and the second. It was found that the cleavage energy of the surface No. 4 was 2.12 J / m ² (see the table below).

_{By this calculation, in the crystal structure of InGaZnO 4} shown in FIG. 10, the cleavage energy in the second plane is the lowest. That is, it can be seen that the surface between the Ga-Zn-O layer and the Ga-Zn-O layer is the most easily cleaved surface (cleavage surface). Therefore, in the present specification, when the term "cleavage surface" is used, it means the second surface which is the most easily cleaved surface.

Since the second plane between the Ga-Zn-O layer and the Ga-Zn-O layer has a cleavage plane, _{the crystal of InGaZnO 4} shown in FIG. 10 (A) is equivalent to the two second planes. Can be separated in various aspects. Therefore, when an ion or the like collides with the target, it is considered that the wafer-shaped unit (which we call a pellet) cleaved on the surface having the lowest cleavage energy pops out as the smallest unit. In that case, _{the pellet of InGaZnO 4} becomes three layers of Ga-Zn-O layer, In-O layer and Ga-Zn-O layer.

Further, the third plane (the crystal plane between the Ga-Zn-O layer and the In-O layer, which is a crystal plane parallel to the (001) plane (or the ab plane)) is more than the first plane (the crystal plane). Since the cleavage energy of the 110) plane (crystal plane parallel to the plane) and the fourth plane (crystal plane parallel to the (100) plane (or bc plane)) is low, the planar shape of the pellet is often triangular or hexagonal. Is suggested.

[Membrane density]
Next, the density of the In-M-Zn oxide film was evaluated. In: Ga: Zn as a target
= 1: 1: 1 polycrystalline In-Ga-Zn oxide was used and nc- by DC sputtering method.
The OS was formed into a film. The pressure is 0.4 Pa, the film formation temperature is room temperature, the power supply power is 100 W, argon and oxygen are used as the film formation gas, and the respective flow rates are 98 sccm for argon and 2 for oxygen.
It was sccm. The density of the obtained In-Ga-Zn oxide was 6.1 g / cm ³ . Here, according to Non-Patent Document 2, _{the density of single crystal InGaZnO 4} is 6.357 g / cm ³
Is. In addition, JCPDS card, No. As described in 00-038-1097, it is known that _{the density of In 2} Ga ₂ ZnO ₇ of a single crystal is 6.494 g / cm ^3. Therefore, it can be seen that the obtained nc-OS film is an excellent film having a high density.

The density of the In—M—Zn oxide film, which is the oxide semiconductor film of one aspect of the present invention, is preferably 85% or more, more preferably 90% or more, for example, the density of single crystals having substantially the same atomic number ratio. 95% or more is more preferable.

Alternatively, when the element M is gallium, the density of the oxide semiconductor film according to one aspect of the present invention is
For example 5.7 g / cm ³ or more 6.49 g / cm ³ or less, preferably 5.75 g / cm ³ or more 6.49 g / cm ³ or less, 5.8 g / cm ³ or more 6.33 g / cm ³ or less More preferably, 5.85 g / cm ³ or more and 6.33 g / cm ³ or less is further preferable.

Here, the substantially same atomic number ratio means that, for example, the difference between the atomic number ratios of each other is within 10%.

Here, for example, the density of a single crystal has two or more In—M—Zn having different atomic number ratios.
It may be estimated from the density of the oxide film. Here, the density of a single crystal having an atomic number ratio of In: M: Zn = 1: 1: 1 is D ₁ , and the density of a single crystal having an atomic number ratio of In: M: Zn = 2: 2: 1 is D. _Let it be 2. In-M- with an atomic ratio of indium, element M and zinc of 1: 1: 0.8
The density of the Zn oxide film is expected to take a value between _{D 1} and D _2. Therefore, as the density of the single crystal, for example, _{the average value of D 1} and D ₂ may be calculated and referred to, _{or the value of either D 1} or D ₂ , for example, a value closer to the atomic number ratio may be referred to. good. When calculating the average value using D ₁ and D ₂ , for example, 0.6 × D ₁ + 0.4 × D ₂ may be set. Atomic number ratio is In: M: Z
_{Let D α be} the density of a single crystal having n = A: B: C, and _{let D β} be the density of a single crystal having an atomic number ratio of In: M: Zn = D: E: F. The density of a single crystal having an atomic number ratio of In: M: Zn = X: Y: Z may be calculated as follows, for example.

First, α so that (αA + βD) :( αB + βE) :( αC + βF) = X: Y: Z
And β are calculated. Next, using the obtained α and β, the density of the single crystal was set to {α / (α + β)} D _α.
It may be calculated as + {β / (α + β)} D _β.

Next, an example of a method for producing an nc-OS film will be described.

Common methods for depositing oxide semiconductor films include, for example, sputtering method, chemical vapor deposition (CVD) method (metalorganic metal deposition (MOCVD) method, atomic layer deposition (ALD) method, or plasma chemistry. Includes vapor deposition (PECVD) method), vacuum deposition (including PECVD) method, pulsed laser deposition (PLD) method and the like.

The nc-OS film is preferably formed by a sputtering method. In—M—Zn oxide can be used as the target used in the sputtering method.

The target preferably has a polycrystalline In—M—Zn oxide. For example, when a target having a polycrystalline In—M—Zn oxide is used, the target has cleavability and may easily form an nc-OS film, which is more preferable.

As a target, an In-M-Zn oxide may be prepared using a mixture of indium oxide, an oxide having an element M, and zinc oxide, but a target having a polycrystalline In-M-Zn oxide may be used. It is preferable to use it.

Further, the nc-OS film may be formed at about room temperature, which is preferable. For example, it may be formed without heating the substrate, which is preferable. Further, for example, the atmosphere in the chamber may be heated preferably at room temperature or higher and 500 ° C. or lower, more preferably 200 ° C. or higher and 400 ° C. or lower.

[About the ratio of the number of atoms]
Here, it is preferable to use, for example, an In—M—Zn oxide film as the oxide semiconductor film according to one aspect of the present invention. The atomic number ratio of In, M and Zn of the In-M-Zn oxide is I
n: M: Zn = x: y: z.

The In—M—Zn oxide film, which is the oxide semiconductor film of one aspect of the present invention, preferably has, for example, an increased proportion of indium.

Further, the smaller the grain boundary of the oxide semiconductor film, the more preferable. Examples of the non-single crystal oxide semiconductor film having a small grain boundary include an nc-OS film and a CAAC-OS film. Further, the oxide semiconductor film may have both an nc-OS film and a CAAC-OS film.

Further, the oxide semiconductor film according to one aspect of the present invention is obtained when nanobeam electron diffraction is performed.
It is preferable to have a region (nc structure) in which the diffraction pattern of the nc-OS film is observed. Further, the oxide semiconductor film according to one aspect of the present invention has a region in which the diffraction pattern of the nc-OS film is observed and a region in which the diffraction pattern of the CAAC-OS film is observed (CAAC structure). You may.

Further, the oxide semiconductor film according to one aspect of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. Further, in the oxide semiconductor film according to one aspect of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, 9
It is preferably 5% or more and 100% or less, preferably 98% or more and 100% or less, and more preferably 99% or more and 100% or less.

The oxide semiconductor film according to one aspect of the present invention may be obtained by laminating a plurality of films. Further, the nc ratio and the CAAC ratio of each of the plurality of films may be different. Further, among the plurality of laminated films, at least one film preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. Further, among the plurality of laminated films, at least one film preferably has a sum of the nc ratio and the CAAC ratio of 80% or more, preferably 90% or more and 100% or less, and 95% or more 1
It is preferably 00% or less, preferably 98% or more and 100% or less, 99.
More preferably, it is% or more and 100% or less.

As shown in FIG. 6, In ₂ O ₃ , Ga ₂ O ₃ and Zn O powders are mixed and 1350.
It is described in Non-Patent Document 1 that when calcined at ° C., the solid solution range is widened by increasing the ratio of zinc. Here, by setting the atomic number ratio of the In—Ga—Zn oxide to a range in which the solid dissolution region can be taken, the CAAC ratio of the oxide semiconductor film of one aspect of the present invention may be further increased. Therefore, by reducing the zinc ratio, the nc ratio of the oxide semiconductor film according to one aspect of the present invention may be increased. The atomic number ratio of indium, element M, and zinc contained in the oxide semiconductor film is defined as indium: element M: zinc = x: y: z. For example, by increasing the ratio of x + y to z, that is, (x + y) / z, the nc ratio may be further increased. Specifically, for example, (x + y)> z is preferable, and (x +)
y) ≧ 1.5z is preferable, and (x + y) ≧ 2z is preferable.

Further, by mixing crystals having a spinel structure with a CAAC-OS film or an nc-OS film,
May form clear grain boundaries or boundaries. Therefore, it is preferable to keep away from the atomic number ratio at which crystals having a spinel structure are more likely to be formed.

Therefore, the In—M—Zn oxide film of the oxide semiconductor film of one aspect of the present invention has In.
The atomic number ratios x, y and z of the elements M and zinc preferably have the ratio of the number of atoms in the region 13 shown in FIG. 4 (A), and the ratio of the number of atoms in the region 14 shown in FIG. 4 (B). It is more preferable to have. Here, the region 13 has the first coordinate K (x: y: z = 8: 14: 7) and the second coordinate R.
(X: y: z = 2: 4: 3), the third coordinate V (x: y: z = 1: 2: 3), and the fourth coordinate S (x: y: z = 1: 0). 1), the fifth coordinate T (x: y: z = 8: 0: 1), and the sixth
The coordinates U (x: y: z = 6: 2: 1) and the first coordinate K are in the region connected by a line segment in order. The region 13 includes a line segment connecting the six points. Further, the area 13 includes all the coordinates. Further, the region 14 has the first coordinate K (x: y: z = 8: 14: 7), the second coordinate R (x: y: z = 2: 4: 3), and the third coordinate. V (x: y: z = 1: 2: 3), the fourth coordinate W (x: y: z = 7: 1: 8), and the fifth coordinate X (x: y: z = 7:). It is within a region in which 1: 1), the sixth coordinate U (x: y: z = 6: 2: 1), and the first coordinate K are connected in order by a line segment. The region 14 includes a line segment connecting the six points. Further, the area 14 includes all coordinates.

Further, when the oxide semiconductor film is formed by the sputtering method, the atomic number ratio of the obtained film is determined.
It may deviate from the target atomic number ratio. Especially for zinc, the ratio of zinc in the obtained film may be smaller than the ratio of target zinc. Specifically, the zinc ratio of the obtained film may be, for example, 40 atomic% or more and 90 atomic% or less of the target zinc ratio.

Here, the relationship between the atomic number ratio of the target used and the atomic number ratio of the obtained film when the In-Ga-Zn oxide was formed by the sputtering method was investigated.

As the film forming conditions, argon and oxygen were used as the film forming gas, and the oxygen flow rate ratio was 33%. Here, the oxygen flow rate ratio is an amount expressed by oxygen flow rate ÷ (oxygen flow rate + argon flow rate) × 100 [%]. The pressure was in the range of 0.4 Pa to 0.7 Pa, the substrate temperature was 200 ° C to 300 ° C, and the power supply power was 0.5 kW (DC).

FIG. 23 shows the relationship between the value of the ratio of the atomic number ratio and the residual rate of zinc when focusing on the two target elements. The numbers in the figure represent the atomic number ratio of the target In: Ga: Zn. Here, the residual rate of zinc will be described. The value obtained by dividing the value of the zinc term in the atomic number ratio of the obtained film by the sum of the values of the indium, gallium and zinc terms of the film is defined as Zn (Film). Further, the value obtained by dividing the value of the zinc term in the target atomic number ratio by the sum of the values of the target indium, gallium and zinc terms is defined as Zn (Target). Here, the residual rate of zinc is defined as a value represented by A = Zn (Film) ÷ Zn (Target) × 100 [%].

The atomic number ratio of indium, gallium, and zinc of the In-Ga-Zn oxide target used is expressed as a: b: c.

FIG. 23 (A) shows the value (c / b) of the ratio of zinc to the target gallium on the horizontal axis, and FIG.
3 (B) is the value of the ratio of gallium to the atomic number ratio of the target indium (b / a) on the horizontal axis.
), FIG. 23 (C) shows the value (c / a) of the ratio of zinc to the target indium on the horizontal axis. The vertical axis of each indicates the zinc residual rate A.

Here, from FIG. 23, the residual ratio of zinc in the film obtained by the sputtering method is approximately 5.
It can be seen that it is 0% or more and 90% or less. Moreover, it can be said that indium and gallium do not change significantly from the target atomic number ratio as compared with zinc. Further, when the value of the ratio of zinc to the target gallium (c / b) is, for example, the zinc residual ratio A is about 66%.
In the case of 2, it is about 74%, and in the case of 3, it is about 83%.

Further, from FIG. 23 (A), it can be seen that there is a good correlation between the value of the ratio of zinc to the target gallium (c / b) and the residual rate of zinc. That is, the smaller the amount of zinc with respect to gallium, the lower the residual rate.

In view of the above, in order to obtain the oxide semiconductor film of the region 13 shown in FIG. 4A by using the sputtering method, for example, the value of the target zinc ratio to the value of the zinc ratio of the target film. Is preferably 1.7 times or more, more preferably 1.5 times or more. Therefore, the target indium, gallium and zinc preferably have the atomic number ratio of the region 15 shown in FIG. Here, the region 15 has the first coordinate K (a: b: c = 8: 14: 7) and the second coordinate R (a).
: B: c = 2: 4: 3), the third coordinate Y (a: b: c = 1: 2: 5.1), and the fourth coordinate Z (a: b: c = 1: 0). 1.7) and the fifth coordinate T (a: b: c = 8: 0: 1),
It is within a region in which the sixth coordinate U (a: b: c = 6: 2: 1) and the first coordinate K are sequentially connected by a line segment. The region 15 includes a line segment connecting the six points. Region 15 includes all coordinates.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 3)
In this embodiment, an example of a transistor using an oxide semiconductor film, which is one aspect of the present invention, will be described.

[Transistor example 1]
An example of a transistor using an oxide semiconductor film will be described with reference to FIG.

FIG. 12A shows a top view of the transistor 100. Further, FIG. 12 (B) is shown in FIG. 12 (A).
) Shows the cross section at the alternate long and short dash line XX', and FIG. 12C shows the cross section at the alternate long and short dash line YY'. The transistor 100 shown in FIG. 12 includes a substrate 50, an insulating film 51 in contact with the upper surface of the substrate 50, an insulating film 114 in contact with the upper surface of the insulating film 51, a semiconductor layer 101 in contact with the upper surface of the insulating film 114, and a conductive layer 104a. And the conductive layer 104b, the gate insulating film 102 on the semiconductor layer 101, and the gate electrode 103 that overlaps with the semiconductor layer 101 via the gate insulating film 102.
Have. Further, an insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100. Further, the transistor 100 may have a conductive layer 105. Further, it is not necessary to provide an insulating film between the substrate 50 and the insulating film 114.

The semiconductor layer 101 may be formed of a single layer, and is more preferably formed of a laminated structure of the first layer to the third layer. The second layer is provided in contact with the first layer, and the third layer is provided in contact with the second layer. Here, in the transistor of one aspect of the present invention, the first layer and the third layer have a region in which a current is less likely to flow as compared with the second layer. Therefore, the first layer and the third layer may be referred to as an insulator layer. Therefore, as in the example shown in FIG. 12, the semiconductor layer 101
Is preferably formed by a laminated structure of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c. Further, the structure may not have either the insulator layer 101a or the insulator layer 101c. In the example shown in FIG. 12, the semiconductor layer 101b is the insulator layer 101.
It touches the upper surface of a. Further, the conductive layer 104a and the conductive layer 104b are in contact with the upper surface of the semiconductor layer 101b and are separated from each other in a region overlapping the semiconductor layer 101b. Further, the insulator layer 101c is in contact with the upper surface of the semiconductor layer 101b. Further, the gate insulating film 102 is in contact with the upper surface of the insulator layer 101c. Further, the gate electrode 103 overlaps with the semiconductor layer 101b via the gate insulating film 102 and the insulator layer 101c.

Further, an insulating film 112 and an insulating film 113 are provided so as to cover the transistor 100.
The insulating film 112 and the insulating film 113 will be described in detail in the embodiments described later.

The conductive layer 104a and the conductive layer 104b have a function as a source electrode or a drain electrode. Further, a voltage lower or higher than that of the source electrode may be applied to the conductive layer 105 to change the threshold voltage of the transistor in the positive direction or the negative direction. By fluctuating the threshold voltage of the transistor in the positive direction, it may be possible to realize normally off in which the transistor is in a non-conducting state (off state) even if the gate voltage is 0V. The voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage may be connected to the conductive layer 105. Further, the conductive layer 105 may be connected to the gate electrode 103.

The upper surface of the insulating film 114 is CMP (Chemical Mechanical Polis).
It is preferable that the material is flattened by a flattening treatment using the hing) method or the like.

The insulating film 114 preferably contains an oxide. In particular, it is preferable to contain an oxide material in which some oxygen is desorbed by heating. Preferably, oxides containing more oxygen than oxygen satisfying the stoichiometric composition are used. In an oxide film containing more oxygen than oxygen satisfying a stoichiometric composition, some oxygen is desorbed by heating. The oxygen desorbed from the insulating film 114 is supplied to the semiconductor layer 101, which is an oxide semiconductor, and oxygen deficiency in the oxide semiconductor can be reduced. As a result, fluctuations in the electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than oxygen satisfying a stoichiometric composition has, for example, a temperature desorption gas spectroscopy analysis (TDS analysis) in which the amount of oxygen desorbed in terms of oxygen atoms is large. 1.0 x 10 ^1
An oxide film having 8 atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ^{3 or more.} The surface temperature of the film during the TDS analysis is 100 ° C. or higher 7
The range of 00 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower is preferable.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxide nitride. Alternatively, a metal oxide can be used. As the metal oxide, aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide and the like can be used. In the present specification, silicon oxide refers to a material having a composition higher in oxygen content than nitrogen, and silicon nitride oxide refers to a material having a composition higher in nitrogen content than oxygen. Is shown.

Further, in order to make the insulating film 114 contain oxygen excessively, oxygen may be introduced into the insulating film 114 to form a region containing oxygen excessively. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, a plasma treatment, or the like can be used.

The semiconductor layer 101 is configured to include an oxide semiconductor. As the oxide semiconductor, it is preferable to use a semiconductor material having a wider bandgap and a smaller carrier density than silicon because the current in the off state of the transistor can be reduced. Further, since the semiconductor layer 101 is configured to include an oxide semiconductor, fluctuations in electrical characteristics are suppressed, and a highly reliable transistor can be realized.

Here, as the semiconductor layer 101, for example, the oxide semiconductor shown in the first embodiment or the second embodiment can be used.

In the present specification and the like, when it is substantially intrinsic, the carrier density of the oxide semiconductor layer is ^{less than 1 × 10 17} / cm ^{3 or} less than 1 × 10 ¹⁵ / cm ³ or 1 × 10 ¹³ / cm ^3.
Is less than. By making the oxide semiconductor layer highly pure and intrinsic, it is possible to impart stable electrical characteristics to the transistor.

Here, a case where a laminated film of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c is used as the semiconductor layer 101 will be described in detail. As the semiconductor layer 101b, it is preferable to use an oxide having a higher electron affinity than the insulator layer 101a and the insulator layer 101c. For example, the semiconductor layer 101b has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0. Use an oxide as large as 4 eV or less. The electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.

By using an oxide having an electron affinity higher than that of the insulator layer 101a and the insulator layer 101c as the semiconductor layer 101b, when an electric field is applied to the gate electrode, the insulator layer 101a,
Of the semiconductor layer 101b and the insulator layer 101c, a channel is formed in the semiconductor layer 101b having a large electron affinity. Here, by forming the channel in the semiconductor layer 101b, for example, the channel forming region is separated from the interface with the gate insulating film 102, so that the influence of scattering at the interface with the gate insulating film can be reduced. Therefore, the electric field effect mobility of the transistor can be increased. Here, as described later, the semiconductor layer 101b and the insulator layer 101c share the same constituent elements, so that interfacial scattering hardly occurs.

When a silicon oxide film, a silicon nitride film, a silicon nitride film, a silicon nitride film, or the like is used as the gate insulating film, silicon contained in the gate insulating film may be mixed in the oxide semiconductor film. When the oxide semiconductor film contains silicon, the crystallinity of the oxide semiconductor film may be lowered, the carrier mobility may be lowered, and the like. Therefore, in order to reduce the impurity concentration of the semiconductor layer 101b on which the channel is formed, for example, the silicon concentration, the semiconductor layer 10
It is preferable to provide an insulator layer 101c between 1b and the gate insulating film. For the same reason, it is preferable to provide an insulator layer 101a between the semiconductor layer 101b and the insulating film 114 in order to reduce the influence of impurity diffusion from the insulating film 114.

As the semiconductor layer 101b, for example, an oxide semiconductor film having indium, element M, and zinc may be used. For example, it is preferable to use the oxide semiconductor film shown in the first embodiment or the second embodiment.

For the semiconductor layer 101b, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.7 eV or less, and more preferably 2.8 eV or more and 3.3 eV or less.

Next, the insulator layer 101a and the insulator layer 101c will be described. For example, insulator layer 1
The 01a and the insulator layer 101c are one or more elements other than oxygen constituting the semiconductor layer 101b.
Or it is an oxide composed of two or more kinds. Since the insulator layer 101a and the insulator layer 101c are composed of one or more or two or more elements other than oxygen constituting the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b and the semiconductor layer 101b Insulator layer 1
At the interface with 01c, the interface state is unlikely to be formed.

Here, the band structure is shown in FIG. In FIG. 11, the vacuum level (vacuum le) is shown.
Notated as vel. ), The energy at the lower end of the conduction band (denoted as Ec) and the energy at the upper end of the valence band (denoted as Ev) of each layer.

Here, between the insulator layer 101a and the semiconductor layer 101b, there may be a mixed region of the insulator layer 101a and the semiconductor layer 101b. Further, the semiconductor layer 101b and the insulator layer 101
There may be a mixed region of the semiconductor layer 101b and the insulator layer 101c between the c and the c.
The interface state density is low in the mixed region. Therefore, the insulator layer 101a and the semiconductor layer 101b
The laminate of the insulator layer 101c and the insulator layer 101c has a band structure in which the energy continuously changes (also referred to as continuous bonding) in the vicinity of the respective interfaces.

At this time, the electrons are not in the insulator layer 101a and the insulator layer 101c, but in the semiconductor layer 1
It mainly moves in 01b. As described above, the insulator layer 101a and the semiconductor layer 101b
By lowering the interface state density at the interface between the semiconductor layer 101b and the interface state density at the interface between the semiconductor layer 101b and the insulator layer 101c, the movement of electrons in the semiconductor layer 101b is less likely to be hindered, and the on-current of the transistor is reduced. Can be raised.

Although FIG. 11 shows a case where the Ec of the insulator layer 101a and the insulator layer 101c are the same, they may be different from each other. For example, Ec of the insulator layer 101c may have higher energy than that of the insulator layer 101a.

As shown in FIG. 12B, the side surfaces of the semiconductor layer 101b are the conductive layer 104a and the conductive layer 1
It comes into contact with 04b. Further, as shown in FIG. 12 (C), due to the electric field of the gate electrode 103,
The semiconductor layer 101b can be electrically surrounded (the structure of the transistor that electrically surrounds the semiconductor by the electric field of the conductor is described as a rounded channel (s-c).
hannel) It is called a structure. ). By providing the gate electrode 103 so as to face the upper surface and the side surface of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the upper surface of the semiconductor layer 101b but also in the whole (bulk). In the s-channel structure, a large current can be passed between the source and drain of the transistor, and the current (on-current) at the time of conduction can be increased.

Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device having the transistor can be a high-density semiconductor device with a high degree of integration. for example,
The transistor has a region having a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, further preferably 30 nm or less, more preferably 30 nm or less. It has a region of 20 nm or less. In particular, the smaller the channel width, the wider the region where the channel is formed inside the semiconductor layer 101b, so that the smaller the channel width, the greater the contribution to the on-current.

For example, In—M—Zn oxide can be used as the insulator layer 101a and the insulator layer 101c.

Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, for example, the insulator layer 101c may contain indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

Further, the insulator layer 101c more preferably contains gallium oxide. Insulator layer 101
If gallium oxide is included in c, a lower off-current may be realized.

Further, it is preferable to use an nc-OS film or a CAAC-OS film for the insulator layer 101a and the insulator layer 101c. Here, the nc ratio of the insulator layer 101a and the insulator layer 101c and CA
By increasing the AC ratio, for example, defects can be reduced. Further, for example, the region having spinel-type crystals can be reduced. Also, for example, carrier scattering can be reduced. Further, for example, a film having a high blocking ability against impurities can be obtained. Further, it is possible to suppress the mixing of impurities into the semiconductor layer 101b, and it is possible to reduce the impurity concentration of the semiconductor layer 101b.

The nc ratio of the insulator layer 101a and the insulator layer 101c is preferably, for example, 10% or more.
30% or more is preferable, 50% or more is preferable, 80% or more is preferable, 90% or more is preferable, and 95% or more is preferable.

Here, the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are In—M—Zn.
Consider the case of an oxide. In having the insulator layer 101a, the atomic ratio of the element M and Zn and _{x a, y} a, and _{z a.} Similarly, In, element M and Zn contained in the semiconductor layer 101b.
_{Let x b} , y _b and z _b be the atomic number ratios of. Similarly, let the atomic number ratios of In, element M, and Zn contained in the insulator layer 101c be x _c , y _c, and z _c . Each preferable value will be described below.

x _b , y _b, and z _b are regions 11, regions 12, and regions 13 shown in FIGS. 1, 2 (A), and 4.
It is preferable to take any range of the region 14 and the region 14.

The insulator layer 101a and the insulator layer 101c preferably do not contain or have few spinel-type crystal structures. Therefore, x _a : y _a : z _a and x _c : y _c : z _c are, for example, FIG.
It is preferable that the value is within the range of the region 11 and the electron affinity is smaller than that of the semiconductor layer 101b.

Here, in order to make the electron affinity of the semiconductor layer 101b larger than that of the insulator layer 101a and the insulator layer 101c, for example, it is preferable to increase the indium content of the semiconductor layer 101b more than that of the insulator layer 101a and the insulator layer 101c. ..

For example, x _b / (x _b + y _b + z _b )> x _a / (x _a + y _a + z _a ), and x _b / (x)
It is preferable to satisfy _b + y _b + z _b )> x _c / (x _c + y _c + z _c).

For example, preferably _{x a / (x a + y} a) <0.5, more preferably _x a / (x
_a + _{y a)} <0.33, more preferably from _{x a / (x a + y} a) <0.25. Further, x _b / (x _b + y _b ) ≧ 0.25 is preferable, and x _b / (more preferably.
x _b + y _b ) ≧ 0.34. Further, it is preferably x _c / (x _c + y _c ) <0.5, more preferably x _c / (x _c + y _c ) <0.33, and further preferably x _c / (x _c).
+ _Y c) <0.25.

Alternatively, x _a , y _a , z _a , and x _c , y _c , z _c preferably have a ratio of the number of atoms in the region 16 shown in FIG. 2 (B). Here, the region 16 has the first coordinate K (x: y: z = 8:
14: 7), the second coordinate R (x: y: z = 2: 4: 3), and the third coordinate L (x: y: z).
= 2: 5: 7), the fourth coordinate M (x: y: z = 51: 149: 300), the fifth coordinate B (x: y: z = 1: 4:10), and the first Coordinate C of 6 (x: y: z = 1: 1: 4) and 7th
This is a region in which the coordinates A (x: y: z = 2: 2: 1) and the first coordinate K are connected in order by a line segment. The area 16 includes all coordinates.

When the transistor has an s-channel structure, a channel is formed in the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, the semiconductor layer 101b having a region having a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more may be used. However, since the productivity of the semiconductor device may decrease, for example, the semiconductor layer 101b having a thickness region of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used.

Further, in order to increase the on-current of the transistor, it is preferable that the thickness of the insulator layer 101c is small. For example, less than 10 nm, preferably 5 nm or less, more preferably 3 nm.
The insulator layer 101c having the following regions may be used. On the other hand, the insulator layer 101c is an element other than oxygen (hydrogen, which constitutes an insulator adjacent to the semiconductor layer 101b on which a channel is formed.
It has a function to block silicon etc. from entering. Therefore, the insulator layer 10
1c preferably has a certain thickness. For example, the insulator layer 101c having a region having a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more may be used. Further, the insulator layer 101c preferably has a property of blocking oxygen in order to suppress the outward diffusion of oxygen released from the gate insulating film 102 or the like.

Further, in order to increase the reliability, it is preferable that the insulator layer 101a is thick and the insulator layer 101c is thin. For example, 10 nm or more, preferably 20 nm or more, more preferably 4
The insulator layer 101a having a region having a thickness of 0 nm or more, more preferably 60 nm or more may be used. By increasing the thickness of the insulator layer 101a, the adjacent insulator and the insulator layer 101 can be made thicker.
The distance from the interface with a to the semiconductor layer 101b on which the channel is formed can be increased.
However, since the productivity of the semiconductor device may decrease, for example, the insulator layer 1 having a region having a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.
It may be 01a.

When a large amount of hydrogen or water is contained in the oxide semiconductor film, a donor level due to hydrogen may be formed. Due to the formation of the donor level, the threshold value of the transistor may shift in the negative direction. Therefore, it is preferable to perform a dehydration treatment (dehydrogenation treatment) after the formation of the oxide semiconductor film to remove hydrogen or water to obtain high purity so that impurities are not contained as much as possible.

The dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film may also reduce oxygen at the same time. Therefore, it is preferable to supply oxygen after the dehydration treatment to compensate for the oxygen deficiency of the oxide semiconductor film. In the present specification and the like, supplying oxygen to the oxide semiconductor film may be referred to as oxygenation treatment. Alternatively, increasing the proportion of oxygen contained in the oxide semiconductor film to be higher than the stoichiometric composition may be referred to as hyperoxygenation treatment.

In this way, by removing hydrogen or water by dehydration treatment and compensating for oxygen deficiency by oxygenation treatment, i-type (intrinsic) or i-type, which is as close as possible to i-type, is substantially i.
A type (intrinsic) oxide semiconductor film can be realized. In addition, substantially true means that the number of carriers derived from the donor in the oxide semiconductor film is extremely small (close to zero), and the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less. It means that it is 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, and 1 × 10 ¹³ / cm ^{3 or less.}

A transistor provided with an i-type or substantially i-type oxide semiconductor film can realize extremely excellent off-current. For example, the off-current of a transistor using an oxide semiconductor film is 1 × 10 ^-18 A or less, preferably 1 × 10 ^-21 A or less, more preferably 1 × 10 ^-24 A at room temperature (about 25 ° C.). Below, or at 85 ° C., it can be 1 × 10 ^-15 A or less, preferably 1 × 10 ^-18 A or less, and more preferably 1 × 10 ^-21 A or less. Here, the off current refers to the drain current when the transistor is in the off state. Further, the transistor off state means a state in which the gate voltage is sufficiently smaller than the threshold value in the case of an n-channel type transistor. Specifically, if the gate voltage is 1 V or more, 2 V or more, or 3 V or more smaller than the threshold value, the transistor is turned off.

One of the conductive layer 104a and the conductive layer 104b functions as a source electrode, and the other functions as a drain electrode.

The conductive layer 104a and the conductive layer 104b have a single-layer structure or a laminated structure of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component. Used as. for example,
Single layer structure of aluminum film containing silicon, double layer structure of laminating aluminum film on titanium film, double layer structure of laminating aluminum film on tungsten film, laminating copper film on copper-magnesium-aluminum alloy film Two-layer structure, two-layer structure in which a copper film is laminated on a titanium film, two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and aluminum laminated on the titanium film or the titanium nitride film. A three-layer structure in which a film or a copper film is laminated and a titanium film or a titanium nitride film is formed on the film, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film overlaid on the molybdenum film or the molybdenum nitride film. There is a three-layer structure or the like in which a molybdenum film or a molybdenum nitride film is formed by laminating them.
A transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

The gate insulating film 102 includes, for example, silicon oxide, silicon nitriding, silicon nitride, and the like.
Aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, silicon nitride or the like may be used, and the layers are laminated or provided in a single layer.

Further, as the gate insulating film 102, a hafnium silicate (HfSiO _x), hafnium silicate to which nitrogen is added _{(HfSi x O y N z)} , hafnium aluminate to which nitrogen is added _{(HfAl x O y N z)} , yttrium oxide High-k materials such as may be used.

Further, as the gate insulating film 102, an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide. , Silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride, and other nitride insulating films, or a mixed material thereof.

Further, as the gate insulating film 102, it is preferable to use an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition, similarly to the insulating film 114.

When a specific material is used for the gate insulating film, electrons can be captured by the gate insulating film under specific conditions to shift the threshold voltage in the positive direction. For example, a material with a large electron capture level such as hafnium oxide, aluminum oxide, and tantalum oxide is used for a part of the gate insulating film, such as a laminated film of silicon oxide and hafnium oxide, and a higher temperature (use of a semiconductor device) is used. Under a temperature higher than the temperature or storage temperature, or 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the gate electrode is higher than the potential of the source electrode or drain electrode. By maintaining for 1 second or longer, typically 1 minute or longer, electrons move from the semiconductor layer toward the gate electrode, and some of them are captured at the electron capture level.

The gate electrode 103 is formed by using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-mentioned metal as a component, an alloy obtained by combining the above-mentioned metals, and the like. Can be done. Further, a metal selected from any one or more of manganese and zirconium may be used. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, and a silicide such as nickel silicide may be used. Further, the gate electrode 103 may have a single-layer structure or a laminated structure having two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film on which a tungsten film is laminated. A layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film, and a titanium film is further formed on the titanium film, etc. be. Also, on aluminum
An alloy film or a nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be combined may be used.

Further, the gate electrode 103 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. , A translucent conductive material such as indium tin oxide to which silicon oxide is added can also be applied. Further, it is also possible to form a laminated structure of the conductive material having the translucency and the metal.

Further, between the gate electrode 103 and the gate insulating film 102, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, and an In-Zn system. Oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (I)
nN, ZnN, etc.) may be provided. Since these films have a work function of 5 eV or more, preferably 5.5 eV or more, and have a value larger than the electron affinity of the oxide semiconductor, the threshold voltage of the transistor using the oxide semiconductor is set in the positive direction. It can be shifted, and a switching element with so-called normally-off characteristics can be realized. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration higher than that of the semiconductor layer 101, specifically, 7 atomic% or more is used.

The above is the description of the transistor 100.

The channel length is, for example, in the top view of the transistor, in the region where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or in the region where the channel is formed. , Source (source region or source electrode)
The distance between and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, the source and the drain facing each other in the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or the region where the channel is formed. The length of the part that is present. In one transistor, the channel width does not always take the same value in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is set to any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). ) And may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, is referred to as “enclosure channel width (SCW)”. : Surrounded Channel
It may be called "Width)". Further, in the present specification, when simply referred to as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term "channel width" may refer to an effective channel width.
The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image or the like and analyzing the image. can.

When calculating the electric field effect mobility of a transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from that calculated using the effective channel width.

[Transistor example 2]
An example of a structure of a transistor using an oxide semiconductor film, which is one aspect of the present invention, having a structure different from that of FIG. 12 will be described with reference to FIG. FIG. 13 (A) is a top view of the transistor 100 which is a semiconductor device of one aspect of the present invention, and FIG. 13 (B) is a cross section of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 13 (A). Corresponding to the figure, FIG. 13 (C) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 13 (A).

The transistor 100 electrically attaches to the gate electrode 203a that functions as a gate electrode on the substrate 50, the gate insulating film 202 on the substrate 50 and the gate electrode 203a, the semiconductor layer 201 on the gate insulating film 202, and the semiconductor layer 201. It has a conductive layer 204a and a conductive layer 204b that function as a connected source electrode and a drain electrode. Also, the transistor 100
Above, more specifically, the insulating film 21 on the conductive layer 204a, the conductive layer 204b, and the semiconductor layer 201.
4. The insulating film 216 and the insulating film 218 are laminated and provided in this order.

Next, the components included in the transistor of the present embodiment will be described.

As the gate electrode 203a that functions as the gate electrode of the transistor 100, the description of the gate electrode 103 may be referred to.

As the gate insulating film 202 that functions as the gate insulating film of the transistor 100, the description of the gate insulating film 102 may be referred to. Further, a laminated film having two or more layers may be used as the gate insulating film 202. For example, as shown in FIG. 13, a two-layer structure of the gate insulating film 202a and the gate insulating film 202b may be used. In that case, for example, the lower layer, here the gate insulating film 20
A film having a function as a blocking film that suppresses the permeation of oxygen may be used for 2a. As a film having a function as a blocking film, for example, a barrier membrane 111 or the like described later may be referred to.

As the semiconductor layer 201, the oxide semiconductor film shown in the first embodiment or the second embodiment may be used. Further, as the semiconductor layer 201, the description of the semiconductor layer 101 may be referred to. Further, the semiconductor layer 201 may be a laminated film having two or more layers.

The insulating film 214, the insulating film 216, and the insulating film 218 have a function as a protective insulating film of the transistor 100. The insulating film 214 also functions as a damage mitigating film for the semiconductor layer 201 when the insulating film 216 is formed.

It is more preferable that the insulating film 214 and the insulating film 216 have a region containing oxygen in excess of the stoichiometric composition (oxygen excess region) like the insulating film 114 described above.

Further, the insulating film 214 preferably has a small amount of defects, and typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 3 × 10 ¹⁷ spins / cm by ESR measurement. It is preferably ^{3 or less.} If the defect density contained in the insulating film 214 is high, oxygen is bonded to the defects, and the amount of oxygen permeated by the insulating film 214 is reduced.

In the insulating film 214, all the oxygen that has entered the insulating film 214 from the outside is the insulating film 21.
There is also oxygen that does not move to the outside of 4 and stays in the insulating film 214. Further, when oxygen enters the insulating film 214 and the oxygen contained in the insulating film 214 moves to the outside of the insulating film 214, oxygen may move in the insulating film 214. When an oxide insulating film capable of transmitting oxygen is formed as the insulating film 214, oxygen desorbed from the insulating film 216 provided on the insulating film 214 is moved to the semiconductor layer 201 via the insulating film 214. Can be done.

_{Further, the insulating film 214 has energy (Ev_os} ) at the upper end of the valence band of the oxide semiconductor film.
It can be formed by using an oxide insulating film having a low level density of nitrogen oxides between _{the energy (E c_os} ) at the lower end of the conduction band. As an _{oxide insulating film with a low level density of nitrogen oxides between E v_os} and E _{c_os,} a silicon oxide film with a small amount of nitrogen oxides released, an aluminum oxide film with a small amount of nitrogen oxides released, etc. Can be used.

A silicon oxide film with a small amount of nitrogen oxides released is a film in which the amount of ammonia molecules released is larger than the amount of nitrogen oxides released in the thermal desorption gas analysis method, and is typically a film of ammonia molecules. The amount released is 1 × 10 ¹⁸ pieces / cm ³ or more and 5 × 10 ¹⁹ pieces / cm ³ or less. The amount of ammonia molecules released is preferably 5 when the surface temperature of the film is 50 ° C. or higher and 650 ° C. or lower.
The amount released by heat treatment at 0 ° C. or higher and 550 ° C. or lower.

Nitrogen oxides (NO _x , x are greater than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO, form a level on the insulating film 214 or the like. The level is the semiconductor layer 20.
It is located within the energy gap of 1. Therefore, when nitrogen oxides diffuse to the interface between the insulating film 214 and the semiconductor layer 201, the level may trap electrons on the insulating film 214 side. As a result, the trapped electrons stay in the vicinity of the interface between the insulating film 214 and the semiconductor layer 201, so that the threshold voltage of the transistor is shifted in the positive direction.

Nitrogen oxides also react with ammonia and oxygen in the heat treatment. Insulating film 214
Since the nitrogen oxides contained in the insulating film 216 react with the ammonia contained in the insulating film 216 in the heat treatment, the nitrogen oxides contained in the insulating film 214 are reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 214 and the semiconductor layer 201.

The insulating film 214 has a function of protecting the back channel region of the semiconductor layer 201 by coming into contact with the semiconductor layer 201 on the opposite side (hereinafter, referred to as a back channel region) of the region where the channel is formed in the semiconductor layer 201. Has.

_{By using an oxide insulating film having a low level density of nitrogen oxides between E v_os} and E _{c_os} as the insulating film 214, it is possible to reduce the shift of the threshold voltage of the transistor, and it is possible to reduce the shift of the threshold voltage of the transistor. Fluctuations in electrical characteristics can be reduced.

Further, the oxide insulating film having a low level density of nitrogen oxides between _{E v_os} and E _{c_os is S.}
The nitrogen concentration measured by IMS is 6 × 10 ²⁰ atoms / cm ³ or less.

Further, the insulating film 216 preferably has a small amount of defects, and typically, the spin density of the signal appearing at g = 2.001 derived from the dangling bond of silicon is 1.5 × 10 ^{18 by ESR measurement.} Less than spins / cm ³ and even 1 x 10 ¹⁸ spins / cm ³
The following is preferable. The insulating film 216 has a semiconductor layer 2 as compared with the insulating film 214.
Since it is far from 01, the defect density may be higher than that of the insulating film 214.

Further, the transistor 100 may have the structure shown in FIGS. 14 and 15. Here, the transistor 100 shown in FIG. 13 was a channel etch type transistor, but the transistor 100 shown in FIGS. 14 and 15 is a channel protection type transistor.

FIG. 14 (A) is a top view of the transistor 100 which is the semiconductor device of one aspect of the present invention, and FIG. 14 (B) is a cross section of the cut surface between the one-point chain lines X1-X2 shown in FIG. 14 (A). Corresponding to the figure, FIG. 14 (C) corresponds to a cross-sectional view of a cut surface between the one-point chain lines Y1-Y2 shown in FIG. 14 (A). The transistor 100 shown in FIG. 14 is a semiconductor that overlaps the gate electrode 203a via the gate electrode 203a provided on the substrate 50, the gate insulating film 202 formed on the substrate 50 and the gate electrode 203a, and the gate insulating film 202. The semiconductor layer 20 at the openings 141a and 141b of the layer 201, the gate insulating film 202, the insulating film 214 on the semiconductor layer 201, the insulating film 216 on the insulating film 214, and the insulating film 214 and the insulating film 216.
It has a pair of conductive layers 204a and a conductive layer 204b in contact with 1. Also, transistor 1
An insulating film 218 may be provided on the conductive layer 204a, the conductive layer 204b, and the insulating film 216 in more detail.

FIG. 15 (A) is a top view of the transistor 100 which is a semiconductor device of one aspect of the present invention, and FIG. 15 (B) is a cross section of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 15 (A). Corresponding to the figure, FIG. 15 (C) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 15 (A). The transistor 100 shown in FIG. 15 is the transistor 10 shown in FIG.
The shapes of 0 and the insulating films 214 and 216 are different. Specifically, the transistor 1 shown in FIG.
The insulating films 214 and 216 of 00 are provided in an island shape on the channel region of the semiconductor layer 101.
Other configurations are the same as those of the transistor 100 shown in FIG. 14, and the same effect is obtained.

In each of the transistors 100 shown in FIGS. 14 and 15, since the semiconductor layer 201 is covered with the insulating film 214 and the insulating film 216 when the pair of conductive layers 204a and the conductive layer 204b are formed, the pair of conductive layers 204a And the etching forming the conductive layer 204b does not damage the semiconductor layer 201. Further, by using the insulating film 214 and the insulating film 216 as an oxide insulating film having nitrogen and a small amount of defects, fluctuations in electrical characteristics can be suppressed and a transistor with improved reliability can be manufactured. can.

Further, as shown in FIG. 16, the transistor 100 may have an electrode 203b on the insulating film 218. 16 (A) is a top view of the transistor 100, which is a semiconductor device according to one aspect of the present invention, and FIG. 16 (B) is a cross section of a cut surface between the alternate long and short dash lines X1-X2 shown in FIG. 16 (A). Corresponding to the figure, FIG. 16 (C) corresponds to a cross-sectional view of a cut surface between the alternate long and short dash lines Y1-Y2 shown in FIG. 16 (A). In FIG. 16, the electrodes 203b are the insulating film 214 and the insulating film 2.
Although the configuration is shown in which the gate electrode 203a is connected to the gate electrode 203a via the opening 142c and the opening 142d provided in 16, the electrode 203b and the gate electrode 203a may not be connected.
When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the respective electrodes.

As shown in FIG. 16, the side surface of the semiconductor layer 201 and the electrode 203b in the channel width direction.
Further, in the channel width direction, the gate electrode 203a and the electrode 203b surround the semiconductor layer 201 via the gate insulating film 202, the insulating film 214, the insulating film 216, and the insulating film 218. In the semiconductor layer 201, the region in which the carrier flows is not only the interface between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201, but also the semiconductor layer 20.
Since carriers also flow inside the transistor 100, the amount of carrier movement in the transistor 100 increases. As a result, the on-current of the transistor 100 increases and the field effect mobility increases. Further, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201, or the end portion including the side surface and the vicinity thereof, it is possible to suppress the generation of parasitic channels on the side surface or the end portion of the semiconductor layer 201.

Further, in FIG. 16, as an example of the semiconductor layer 201, the semiconductor layer 201b is placed on the semiconductor layer 201a.
The configuration in which is laminated is shown. Here, for example, in the semiconductor layer 201b, the energy at the lower end of the conduction band is closer to the vacuum level than the semiconductor layer 201a, and typically, the energy at the lower end of the conduction band of the semiconductor layer 201b and the conduction band of the semiconductor layer 201a. The difference from the energy at the lower end is 0.05 eV
0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less,
It is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more, 0.07 e.
V or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.
It is 5 eV or less, or 0.4 eV or less.

As the semiconductor layer 201a, the semiconductor layer 101b shown in the third embodiment may be referred to. For example, a preferable range of atomic number ratios of indium, element M and zinc contained in the semiconductor layer 101b may be referred to. Further, as the semiconductor layer 201b, the insulator layer 1 shown in the third embodiment
You may refer to 01c. For example, a preferable range of atomic number ratios of indium, element M and zinc contained in the insulator layer 101c may be referred to.

[Transistor modification example]
Modification examples of the transistor 100 are shown in FIGS. 30 to 33. For example, the transistor 100 may have the structure shown in FIG. In FIG. 30, the shapes of the conductive layer 104a and the conductive layer 104b are different from those in FIG. Note that FIG. 30 (B) passes through the alternate long and short dash line AB shown in FIG. 30 (A), and is shown in FIG.
The cross section of the plane perpendicular to 0 (A) is shown.

Further, the transistor 100 may have the structure shown in FIG. In FIG. 12, the insulator layer 101
While c is in contact with the upper surfaces of the conductive layer 104a and the conductive layer 104b, in FIG. 31, the conductive layer 1
It is in contact with the lower surfaces of 04a and the conductive layer 104b. Note that FIG. 31 (B) shows a cross section of a plane that passes through the alternate long and short dash line AB shown in FIG. 31 (A) and is perpendicular to FIG. 31 (A). With such a configuration, when the films constituting the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are formed, the films can be continuously formed without being exposed to the atmosphere. , Each interface defect can be reduced.

Further, the transistor 100 may have the structure shown in FIG. 32. Note that FIG. 32 (B) shows a cross section of a plane that passes through the alternate long and short dash line AB shown in FIG. 32 (A) and is perpendicular to FIG. 32 (A). FIG. 32
Is different from FIG. 12 in that it does not have the conductive layer 104a and the conductive layer 104b. Here, FIG. 32
As shown in (C), the transistor 100 may have a low resistance layer 171a and a low resistance layer 171b. The low resistance layer 171a and the low resistance layer 171b preferably function as a source region or a drain region. Further, impurities may be added to the low resistance layer 171a and the low resistance layer 171b. The resistance of the semiconductor layer 101 can be lowered by adding impurities. The impurities to be added include, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, ittrium, etc.
It is preferable to add one or more selected from zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. The low resistance layer 171a and the low resistance layer 171b contain, for example, 5 × 10 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / c, of the above-mentioned impurity elements in the semiconductor layer 101.
m ³ or more, more preferably 2 × 10 ²⁰ atoms / cm ³ or more, more preferably 5 ×
It is an area containing 10 ²⁰ atoms / cm ^{3 or more.} 32 (D) is an enlarged view of the region 324 of FIG. 32 (C).

In some cases, impurities such as unnecessary hydrogen can be trapped in such a region having low resistance. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region can be lowered, and good characteristics can be obtained as the characteristics of the transistor 100.

Further, the transistor 100 may have the structure shown in FIG. 33. FIG. 33 shows the insulator layer 101.
The shapes of c and the gate insulating film 102 are different from those in FIG. 32. Note that FIG. 33 (B) is shown in FIG. 33 (A).
A cross section of a plane passing through the alternate long and short dash line AB shown in FIG. 33 (A) is shown.

Further, in the structures shown in FIGS. 30 to 33, the insulator layer 101 is in contact with the semiconductor layer 101b.
Although the configuration in which a and the insulator layer 101c are provided has been described, the insulator layer 101a or the insulator layer 1 has been described.
A configuration may be configured in which one or both of 01c is not provided.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 4)
In the present embodiment, an example of the display device having the transistor illustrated in the previous embodiment will be described below with reference to FIGS. 34 to 36.

FIG. 34 is a top view showing an example of the display device. The display device 700 shown in FIG. 34 includes a pixel unit 702 provided on the first substrate 701, a source driver circuit unit 704 and a gate driver circuit unit 706 provided on the first substrate 701, a pixel unit 702, and a source. A sealing material 712 arranged so as to surround the driver circuit section 704 and the gate driver circuit section 706, and
It has a second substrate 705 provided so as to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealing material 712. That is, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 are
It is sealed by a first substrate 701, a sealing material 712, and a second substrate 705. note that,
Although not shown in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display device 700 has a pixel unit 702, a source driver circuit unit 704, a gate driver circuit unit 706, and a gate driver circuit unit in a region different from the region surrounded by the sealing material 712 on the first substrate 701. FPC terminal 708 that is electrically connected to 706
(FPC: Flexible printed circuit) is provided. again,
The FPC 716 is connected to the FPC terminal unit 708, and the pixel unit 702 is connected by the FPC 716.
, Source driver circuit unit 704, and gate driver circuit unit 706 are supplied with various signals and the like. Further, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706
, And the signal line 710 is connected to the FPC terminal portion 708, respectively. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 via the signal line 710.

Further, the display device 700 may be provided with a plurality of gate driver circuit units 706. Further, the display device 700 shows an example in which the source driver circuit unit 704 and the gate driver circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, but the present invention is not limited to this configuration. For example, only the gate driver circuit unit 706 may be formed on the first substrate 701, or only the source driver circuit unit 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. .. The method for connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Further, the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 of the display device 700 have a wiring unit or a plurality of transistors, and the semiconductor device of one aspect of the present invention can be applied. can.

Further, the display device 700 can have various elements. The elements include, for example, a liquid crystal element, an EL (electroluminescence) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element), and an LED (white LED, red LED, green LED, blue LED).
Etc.), Transistor (transistor that emits light according to current), electron emitting element, electronic ink, electrophoresis element, grating light valve (GLV), plasma display (P)
DP), Display element using MEMS (Micro Electro Mechanical System),
Digital Micromirror Device (DMD), DMS (Digital Micro Shutter), MIRASOL (Registered Trademark), IMOD (Interferometric Modulation) Element, Shutter MEMS Display Element, Optical Interferometric MEMS Display, Electrowet It has at least one such as a ting element, a piezoelectric ceramic display, and a display element using carbon nanotubes. In addition to these, a display medium whose contrast, brightness, reflectance, transmittance, and the like are changed by an electric or magnetic action may be provided. An example of a display device using an EL element is an EL display or the like. As an example of a display device using an electron emitting element, a field emission display (FED) or a SED type planar display (SED: Surface-conduction E)
lectron-emitter Display) and the like. An example of a display device using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection liquid crystal display).
and so on. An example of a display device using electronic ink or an electrophoresis element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display device 700, a progressive method, an interlaced method, or the like can be used. Moreover, as a color element controlled by a pixel at the time of color display, R
It is not limited to the three colors of GB (R stands for red, G stands for green, and B stands for blue). For example, it may be composed of four pixels of R pixel, G pixel, B pixel, and W (white) pixel. Alternatively, as in the pentile array, one color element may be composed of two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

In addition, white light (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is used for the backlight.
A colored layer (also referred to as a color filter) may be used in order to display the display device in full color using W). The colored layer is, for example, red (R), green (G), blue (B).
, Yellow (Y) and the like can be used in appropriate combinations. By using a colored layer
Color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part thereof, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% at the time of bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from an element having each emission color. .. By using the self-luminous element, the power consumption may be further reduced as compared with the case where the colored layer is used.

In the present embodiment, a configuration in which a liquid crystal element and an EL element are used as display elements will be described with reference to FIGS. 35 and 36. Note that FIG. 35 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 34, and has a configuration in which a liquid crystal element is used as the display element. Further, FIG. 36 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 34, and has a configuration in which an EL element is used as a display element.

First, the common parts shown in FIGS. 35 and 36 will be described first, and then the different parts will be described below.

[Explanation of common parts of display devices]
The display device 700 shown in FIGS. 35 and 36 includes a routing wiring unit 711, a pixel unit 702, a source driver circuit unit 704, and an FPC terminal unit 708. Further, the routing wiring portion 711 has a signal line 710. Further, the pixel unit 702 includes a transistor 750 and a capacitive element 790 (capacitive element 790a or capacitive element 790b). Further, the source driver circuit unit 704 has a transistor 752.

Further, the signal line 710 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. The signal line 710 is a transistor 75.
A conductive film formed in a process different from that of the source electrode and the drain electrode of 0 and 752, for example, a conductive film that functions as a gate electrode may be used. When, for example, a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen becomes possible.

As the transistor 750 and the transistor 752, the transistor shown above can be used. Here, an example in which the structure of the transistor 100 shown in FIG. 13 is used for the transistor 750 and the transistor 752 is shown, but other transistors shown above may be used.

Further, for the transistor 750 and the transistor 752, for example, the structure of the transistor 100 shown in FIG. 16 may be used. In this case, the electrode 203b can be formed, for example, by using the same process as the formation of the conductive layer 772 and the conductive layer 784. By using the structure of the transistor 100 shown in FIG. 16, for example, the transistor 750 and the transistor 75
The on-current of 2 can be increased, and the circuit operating speed can be increased. Further, the channel width of the transistor 750 and the transistor 752 may be reduced, and the circuit can be integrated.

The transistor used in this embodiment has an oxide semiconductor film that is highly purified and suppresses the formation of oxygen deficiency. The transistor can reduce the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, the transistor used in the present embodiment can be driven at high speed because a relatively high field effect mobility can be obtained. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, also in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

Further, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive layer 780, and an FPC 71.
Has 6. The connection electrode 760 is formed in the same process as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is set to F.
It is electrically connected to the terminal of the PC 716 via the anisotropic conductive layer 780.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

By using a flexible substrate, a flexible display device can be manufactured. Since the display device has flexibility, it can be bonded on a curved surface or an irregular shape, and a wide variety of applications are realized.

By using a flexible substrate such as a plastic substrate, the display device can be made thinner and lighter. Further, a display device using a flexible substrate such as a plastic substrate is not easily cracked, and the durability against an impact when dropped can be improved.

Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix and
A colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching the insulating film.
It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778. In addition, FIG. 35
In the above, the configuration in which the structure 778 is provided on the second substrate 705 side has been illustrated, but the present invention is not limited to this. For example, as shown in FIG. 36, the structure 778 may be provided on the first substrate 701 side, or the structure 778 may be provided on both the first substrate 701 and the second substrate 705.

Further, in FIGS. 35 and 36, on the transistor 750 and the transistor 752,
Insulating films 764, 766, and 768 are provided.

The insulating films 764, 766, and 768 are the insulating films 214 shown in the previous embodiments, respectively.
, 216 and 218 can be formed by the same material and manufacturing method.

[Configuration example of a display device using a liquid crystal element as a display element]
The display device 700 shown in FIG. 35 has a capacitance element 790a. The capacitive element 790a has a structure having a dielectric material between a pair of electrodes. More specifically, as one electrode of the capacitive element 790a, a highly conductive oxide semiconductor film formed through the same process as the oxide semiconductor film functioning as the semiconductor layer of the transistor 750 is used, and the capacitive element 790a As the other electrode, a conductive layer 772 electrically connected to the transistor 750 is used. An insulating film 768 is used as the dielectric sandwiched between the pair of electrodes.

Here, a highly conductive oxide semiconductor film that functions as one of a pair of electrodes of the capacitive element 790a will be described below.

[About highly conductive oxide semiconductor films]
When hydrogen is added to an oxide semiconductor in which oxygen deficiency is formed, hydrogen enters the oxygen deficient site and a donor level is formed in the vicinity of the conduction band. As a result, the oxide semiconductor becomes highly conductive.
Make it a conductor. An oxide semiconductor that has been made into a conductor can be called an oxide conductor. In general, oxide semiconductors have a large energy gap and therefore have translucency with respect to visible light.
On the other hand, the oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the influence of absorption by the donor level is small, and it has the same level of translucency as an oxide semiconductor with respect to visible light.

Here, in each of a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film (OC)). , The temperature dependence of the resistance will be described.

The temperature dependence of the resistivity in the oxide conductor film (OC) is smaller than the temperature dependence of the resistivity in the oxide semiconductor film (OS). Typically, the rate of change in resistivity of the oxide semiconductor film (OC) at 80 K or more and 290 K or less is less than ± 20%. Or 150K or more 2
The rate of change in resistivity below 50 K is less than ± 10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide with or substantially coincide with each other.
Therefore, the oxide conductor film can be used for one electrode of the capacitive element 790a. Here, the oxide conductor film can be formed, for example, by forming silicon nitride on the In-M-Zn oxide.

Further, the display device 700 shown in FIG. 35 has a liquid crystal element 775. The liquid crystal element 775 is
It has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776. The conductive layer 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display device 700 shown in FIG. 35 is
The voltage applied to the conductive layer 772 and the conductive layer 774 changes the orientation state of the liquid crystal layer 776, so that light transmission and non-transmission are controlled and an image can be displayed.

Further, the conductive layer 772 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive layer 772 is formed on the insulating film 768 and is a pixel electrode.
That is, it functions as one electrode of the display element.

Examples of the conductive layer 772 include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. , A conductive material having translucency such as indium tin oxide to which silicon oxide is added can be used.

Although not shown in FIG. 35, an alignment film may be provided on each side of the conductive layers 772 and 774 in contact with the liquid crystal layer 776. Further, although not shown in FIG. 35, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. Depending on the conditions, these liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is
Since the response speed is short and it is optically isotropic, no orientation treatment is required and the viewing angle dependence is small. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. ..

When a liquid crystal element is used as the display element, TN (Twisted Nematic)
) Mode, IPS (In-Plane-Switching) mode, FFS (Frin)
get Field Switching) mode, ASM (Axially System)
tric aligned Micro-cell mode, OCB (Optical)
Compenated Birefringence mode, FLC (Ferroe)
liquid Liquid Crystal mode, AFLC (AntiFerr)
An electric Liquid Crystal) mode or the like can be used.

Further, a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device adopting a vertical orientation (VA) mode may be used. There are several vertical orientation modes, for example, MVA (Multi-Domain Vertical Alignment).
) Mode, PVA (Patterned Vertical Element) mode, ASV mode and the like can be used.

[Display device using a light emitting element as a display element]
The display device 700 shown in FIG. 36 has a capacitance element 790b. The capacitive element 790b has a structure having a dielectric material between a pair of electrodes. More specifically, as one electrode of the capacitive element 790b, a conductive film formed in the same step as the conductive film functioning as the gate electrode of the transistor 750 is used, and as the other electrode of the capacitive element 790b, the source of the transistor 750 is used. A conductive film that functions as an electrode or a drain electrode is used. Further, as the dielectric sandwiched between the pair of electrodes, an insulating film that functions as a gate insulating film of the transistor 750 is used.

Further, in FIG. 36, a flattening insulating film 770 is provided on the insulating film 768.

As the flattening insulating film 770, a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin can be used. The flattening insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials. Further, as shown in FIG. 35, the flattening insulating film 77
A configuration in which 0 is not provided may be used.

Further, the display device 700 shown in FIG. 36 has a light emitting element 782. The light emitting element 782 is
It has a conductive layer 784, an EL layer 786, and a conductive layer 788. Display device 700 shown in FIG.
Can display an image by emitting light from the EL layer 786 of the light emitting element 782.

Further, the conductive layer 784 is connected to a conductive film that functions as a source electrode and a drain electrode of the transistor 750. The conductive layer 784 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element. As the conductive layer 784, a conductive film that is transparent in visible light or a conductive film that is reflective in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film which is reflective in visible light, for example, a material containing aluminum or silver may be used.

Further, in the display device 700 shown in FIG. 36, an insulating film 730 is provided on the flattening insulating film 770 and the conductive layer 784. The insulating film 730 covers a part of the conductive layer 784. The light emitting element 782 has a top emission structure. Therefore, the conductive layer 788 has translucency and is E.
It transmits the light emitted by the L layer 786. In the present embodiment, the top emission structure is illustrated, but the present invention is not limited to this. For example, it can be applied to a bottom emission structure that emits light to the conductive layer 784 side and a dual emission structure that emits light to both the conductive layer 784 and the conductive layer 788.

Further, a colored film 736 is provided at a position overlapping the light emitting element 782, and a light shielding film 738 is provided at a position overlapping the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. Further, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that FIG. 36
In the display device 700 shown in the above, the configuration in which the colored film 736 is provided has been illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed by painting separately, the colored film 736 may not be provided.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 5)
In the present embodiment, a display device having the semiconductor device of one aspect of the present invention will be described with reference to FIG.

The display device shown in FIG. 26A has a region having pixels of the display element (hereinafter referred to as pixel unit 502) and a circuit unit (hereinafter, referred to as pixel unit 502) which is arranged outside the pixel unit 502 and has a circuit for driving the pixels (hereinafter referred to as pixel unit 502).
Hereinafter, a drive circuit unit 504) and a circuit having an element protection function (hereinafter, protection circuit 50).
6) and a terminal portion 507. The protection circuit 506 may not be provided.

It is desirable that a part or all of the drive circuit unit 504 is formed on the same substrate as the pixel unit 502. As a result, the number of parts and the number of terminals can be reduced. Drive circuit unit 504
If part or all of the above is not formed on the same substrate as the pixel unit 502, part or all of the drive circuit unit 504 may be COG or TAB (Tape Automated B).
It can be implemented by on).

The pixel unit 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a gate driver 504a). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a
A signal for driving the shift register is input via the terminal portion 507, and the signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which the scanning signal is given. A plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 50
4a can also supply another signal.

The source driver 504b has a shift register and the like. The source driver 504b
In addition to the signal for driving the shift register, a signal (image signal) that is the source of the data signal is input via the terminal unit 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image signal. Further, the source driver 504b has a function of controlling the output of the data signal according to the pulse signal obtained by inputting the start pulse, the clock signal and the like. Further, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is given. Alternatively, the source driver 504b has a function capable of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured by using, for example, a plurality of analog switches.
The source driver 504b sequentially turns on a plurality of analog switches to turn them on.
A time-division signal of an image signal can be output as a data signal. Further, the source driver 504b may be configured by using a shift register or the like.

In each of the plurality of pixel circuits 501, the pulse signal is input via one of the plurality of scanning lines GL to which the scanning signal is given, and the data signal is transmitted through one of the plurality of data line DLs to which the data signal is given. Entered. Also. In each of the plurality of pixel circuits 501, the writing and holding of data of the data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and n-th column, a pulse signal is input from the gate driver 504a via the scanning line GL_m (m is a natural number of X or less), and the data line DL_n (m is a natural number of X or less) is input according to the potential of the scanning line GL_m.
A data signal is input from the source driver 504b via (n is a natural number less than or equal to Y).

The protection circuit 506 shown in FIG. 26 (A) includes, for example, a gate driver 504a and a pixel circuit 5.
It is connected to the scanning line GL, which is the wiring between 01. Alternatively, the protection circuit 506 is connected to the data line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. The terminal portion 507 refers to a portion provided with a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device.

The protection circuit 506 is a circuit that makes the wiring and another wiring conductive when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 26 (A), the protection circuit 50 is attached to the pixel unit 502 and the drive circuit unit 504, respectively.
By providing 6, ESD (Electrostatic Discharge:
It is possible to increase the resistance of the display device to the overcurrent generated by (electrostatic discharge) or the like.
However, the configuration of the protection circuit 506 is not limited to this, and for example, the configuration may be such that the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

Further, FIG. 26A shows an example in which the drive circuit unit 504 is formed by the gate driver 504a and the source driver 504b, but the present invention is not limited to this configuration. For example, a configuration in which only the gate driver 504a is formed and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

Further, the plurality of pixel circuits 501 shown in FIG. 26 (A) can have the configuration shown in FIG. 26 (B), for example.

The pixel circuit 501 shown in FIG. 26B includes a liquid crystal element 570, a transistor 550, and a capacitance element 560. The transistor shown in the previous embodiment can be applied to the transistor 550.

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of each row.

For example, as a method of driving a display device including a liquid crystal element 570, a TN mode, an STN mode, a VA mode, and an ASM (Axially Symmetrically Defined M) are used.
icro-cell) mode, OCB (Optically Compensated)
Birefringence mode, FLC (Ferroelectric Liqu)
id Crystal) mode, AFLC (Antiferroelectric Li)
Quad Crystal) mode, MVA mode, PVA (Patterned Ve)
ritical Element) mode, IPS mode, FFS mode, or TBA
(Transverse Bend Alignment) mode and the like may be used.
Further, as a driving method of the display device, in addition to the driving method described above, ECB (Electric)
ally Controlled Birefringence mode, PDLC (P
olymer Dispersed Liquid Crystal) mode, PNLC
There are (Polymer Network Liquid Crystal) mode, guest host mode, and the like. However, the present invention is not limited to this, and various liquid crystal elements and various driving methods thereof can be used.

In the pixel circuit 501 of the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. NS. Further, the gate electrode of the transistor 550 is a scanning line G.
It is electrically connected to L_m. The transistor 550 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 560 is a wiring to which a potential is supplied (hereinafter, potential supply line VL).
), And the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitance element 560 has a function as a holding capacitance for holding the written data.

For example, in the display device having the pixel circuit 501 of FIG. 26 (B), for example, FIG. 26 (A)
The gate driver 504a shown in the above sequentially selects the pixel circuit 501 of each row, turns on the transistor 550, and writes the data of the data signal.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 550 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, the plurality of pixel circuits 501 shown in FIG. 26 (A) can have the configuration shown in FIG. 26 (C), for example.

Further, the pixel circuit 501 shown in FIG. 26C includes transistors 552, 554, a capacitance element 562, and a light emitting element 57 2. Transistor 552 and transistor 554
The transistor shown in the previous embodiment can be applied to either or both of the above.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n) to which a data signal is given. Furthermore, the transistor 55
The gate electrode 2 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is given.

The transistor 552 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitance element 562 is a wiring to which a potential is applied (hereinafter, potential supply line VL).
It is electrically connected to (referred to as _a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

The capacitance element 562 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

One of the potential supply line VL_a and the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display device having the pixel circuit 501 of FIG. 26 (C), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 26 (A), the transistor 552 is turned on, and the data of the data signal is input. Write.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 6)
Hereinafter, an example of a semiconductor device using the oxide semiconductor of one aspect of the present invention will be described.

[Example of semiconductor device]
FIG. 37A is an example of a circuit diagram of a semiconductor device according to an aspect of the present invention. The semiconductor device shown in FIG. 37 (A) includes a transistor 100, a transistor 130, a capacitance element 150, a wiring WBL, a wiring RBL, a wiring WL, a wiring CL, a wiring BG, and a wiring SL. ..

In the transistor 130, one of the source and the drain is electrically connected to the wiring RBL, and the transistor 130 is connected to the wiring RBL.
The other is electrically connected to the wiring SL, and the gate is electrically connected to one of the source or drain of the transistor 100 and one of the capacitance elements 150. In the transistor 100, the other of the source and the drain is electrically connected to the wiring WBL, and the first gate is electrically connected to the wiring WL. In the capacitive element 150, the other electrode is electrically connected to the wiring CL. Further, the wiring BG is electrically connected to the second gate of the transistor 100. Transistor 1
30 gates, one of the source or drain of the transistor 100, and the capacitive element 150
The node between one of the electrodes is called a node FN.

The semiconductor device shown in FIG. 37A gives the node FN a potential corresponding to the potential of the wiring WBL when the transistor 100 is in the conductive state (ON state). Further, it has a function of holding the potential of the node FN when the transistor 100 is in the non-conducting state (off state). That is,
The semiconductor device shown in FIG. 37 (A) has a function as a memory cell of the storage device. FIG. 37
By arranging the semiconductor devices shown in (A) in a matrix, a storage device (memory cell array) can be configured.

A liquid crystal element or organic EL (Electrolumin) that is electrically connected to the node FN.
When having a display element such as an access) element, the semiconductor device of FIG. 37 (A) can also function as a pixel of the display device.

The selection of the conductive state and the non-conducting state of the transistor 100 can be controlled by the potential given to the wiring WL or the wiring BG. Further, the threshold value of the transistor 100 can be controlled by the potential given to the wiring WL or the wiring BG. By using a transistor having a small off current as the transistor 100, the potential of the node FN in the non-conducting state can be maintained for a long period of time. Therefore, the refresh frequency of the semiconductor device can be reduced, and the semiconductor device with low power consumption can be realized. By using, for example, a transistor using an oxide semiconductor film as the transistor 100, a transistor having a small off-current can be realized.

A constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is given to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 fluctuates depending on the potential of the node FN. By utilizing the fact that the conduction state and the non-conduction state of the transistor 130 change due to the apparent fluctuation of the threshold voltage, the potential information held in the node FN can be read out as data.

Incidentally, 10 years at 85 ° C. The potential held in the node FN (3.15 × 10 ⁸ seconds)
To retain the per volume 1 fF, value 4.3yA off current per channel width 1μm of the transistor (yoctoampere: 1 yA is ^{10 -24} A) is preferably less than. At this time, it is preferable that the permissible fluctuation of the potential of the node FN is within 0.5 V. Alternatively, at 95 ° C., the off-current is preferably less than 1.5 yA.

Further, by increasing the capacitance, the potential can be held in the node FN for a longer period of time. That is, the holding time can be lengthened.

In the semiconductor device shown in FIG. 37 (A), information can be written, held, and read as follows by taking advantage of the feature that the potential of the gate electrode of the transistor 130 can be held.

The writing and holding of information will be described. First, the potential of the wiring WL is set to the transistor 1
The potential at which 00 is turned on is set, and the transistor 100 is turned on. This will
The potential of the wiring WBL is given to the gate electrode of the transistor 130 and the capacitive element 150. That is, a predetermined charge is given to the gate electrode of the transistor 130 (writing). Here, a charge that gives two different potential levels (hereinafter, Low level charge, High)
It is assumed that one of the h-level charges) is given. After that, the potential of the wiring WL is changed.
By setting the potential at which the transistor 100 is turned off and turning the transistor 100 off, the electric charge given to the gate electrode of the transistor 130 is retained (retained).

Since the off-current of the transistor 100 is extremely small, the charge of the gate electrode of the transistor 130 is retained for a long time.

Next, reading information will be described. When a predetermined potential (constant potential) is applied to the wiring RBL and an appropriate potential (reading potential) is applied to the wiring CL, the wiring SL has a different potential depending on the amount of electric charge held in the gate electrode of the transistor 130. Take. Generally, when the transistor 130 is an n-channel type, the apparent threshold value _{Vth_H} when a high level charge is given to the gate electrode of the transistor 130 is a low level charge given to the gate electrode of the transistor 130. This is because it is lower than the apparent threshold value V _{th_L in the case.} Here, the apparent threshold voltage means the potential of the wiring CL required to put the transistor 130 in the “ON state”. Therefore, the potential of the wiring CL is changed to V _{t.
By setting} the potential V ₀ between h_H and V _{th_L} , the charge given to the gate electrode of the transistor 130 can be discriminated. For example, in writing, when a high level charge is given, if the potential of the wiring CL becomes V ₀ (> V _{th_H} ), the transistor 1
30 is in the "on state". When the Low level charge is given, the transistor 130 remains in the “off state” even when the potential of the wiring CL becomes V ₀ (<V _{th_L).} Therefore, the retained information can be read out by discriminating the potential of the wiring SL. In addition, in order to reduce the number of wirings, for example, WBL and RBL shown in FIG. 37A may be made conductive.

When the memory cells are arranged in an array and used, it is necessary to be able to read only the information of the desired memory cells. When the information is not read in this way, the potential at which the transistor 130 is in the "off state" regardless of the state of the gate electrode, that is, V _{th_H}
A smaller potential may be applied to the wiring CL. Alternatively, the wiring CL may be given a potential that _{causes the} transistor 130 to be in the “on state” regardless of the state of the gate electrode, that is, a potential larger than Vth_L.

The semiconductor device shown in FIG. 37 (B) is mainly shown in FIG. 37 in that the transistor 130 is not provided.
It is different from (A). In this case as well, information can be written and held by the same operation as described above.

Next, reading information will be described. When the transistor 100 is turned on, the floating wiring BL and the capacitance element 150 are electrically connected, and the electric charge is redistributed between the wiring BL and the capacitance element 150. As a result, the potential of the wiring BL changes. The amount of change in the potential of the wiring BL is
It takes a different value depending on the potential of one electrode of the capacitance element 150 (or the electric charge accumulated in the capacitance element 150).

For example, the potential of one electrode of the capacitance element 150 is V, the capacitance of the capacitance element 150 is C, and the wiring B.
Assuming that the capacitance component of L is CB and the potential of the wiring BL before the charge is redistributed is VB0.
The potential of the wiring BL after the charge is redistributed becomes (CB × VB0 + C × V) / (CB + C). Therefore, as a state of the memory cell, the potential of one electrode of the capacitance element 150 is V1.
Assuming that the two states of V0 (V1> V0) are taken, the wiring BL when the potential V1 is held.
The potential of (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential of the wiring BL (= (CB × VB0 + C × V0) / (CB + C)) when the potential V0 is held. I understand.

Then, the information can be read out by comparing the potential of the wiring BL with a predetermined potential.

The semiconductor device shown in FIGS. 37 (A) and 37 (B) can also be used as, for example, a storage device for a CPU.

FIG. 38 shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. 37 (A). Note that FIG. 38 shows an example in which WBL and RBL are made conductive in order to reduce the number of wires. Note that FIG. 38 (B) shows a cross section of a plane that passes through the alternate long and short dash line AB shown in FIG. 38 (A) and is perpendicular to FIG. 38 (A). Further, FIG. 38 (C) passes through the alternate long and short dash line CD shown in FIG. 38 (A), and is shown in FIG.
The cross section of the plane perpendicular to 8 (A) is shown.

The transistor 100 is preferably provided above the transistor 130. By stacking the transistor 100 and the transistor 130, for example, the circuit area can be reduced. As the transistor 100, for example, the transistor shown in the third embodiment can be used. FIG. 38 shows an example in which the transistor 100 shown in FIG. 12 is used.

The transistor 130 is configured to include a first semiconductor material. Also, transistor 1
00 is configured to include a second semiconductor material. Examples of the semiconductor that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium, and arsenic, and compound semiconductor materials having silicon, germanium, gallium, arsenic, and aluminum. Examples thereof include organic semiconductor materials and oxide semiconductor materials.

The first semiconductor material and the second semiconductor material may be the same material, but it is more preferable that they are different semiconductor materials. Here, single crystal silicon is used as the first semiconductor material.
A case where an oxide semiconductor is used as the second semiconductor material will be described.

[First transistor]
The transistor 130 is provided on the semiconductor substrate 131, and is a semiconductor layer 132, a gate insulating film 134, a gate electrode 135, and a low resistance layer 133a and a low resistance layer 133b that function as a source region or a drain region. Has.

The transistor 130 may be either a p-channel type or an n-channel type, but an appropriate transistor may be used depending on the circuit configuration and the driving method.

It is preferable that a semiconductor such as a silicon-based semiconductor is contained in a region in which a channel of the semiconductor layer 132 is formed or a region in the vicinity thereof, a low resistance layer 133a and a low resistance layer 133b serving as a source region or a drain region, and the like, and a single crystal. It preferably contains silicon. Or G
e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide),
It may be formed of a material having GaAlAs (gallium-aluminum arsenic) or the like. A configuration using silicon having a strain in the crystal lattice may be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 130 can be made into a HEMT (High Electron Mob).
It may be an illumination Transistor).

Further, the transistor 130 may have a region 176a and a region 176b which are LDD (Lightly Doped Drain) regions.

In the low resistance layer 133a and the low resistance layer 133b, in addition to the semiconductor material applied to the semiconductor layer 132, an element that imparts n-type conductivity such as phosphorus or an element that imparts p-type conductivity such as boron is used. include.

The gate electrode 135 is an element that imparts n-type conductivity such as phosphorus, or p such as boron.
A semiconductor material such as silicon, a metal material, an alloy material, or a conductive material such as a metal oxide material containing an element that imparts conductivity to the mold can be used.

Here, the transistor 190 as shown in FIGS. 29 (A) and 29 (B) may be used instead of the transistor 130. FIG. 29 (B) shows a cross section of a plane passing through the alternate long and short dash line EF shown in FIG. 29 (A) and perpendicular to FIG. 29 (A). In the transistor 190, the semiconductor layer 132 (a part of the semiconductor substrate) on which the channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along the side surfaces and the upper surface thereof. Further, an element separation layer 181 is provided between the transistors. Since such a transistor 190 utilizes a convex portion of a semiconductor substrate, it is also called a FIN type transistor. In addition, an insulating film that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion may be provided. Further, although the case where a part of the semiconductor substrate is processed to form a convex portion is shown here, SOI (Silicon o) is shown.
n Insulator) The substrate may be processed to form a semiconductor layer having a convex shape.

An insulating film 136, an insulating film 137, and an insulating film 138 are laminated in this order so as to cover the transistor 130.

The insulating film 136 is a low resistance layer 133a and a low resistance layer 133 in the manufacturing process of the semiconductor device.
It functions as a protective film when the element added to b that imparts conductivity is activated. Insulating film 13
6 may not be provided if it is unnecessary.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By performing the heat treatment, the dangling bond in the semiconductor layer 132 is terminated by the hydrogen in the insulating film 137, and the reliability of the transistor 130 can be improved.

The insulating film 138 functions as a flattening layer for flattening a step generated by a transistor 130 or the like provided under the insulating film 138. The upper surface of the insulating film 138 may be flattened by the CMP method or the like.

Further, the insulating film 136, the insulating film 137, and the insulating film 138 include the low resistance layer 133a and the low resistance layer 1.
A plug 140 electrically connected to 33b or the like, a plug 139 electrically connected to the gate electrode 135 of the transistor 130, or the like may be embedded.

A barrier membrane 111 is provided between the transistor 130 and the transistor 100. The barrier membrane 111 is a layer having a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. Further, the barrier membrane 111 preferably has low oxygen permeability. Here, the fact that water and hydrogen are difficult to diffuse means that the permeability of water and hydrogen is low as compared with, for example, silicon oxide generally used as an insulating film. Further, low oxygen permeability means that oxygen permeability is low as compared with, for example, silicon oxide generally used as an insulating film.

Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST). ) Etc. so-called h
The insulating film containing the high-k material can be used in a single layer or in a laminated manner. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, and gallium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided to form an oxide nitride film. Silicon oxide, silicon oxide nitride, or silicon nitride may be laminated on the above insulating film. In particular, aluminum oxide is more preferable because it has an excellent barrier property against water and hydrogen.

Further, the above-mentioned material is a material having an excellent barrier property of oxygen in addition to hydrogen and water. Therefore, it is possible to prevent the oxygen released when the insulating film 114 is heated from diffusing into the lower layer than the barrier film 111. As a result, the transistor 100 is released from the insulating film 114.
The amount of oxygen that can be supplied to the semiconductor layer of the above can be increased.

Here, in the layer below the barrier membrane 111, it is preferable to reduce hydrogen, water, and the like by, for example, heat treatment. The heat treatment conditions may be, for example, 170 ° C. or higher under an inert gas atmosphere or a reduced pressure atmosphere.

When single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment involves terminating the unpaired bond (also referred to as dangling bond) of silicon with hydrogen (also referred to as hydrogenation treatment). Can also serve as.

The conductive layer 151, the conductive layer 152a, and the conductive layer 152b are provided so as to sandwich the barrier film 111, and form the capacitive element 150. The conductive layer 151 is electrically connected to the conductive layer 104a of the transistor 100.

An insulating film 114 is provided so as to cover the barrier film 111, the conductive layer 152a, the conductive layer 152b, the conductive layer 105, and the like. For the insulating film 114, refer to, for example, the description of the insulating film 114 in FIG.

[Second transistor]
A transistor 100 is provided above the insulating film 114. In the example shown in FIG. 38, the transistor shown in FIG. 12 is used as the transistor 100.

Further, the transistor 100 shown in FIG. 38 is a conductive layer 1 that functions as a second gate electrode.
Has 05. The conductive layer 105 may be formed at the same time as the conductive layer 152a and the conductive layer 152b that form a part of the capacitive element 150. By forming these conductive layers at the same time, for example, the process can be simplified.

Further, an insulating film 112, an insulating film 113, and an insulating film 116 are provided so as to cover the transistor 100.

As with the barrier film 111, it is preferable to use a material for the insulating film 112 in which water and hydrogen do not easily diffuse. In particular, it is preferable to use a material that does not easily allow oxygen to permeate.

The insulating film 112 may have a laminated structure of two or more layers. In that case, for example, it is preferable that the insulating film 112 has a two-layer laminated structure, and a material that does not easily diffuse water or hydrogen is used for the upper layer. Further, for the lower layer, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride or the like may be used. The insulating film provided in the lower layer may be configured to supply oxygen from the upper side of the semiconductor layer 101 via the gate insulating film 102 as an insulating film in which oxygen is desorbed by heating, similar to the insulating film 114.

By covering the semiconductor layer 101 with the insulating film 112, it is possible to suppress the release of oxygen from the semiconductor layer 101 above the insulating film 112. Further, since the oxygen desorbed from the insulating film 114 or the like can be confined below the insulating film 112, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

Further, by providing the insulating film 112, it is possible to prevent water and hydrogen from being mixed into the oxide semiconductor from the outside. Therefore, it is possible to realize a highly reliable transistor in which fluctuations in electrical characteristics are suppressed.

Examples of the insulating film 113 include silicon oxide, silicon nitriding, silicon nitride, and the like.
Silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride, aluminum nitride or the like may be used, and the mixture is laminated or provided in a single layer.

The insulating film 116 that covers the transistor 100 functions as a flattening layer that covers the uneven shape of the underlying layer. Further, the insulating film 113 may have a function as a protective film when forming the insulating film 116. The insulating film 113 may not be provided if it is unnecessary. As the insulating film 116, for example, silicon oxide, silicon oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride or the like may be used, and the insulating film 116 is provided in a laminated or single layer.

A plug 321 and a plug 322 and a plug 123 that are electrically connected to the conductive layer 104b are embedded in the insulating film 112, the insulating film 113, and the insulating film 116.

A wiring 124 or the like that electrically connects to the plug 322 is provided above the insulating film 116.

Further, as shown in FIG. 38, the insulating film 137 containing the same material as the barrier film 111 may be provided on the insulating film 136 containing hydrogen. With such a configuration, it is possible to effectively suppress the diffusion of water and hydrogen remaining in the insulating film 136 containing hydrogen upward.

Wiring 124, wiring such as wiring 166, conductive layer 143, conductive layer 151, conductive layer 152a, conductive layer 152b, conductive layer 251 and the like, and plug 123, plug 139, plug 1
For plugs such as 40, plug 164, and plug 165, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used as the material. In particular, it is preferable to use a refractory material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, a material such as titanium nitride or titanium may be used by laminating with another material.

[Example of manufacturing method]
Next, an example of a method for manufacturing the semiconductor device of FIG. 38 will be described with reference to FIGS. 39 to 42.

First, the semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Moreover, you may use the SOI substrate as the semiconductor substrate 131. Hereinafter, a case where single crystal silicon is used as the semiconductor substrate 131 will be described.

Subsequently, an element separation layer (not shown) is formed on the semiconductor substrate 131. The element separation layer is LOC
OS (Local Oxidation of Silicon) method or STI (Sh)
It may be formed by using an allow Trench Isolation method, a mesa separation method, or the like.

When forming a p-type transistor and an n-type transistor on the same substrate, the semiconductor substrate 1
N-well or p-well may be formed in a part of 31. For example, the n-type semiconductor substrate 13
Impurity elements such as boron, which imparts p-type conductivity, may be added to 1 to form p-wells, and n-type transistors and p-type transistors may be formed on the same substrate.

Subsequently, an insulating film to be the gate insulating film 134 is formed on the semiconductor substrate 131. for example,
The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, a laminated structure of a silicon oxide film and a silicon nitride film may be formed by nitriding the surface of the silicon oxide film by performing a nitriding treatment after forming silicon oxide by a thermal oxidation method. Alternatively, silicon oxide, silicon nitride nitride, tantalum oxide which is a high dielectric constant (also referred to as high-k material), hafnium oxide, hafnium oxide silicate, zirconium oxide,
Metal oxides such as aluminum oxide and titanium oxide, rare earth oxides such as lanthanum oxide, and the like may be used.

The insulating film is obtained by a sputtering method or CVD (Chemical Vapor Depot).
site) method (including thermal CVD method, MOCVD (Metal Organic CVD) method, PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo)
molecular Beam Epitaxy) method, ALD (Atomic Layer)
Deposition) method, or PLD (Pulsed Laser Deposition)
It may be formed by forming a film by an ion) method or the like.

Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium and the like, or an alloy material or compound material containing these metals as a main component. Further, polycrystalline silicon to which impurities such as phosphorus are added can be used. Further, a laminated structure of the metal nitride film and the above-mentioned metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

The conductive film is a sputtering method, a vapor deposition method, a CVD method (thermal CVD method, MOCVD method, PEC).
A film can be formed by a VD method or the like). Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, a resist mask is formed on the conductive film by a lithography method or the like, and an unnecessary portion of the conductive film is removed. After that, the gate electrode 135 can be formed by removing the resist mask.

Here, a method for processing the film to be processed will be described. As a processing method, various microfabrication techniques can be used. For example, a method of slimming a resist mask formed by a photolithography method or the like may be used. Further, a dummy pattern may be formed by a photolithography method or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the remaining sidewall may be used as a resist mask to etch the film to be processed. In addition, in order to achieve a high aspect ratio for etching the film to be processed,
It is preferable to use anisotropic dry etching. Further, a hard mask made of an inorganic film or a metal film may be used.

The light used to form the resist mask is, for example, i-line (wavelength 365 nm) and g-line (wavelength 43).
6 nm), h-ray (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet rays, KrF laser light, ArF laser light, or the like can also be used.
Further, the exposure may be performed by the immersion exposure technique. Further, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

Further, before forming the resist film to be the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed so as to cover the step of the lower layer and flatten the surface by, for example, a spin coating method, and the thickness of the resist mask provided on the upper layer of the organic resin film varies. Can be reduced. Further, particularly when performing fine processing, it is preferable to use a material that functions as an antireflection film against light used for exposure as the organic resin film. Examples of the organic resin film having such a function include BARC (Bottom Anti-Reflection).
There is a coating film and the like. The organic resin film may be removed at the same time as the resist mask is removed, or may be removed after the resist mask is removed.

From this point onward, for the description of the processing using the resist mask, for example, the processing method described with respect to the gate electrode 135 may be referred to. Further, in the present specification, the description of resist removal after etching the film to be processed may be omitted.

After forming the gate electrode 135, a sidewall covering the side surface of the gate electrode 135 may be formed. After forming an insulating film thicker than the thickness of the gate electrode 135, the sidewall is formed.
It can be formed by performing anisotropic etching and leaving the insulating film only on the side surface portion of the gate electrode 135.

Although FIG. 39 shows an example in which the gate insulating film is not etched when the sidewall is formed, the insulating film to be the gate insulating film 134 may be etched at the same time when the sidewall is formed. In this case, the gate insulating film 134 is formed on the lower part of the gate electrode 135 and the sidewall.

Subsequently, an element that imparts n-type conductivity such as phosphorus or an element that imparts p-type conductivity such as boron is added to the region of the semiconductor substrate 131 where the gate electrode 135 (and sidewall) is not provided. do. The schematic cross-sectional view at this stage corresponds to FIG. 39 (A).

Subsequently, after forming the insulating film 136, for example, heat treatment for activating the above-mentioned element that imparts conductivity is performed. The heat treatment can be carried out in an atmosphere of an inert gas such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere, for example, at 400 ° C. or higher and lower than the strain point of the substrate.

The insulating film 136 may be made of, for example, silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum oxide, aluminum nitride, aluminum nitride, or the like, and is provided in a laminated or single layer. The insulating film 136 can be formed by using a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. To reduce the damage caused by plasma, thermal CVD method, MOCVD method or A
The LD method is preferred.

At this stage, the transistor 130 is formed. Further, the third transistor 160 may be formed in the same manner as for forming the transistor 130.

Subsequently, the insulating film 137 and the insulating film 138 are formed.

As the insulating film 137, in addition to the material that can be used for the insulating film 136, silicon nitride (SiNOH) containing oxygen and hydrogen may be used. The insulating film 138 is a material that can be used for the insulating film 136, as well as TEOS (Tetra-Ethyl-Ortho-Sili).
It is preferable to use silicon oxide having a good step covering property, which is formed by reacting cate) or silane or the like with oxygen or nitrous oxide.

The insulating film 137 and the insulating film 138 are, for example, a sputtering method, a CVD method (thermal CVD method, etc.).
It can be formed by using the MOCVD method, PECVD method, etc.), MBE method, ALD method, PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, the upper surface of the insulating film 138 is flattened by using the CMP method or the like. Further, a flattening film may be used as the insulating film 138. In that case, it is not always necessary to flatten by the CMP method or the like.
For the formation of the flattening film, for example, a normal pressure CVD method, a coating method, or the like can be used. Normal pressure C
Examples of the film that can be formed by using the VD method include BPSG (Boron Phosphor).
us Silicate Glass) and the like. Further, examples of the film that can be formed by using the coating method include HSQ (hydrogen silsesquioxane) and the like. After that, a heat treatment may be performed to terminate the dangling bond in the semiconductor layer 132 with hydrogen desorbing from the insulating film 137.

Subsequently, openings are formed in the insulating film 136, the insulating film 137, and the insulating film 138 to reach the low resistance layer 133a, the low resistance layer 133b, the gate electrode 135, and the like (see FIG. 39 (B)). Then, a conductive film is formed so as to fill the opening (see FIG. 39 (C)). After that, the insulating film 138
A plug 139, a plug 140, and the like are formed by subjecting the conductive film to a flattening treatment so that the upper surface of the conductive film is exposed (see FIG. 39 (D)). The conductive film can be formed by using, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like.

Subsequently, the insulating film 215 is formed on the insulating film 138. The insulating film 215 can be formed by the same material and method as the insulating film 136 and the like. After forming the insulating film 215, heat treatment may be performed.

The third heat treatment can be performed under the conditions exemplified in the above description of the laminated structure. For example, the conditions described in the first heat treatment can be used.

Subsequently, an opening is formed in the insulating film 215. After that, a conductive film is formed so as to fill the opening, and the conductive film is flattened so that the upper surface of the insulating film 215 is exposed, thereby forming a conductive layer 251, a conductive layer 143, a conductive layer 151, and the like. (See FIG. 39 (E)). When forming a conductive film in the opening, for example, a material such as titanium nitride or titanium may be formed in the opening, and then another conductive material may be laminated. For example, by using titanium nitride or titanium as the lower layer of the laminated film, the adhesion to the opening can be improved.

Subsequently, the barrier film 111 is formed to form an opening (see FIG. 40 (A)). The barrier film 111 is, for example, a sputtering method, a CVD method (thermal CVD method, MOCVD method, PECVD method).
It can be formed by using the MBE method, the ALD method, the PLD method, or the like.
In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, a conductive film to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b is formed.
After that, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see FIG. 40 (B)).

Next, the insulating film 114 is formed. The insulating film 114 includes, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL.
It can be formed by using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

In order to allow the insulating film 114 to contain an excessive amount of oxygen, for example, the insulating film 11 is provided in an oxygen atmosphere.
The film formation of 4 may be performed. Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to form a region containing an excess of oxygen, or both means may be combined.

For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, a plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. or,
It may contain hydrogen or the like. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

Further, after molding the insulating film 114, a flattening treatment using a CMP method or the like may be performed in order to improve the flatness of the upper surface thereof.

Next, the semiconductor film to be the insulator layer 101a and the semiconductor film to be the semiconductor layer 101b are formed in this order (see FIG. 40C). It is preferable that the semiconductor film is continuously formed without being exposed to the atmosphere. The semiconductor to be the insulator layer 101a and the semiconductor to be the semiconductor layer 101b may be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the semiconductor that becomes the insulator layer 101a and the semiconductor that becomes the semiconductor layer 101b, I
When the n-Ga-Zn oxide layer is formed by the MOCVD method, trimethylindium, trimethylgallium, dimethylzinc or the like may be used as the raw material gas. The combination of the above raw material gases is not limited, and triethylindium or the like may be used instead of trimethylindium. Further, triethylgallium or the like may be used instead of trimethylgallium. Further, diethylzinc or the like may be used instead of dimethylzinc.

Here, oxygen may be introduced into the insulator layer 101a after the insulator layer 101a is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, a plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. or,
It may contain hydrogen or the like. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

After forming the insulator layer 101a and the semiconductor layer 101b, heat treatment may be performed. The heat treatment may be carried out at a temperature of 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower, in an atmosphere of an inert gas, an atmosphere containing 10 ppm or more of an oxidizing gas, or a reduced pressure state. Further, the atmosphere of the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in the atmosphere of an inert gas. The heat treatment may be performed immediately after the semiconductor film is formed, or the semiconductor film is processed to form island-shaped insulator layers 101a and 101b.
It may be done after forming. By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film, and oxygen deficiency in the semiconductor film can be reduced.

Then, using a resist mask, the island-shaped insulator layer 101a and the island-shaped semiconductor layer 101b
(See FIG. 40 (D)). When the semiconductor film is etched, a part of the insulating film 114 may be etched, and the insulating film 114 in the region not covered by the insulator layer 101a and the semiconductor layer 101b may be thinned. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 does not disappear due to the etching.

Depending on the etching conditions of the semiconductor film, the resist may disappear during the etching process. Therefore, a material having high etching resistance, for example, a so-called hard mask made of an inorganic film or a metal film may be used. Here, an example in which a conductive film is used as the hard mask 281 is shown. FIG. 41 (A) shows an example in which a semiconductor film is processed using a hard mask 281 to form an insulator layer 101a and a semiconductor layer 101b. Here, if a material that can be used as the conductive layer 104a and the conductive layer 104b is used for the hard mask 281, the hard mask 281 can be processed to form the conductive layer 104a and the conductive layer 104b. By using such a method, for example, the transistor 100 shown in FIG. 30 can be manufactured.

After forming the structure shown in FIG. 40 (D), the insulating film 114 is provided with an opening reaching the conductive layer 151, the conductive layer 251 and the like (see FIG. 41 (B)). After that, a conductive film to be a conductive layer 104a, a conductive layer 104b, or the like is formed so as to embed the opening provided in the insulating film 114. Conductive layer 1
For the formation of the conductive film to be 04a, the conductive layer 104b, etc., for example, a sputtering method or a CVD method (
Thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or PLD
It can be formed by using a method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Next, using a resist mask, unnecessary portions of the conductive film to be the conductive layer 104a, the conductive layer 104b, etc. are removed by etching to form the conductive layer 104a, the conductive layer 104b, etc. (
(See FIG. 41 (C)). Here, when etching the conductive film, the semiconductor layer 101b and the insulating film 1
A part of the upper part of 14 may be etched, and the part that does not overlap with the conductive layer 104a and the conductive layer 104b may be thinned. Therefore, the thickness of the semiconductor film or the like to be the semiconductor layer 101b is determined.
It is preferable to form a thick layer in advance in consideration of the etching depth.

Next, the insulator layer 101c and the gate insulating film 102 are formed. Then, it is processed by etching using a resist mask (see FIG. 42 (A)). Next, a conductive film to be the gate electrode 103 is formed, and the conductive film is processed using a resist mask to form the gate electrode 103 (see FIG. 42 (B)).

For the method of forming the insulator layer 101c, for example, the insulator layer 101a may be referred to.

Further, oxygen may be introduced into the insulator layer 101c after the insulator layer 101c is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101c after the film formation to form a region containing an excess of oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, a plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. or,
It may contain hydrogen or the like. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

At this stage, the transistor 100 is formed.

Next, the insulating film 112 is formed. The insulating film 112 includes, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL.
It can be formed by using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the coating property can be improved. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

After forming the insulating film 112, heat treatment may be performed. By heat treatment, oxygen can be supplied to the semiconductor layer 101 from the insulating film 114 or the like, and oxygen deficiency in the semiconductor layer 101 can be reduced.

Further, the insulating film 112 may have a laminated structure of two or more layers.

Subsequently, the insulating film 113 is formed. The insulating film 113 is, for example, a sputtering method or CVD.
Method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed by using the LD method or the like. In particular, the CVD method, preferably plasma CVD
When a film is formed by the method, the coating property can be improved, which is preferable. Further, in order to reduce the damage caused by plasma, the thermal CVD method, the MOCVD method or the ALD method is preferable.

Subsequently, the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulator layer 101c were formed.
An opening that reaches the conductive layer 104a or the like is provided. Next, after forming a conductive film so as to embed the opening, an unnecessary portion is removed using a resist mask to form a plug 321 and a plug 322.

Subsequently, the insulating film 116 is formed. The insulating film 116 is, for example, a sputtering method or CVD.
Method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed by using the LD method or the like. When an organic insulating material such as an organic resin is used as the insulating film 116, it may be formed by a coating method such as a spin coating method. Further, it is preferable to perform a flattening treatment on the upper surface of the insulating film 116 after the insulating film 116 is formed. Further, as the insulating film 116, the material shown in the insulating film 138 or the forming method may be used.

Subsequently, the plug 12 reaching the plug 322 on the insulating film 116 by the same method as described above.
Form 3 mag.

Subsequently, a conductive film is formed on the insulating film 116. After that, an unnecessary portion of the conductive film can be removed by etching using a resist mask by the same method as described above to form wiring 124 and the like.

By the above steps, the semiconductor device according to one aspect of the present invention can be manufactured.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 7)
In the present embodiment, an example of a circuit using the transistor of one aspect of the present invention will be described with reference to the drawings.

[Circuit configuration example]
In the configuration shown in the semiconductor device to which the first embodiment is applied, various circuits can be configured by different connection configurations of transistors, wirings, and electrodes. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device of one aspect of the present invention will be described.

[CMOS circuit]
In the circuit diagram shown in FIG. 37 (C), a so-called CM in which a p-channel type transistor 2200 and an n-channel type transistor 2100 are connected in series and their respective gates are connected.
The configuration of the OS circuit is shown. In the figure, the transistor to which the second semiconductor material is applied is indicated by the symbol “OS”. Here, the CMOS circuit shown in the present embodiment is N.
AND circuit, NOR circuit, encoder, decoder, MUX (multiplamplife)
It can be used as a basic element of a logic circuit such as ier) or DEMUX (demultiplexer).

[Analog switch]
Further, the circuit diagram shown in FIG. 37 (D) shows a configuration in which the sources and drains of the transistors 2100 and the transistors 2200 are connected. With such a configuration,
It can function as a so-called analog switch.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 8)
In the present embodiment, a display module having the semiconductor device of one aspect of the present invention will be described with reference to FIG. 27.

The display module 8000 shown in FIG. 27 has a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, and a printed circuit board 801 between the upper cover 8001 and the lower cover 8002.
0, has battery 8011.

The semiconductor device of one aspect of the present invention can be used, for example, in the display panel 8006.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be used by superimposing a resistive film type or capacitance type touch panel on the display panel 8006. It is also possible to provide the opposite substrate (sealing substrate) of the display panel 8006 with a touch panel function. In addition, the display panel 8
It is also possible to provide an optical sensor in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008. In FIG. 27, the configuration in which the light source 8008 is arranged on the backlight 8007 has been illustrated, but the present invention is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusing plate may be used. When a self-luminous light emitting element such as an organic EL element is used, or when a reflective panel or the like is used, the backlight 8007 may not be provided.

The frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010, in addition to the protective function of the display panel 8006. Further, the frame 8009 may have a function as a heat radiating plate.

The printed circuit board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying electric power to the power supply circuit may be an external commercial power source or a power source supplied by a separately provided battery 8011. The battery 8011 can be omitted when a commercial power source is used.

Further, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

The display module 8000 shown in this embodiment may have flexibility. By having flexibility, it becomes possible to bond it on a curved surface or an irregular shape, and a wide variety of applications are realized.

The configuration shown in this embodiment can be used in combination with the configuration shown in other embodiments as appropriate.

(Embodiment 9)
In the present embodiment, the R including the transistor or the storage device exemplified in the above embodiment.
The F tag will be described with reference to FIG. 28.

The RF tag in the present embodiment has a storage circuit inside, stores information necessary for the storage circuit, and exchanges information with the outside by using non-contact means, for example, wireless communication. Due to these characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading individual information of the article or the like. In addition, extremely high reliability is required for use in these applications.

The structure of the RF tag will be described with reference to FIG. 28. FIG. 28 is a block diagram showing a configuration example of an RF tag.

As shown in FIG. 28, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader / writer, etc.). Further, the RF tag 800 has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. In addition, a material capable of sufficiently suppressing the reverse current, for example, an oxide semiconductor, may be used for the transistor having a rectifying action included in the demodulation circuit 807. As a result, it is possible to suppress a decrease in the rectifying action due to the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RF tag 800 shown in this embodiment can be used in any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal at the antenna 804, for example, half-wave double pressure rectification, and the signal rectified by the capacitive element provided in the subsequent stage is used. It is a circuit for generating an input potential by smoothing. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so that power exceeding a certain power is not input to the subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit utilizes the rising edge of the stable power supply voltage to make the logic circuit 8
This is a circuit for generating a reset signal of 09.

The demodulation circuit 807 is a circuit for generating a demodulated signal by demodulating the input AC signal by detecting the envelope. Further, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The storage circuit 810 is a circuit that holds the input information, and has a row decoder, a column decoder, a storage area, and the like. Further, the ROM 811 is a circuit for storing a unique number (ID) and the like and outputting according to processing.

It should be noted that each of the above-mentioned circuits can be appropriately discarded as needed.

Here, the storage circuit described in the previous embodiment can be used for the storage circuit 810. Since the storage circuit of one aspect of the present invention can hold information even when the power supply is cut off, it can be suitably used for an RF tag. Further, the storage circuit of one aspect of the present invention does not cause a difference in the maximum communication distance between reading and writing data because the power (voltage) required for writing data is significantly smaller than that of the conventional non-volatile memory. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.

Further, since the storage circuit of one aspect of the present invention can be used as a non-volatile memory, it can also be applied to ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data to the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign the unique number only to the non-defective product to be shipped, instead of assigning the unique number to all the RF tags produced. The unique numbers of the products after shipment do not become discontinuous, and customer management corresponding to the products after shipment becomes easy.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 10)
The semiconductor device according to one aspect of the present invention is an image reproduction device (typically, DVD: Digital Versailles Dis) including a display device, a personal computer, and a recording medium.
It can be used for a device having a display capable of reproducing a recording medium such as c and displaying the image). In addition, as electronic devices that can use the semiconductor device according to one aspect of the present invention, mobile phones, game machines including portable types, mobile data terminals, electronic books, video cameras, and the like.
Cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automatic cash deposit / payment machines (ATM) ), Vending machines, etc. Specific examples of these electronic devices are shown in FIG. 57.

FIG. 57A shows a portable game machine, which is a housing 901, a housing 902, a display unit 903, a display unit 904, a microphone 905, a speaker 906, an operation key 907, and a stylus 90.
Has 8 mag. The portable game machine shown in FIG. 57A has two display units 903 and a display unit 904, but the number of display units included in the portable game machine is not limited to this.

FIG. 57B is a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, and the like. First display unit 91
Reference numeral 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. be. The image in the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915. Further, a display device having a function as a position input device may be used for at least one of the first display unit 913 and the second display unit 914. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, which is also called a photo sensor, in the pixel portion of the display device.

FIG. 57 (C) is a notebook personal computer, which includes a housing 921, a display unit 922, and a display unit 922.
It has a keyboard 923, a pointing device 924, and the like.

FIG. 57 (D) shows an electric freezer / refrigerator, which includes a housing 931, a refrigerator door 932, and a freezer door 9.
It has 33 and the like.

FIG. 57 (E) is a video camera, which is a first housing 941, a second housing 942, and a display unit 943.
, Operation key 944, lens 945, connection portion 946 and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. be. The video on the display unit 943 is displayed on the first housing 941 and the second housing 94 on the connection unit 946.
It may be configured to switch according to the angle between 2.

FIG. 57 (F) shows an ordinary automobile, which includes a vehicle body 951, wheels 952, and a dashboard 953.
It has a light 954 and the like.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

(Embodiment 11)
In the present embodiment, an example of using the RF tag according to one aspect of the present invention will be described with reference to FIG. 56. RF tags have a wide range of uses, such as banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see Fig. 56 (A)), packaging containers (wrapping paper, etc.). Bottles, etc., see Fig. 56 (C)), recording media (DVDs, video tapes, etc., see Fig. 56 (B)), vehicles (bicycles, etc., see Fig. 56 (D)), personal belongings (bags, glasses, etc.) , Foods,
Plants, animals, human body, clothing, daily necessities, medical products containing chemicals and drugs, or electronic devices (
It can be used by being provided on an article such as a liquid crystal display device, an EL display device, a television device, or a mobile phone, or a tag attached to each article (see FIGS. 56 (E) and 56 (F)).

The RF tag 4000 according to one aspect of the present invention can be attached or embedded on the surface of the RF tag 4000.
It is fixed to the article. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF tag 4000 according to one aspect of the present invention realizes small size, thinness, and light weight, the design of the article itself is not impaired even after being fixed to the article. Further, an authentication function can be provided by providing an RF tag 4000 according to one aspect of the present invention on banknotes, coins, securities, bearer bonds, certificates, etc., and if this authentication function is utilized, Counterfeiting can be prevented. Further, by attaching the RF tag according to one aspect of the present invention to packaging containers, recording media, personal belongings, foods, clothing, daily necessities, electronic devices, etc., the efficiency of systems such as inspection systems can be improved. Can be planned. Further, even in vehicles, by attaching the RF tag according to one aspect of the present invention, it is possible to enhance the security against theft and the like.

As described above, by using the RF tag according to one aspect of the present invention for each of the applications listed in the present embodiment, the operating power including writing and reading of information can be reduced, so that the maximum communication distance can be lengthened. Is possible. Further, since the information can be retained for an extremely long period even when the power is cut off, it can be suitably used for applications in which the frequency of writing and reading is low.

This embodiment can be implemented in combination with at least a part thereof as appropriate with other embodiments described in the present specification.

It should be noted that the figure (which may be a part) described in one embodiment is another part of the figure, another figure (which may be a part) described in the embodiment, and / or one or more. By combining the figures (which may be a part) described in another embodiment of the above, more figures can be constructed.

It should be noted that, with respect to the contents not specified in the drawings and sentences in the specification, one aspect of the invention in which the contents are excluded can be configured. Alternatively, if a numerical range indicated by an upper limit value and a lower limit value is described for a certain value, the range can be narrowed arbitrarily or by excluding one point in the range. It is possible to specify one aspect of the invention excluding parts. These can, for example, specify that the prior art does not fall within the technical scope of one aspect of the invention.

As a specific example, it is assumed that a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it is possible to define as an invention that the circuit does not have a sixth transistor. Alternatively, it is possible to specify that the circuit does not have a capacitive element. Further, the invention can be configured by defining that the circuit does not have a sixth transistor such as having a particular connection structure. Alternatively, the invention can be constructed by defining that the circuit does not have a capacitive element having a specific connection structure. For example, it is possible to define the invention that the gate does not have a sixth transistor connected to the gate of the third transistor.
Alternatively, for example, it is possible to define the invention that the first electrode does not have a capacitive element connected to the gate of the third transistor.

As another specific example, regarding the properties of a substance, for example, "a film is an insulating film".
It is assumed that it is described. In that case, for example, it is possible to specify one aspect of the invention except that the insulating film is an organic insulating film. Alternatively, for example, it is possible to specify one aspect of the invention except that the insulating film is an inorganic insulating film. Alternatively, for example, it is possible to specify one aspect of the invention, except when the film is a conductive film. Alternatively, for example, it is possible to specify one aspect of the invention, except when the film is a semiconductor film.

As another specific example, it is assumed that a certain laminated structure is described as, for example, "a certain film is provided between the A film and the B film". In that case, it is possible to specify the invention, for example, except when the film is a laminated film having four or more layers. Alternatively, for example, it is possible to specify the invention except when a conductive film is provided between the A film and the film.

In addition, in this specification and the like, it is possible to take out a part of the figure or text described in one embodiment to form one aspect of the invention. Therefore, when a figure or a sentence describing a certain part is described, the content obtained by taking out the figure or the sentence of the part is also disclosed as one aspect of the invention, and constitutes one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistance elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operating methods, manufacturing methods. It is possible to take out a part of a drawing or text in which one or more of the above are described to form one aspect of the invention. For example, N (N)
Is an integer) of circuit elements (transistors, capacitive elements, etc.), and M (M is an integer, M <N) circuit elements (transistors, capacitive elements, etc.) are extracted from the circuit diagram. It is possible to construct one aspect of the invention. As another example, one aspect of the invention is constructed by extracting M layers (M is an integer and M <N) from a cross-sectional view having N layers (N is an integer). It is possible to do. As yet another example, one aspect of the invention is constructed by extracting M elements (M is an integer and M <N) from a flowchart composed of N elements (N is an integer). It is possible to do. As yet another example, some elements are arbitrarily extracted from the sentence "A has B, C, D, E, or F", and "A has B and E.""Has","A has E and F", "A has C, E and F"
Or, it is possible to construct one aspect of the invention, such as "A has B, C, D, and E."

In the present specification and the like, when at least one specific example is described in the figure or text described in one embodiment, it is easy for a person skilled in the art to derive a superordinate concept of the specific example. Understood by. Therefore, when at least one specific example is described in the figure or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention, and one of the inventions. It is possible to configure aspects. And it can be said that one aspect of the invention is clear.

In this specification, etc., at least the contents described in the figure (may be a part of the figure).
Is disclosed as one aspect of the invention, and it is possible to constitute one aspect of the invention. Therefore, if a certain content is described in the figure, the content is disclosed as one aspect of the invention even if it is not described by using a sentence, and can constitute one aspect of the invention. It is possible. Similarly, a figure obtained by taking out a part of the figure is also disclosed as one aspect of the invention, and it is possible to construct one aspect of the invention. and,
It can be said that one aspect of the invention is clear.

In this embodiment, the evaluation result of the oxide semiconductor film which is one aspect of the present invention will be described.

[Manufacturing method]
The silicon wafer was thermally oxidized to form a silicon oxide film having a thickness of 100 nm. Then, 100 nm of In-Ga-Zn oxide was formed as an oxide semiconductor film by a sputtering method. As the conditions of the sputtering method, the target is In-Ga: Zn = 1: 1: 1 (atomic number ratio) polycrystalline In-Ga-Zn oxide, the power supply is 0.5 kW (DC), and the substrate is used. The distance between the targets was 60 mm. In addition, argon and oxygen are used as the film forming gas, and
The respective flow rates were 30 sccm for argon and 15 sccm for oxygen. The pressure is 0.4
It was set to Pa. The substrate temperature was 170 ° C. for sample E1-1 and 300 ° C. for sample F1-1.

Next, heat treatment was performed. The heat treatment conditions were as follows: heat treatment was performed at 450 ° C. in a nitrogen atmosphere for 1 hour, and then heat treatment was performed in the same treatment room at 450 ° C. in an oxygen atmosphere for 1 hour.

[XRD evaluation]
Next, the result of the evaluation using the XRD apparatus will be described. The XRD device is a multifunctional thin film material evaluation X-ray diffractometer D8 DISCOVER Hybrid (manufactured by Bruker AXS).
Was used to evaluate each sample. FIG. 43 shows the analysis result by the Out-Of-Plane method. FIG. 43 (A) shows the results of sample E1-1, and FIG. 43 (B) shows the results of sample F1-1. A peak was observed in the vicinity of 2θ = 31 ° in all the samples. The peak was broad under the condition of forming a film at 170 ° C., and the peak tended to be sharper under the condition of forming a film at 300 ° C. Since this peak is _{assigned to the (009) plane of the crystal of InGaZnO 4} , it is suggested that the number of crystals of the oxide semiconductor film having c-axis orientation increases by increasing the film formation temperature.

[Evaluation of film density]
Next, the film density was measured. For evaluation of film density, XRR (X-ray reflectivity: X-ray R)
eflextomy) was used. The obtained film density was 6.18 [g] for sample E1-1.
/ Cm ³ ], sample F1-1 was 6.36 [g / cm ³ ]. A dense and good film was obtained under all conditions.

[Nanobeam electron diffraction]
Next, the sample E1-1 and the sample F1-1 were analyzed by nanobeam electron diffraction. "HF-2000" manufactured by Hitachi High-Technologies Corporation was used for the acquisition of electron diffraction. The acceleration voltage was 200 kV.

A transmitted electron diffraction pattern was obtained while scanning by moving the sample stage little by little on the upper surface of each sample having an oxide semiconductor film. Probe diameter is 1 nm as an electron beam
Nanobeam electron beam was used. In addition, the same measurement was performed at 3 points for each sample. That is, each sample was scanned a total of 3 times of scan1 to scan3.

Diffraction patterns were observed while scanning at a speed of 5 nm / sec, and moving images were acquired. next,
The diffraction pattern observed in the obtained moving image was converted into a still image every 0.5 seconds. The converted still image was analyzed and classified into three patterns: an nc-OS film pattern, a CAAC-OS film pattern, and a spinel-type crystal structure pattern. Table 3 shows the number of images classified into each pattern in Scan1 to Scan3 for Sample E1-1 and Sample F1-1. In addition, the results of scan1 of the electron diffraction pattern of sample E1-1 are shown in FIGS. 44 to 48, in which sample F1 is shown.
The results of scan1 of -1 are shown in FIGS. 49 to 53. Further, among the results of electron diffraction shown in FIGS. 44 to 48, those judged to be the pattern of the CAAC-OS film are shown by enclosing them with broken lines. Further, among the results of electron diffraction shown in FIGS. 49 to 53, those judged to be the pattern of the nc-OS film are shown by enclosing them with broken lines.

In sample E1-1, the nc ratio was as high as 90% or more. It was found that the nc ratio was further increased by lowering the film formation temperature. In addition, in any sample, n
The sum of the c ratio and the CAAC ratio was 100%.

In this example, the film density evaluation result of In-Ga-Zn oxide and TDS (Thermal)
Depression Spectroscopy: The result of the analysis is shown.

An In-Ga-Zn oxide was formed on a quartz substrate that had been washed in advance by a sputtering method. The target is In-: Ga: Zn = 1: 1: 1 (atomic number ratio) polycrystalline In-
Ga-Zn oxide was used. The film forming conditions are that the power supply power is 100 W, argon and oxygen are used as the film forming gas, and the flow rate of oxygen gas is 2 with respect to the total flow rate of argon gas and oxygen gas.
The flow rate was adjusted to be%. The pressure was 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. Table 4 shows the film forming conditions and the film density. sampleB and sample
D was heat-treated at 450 ° C. after forming an In-Ga-Zn oxide film by a sputtering method. An XRR was used to evaluate the film density. As shown in Table 4, the density of sampleC was as high as 6 [g / cm ³ ] or more.

Next, TDS analysis was performed on sampleA to sampleD. Molecular weight is 1
The amount of degassing in 8 is shown in FIGS. 54 (A) and 54 (B). Degassing molecular weight 18 is believed to be derived from H _{2 O.} The release amount was large in sample A, and decreased in the heat-treated sample B. It is considered that in sample C having a high film density, the amount of gas released is small and the amount of water contained in the film is small even without heat treatment.

Next, for sampleA to sampleD, the crystal size by electron beam irradiation (
The change in crystal size) was evaluated. The crystal size was calculated by observing the cross section using TEM. FIG. 55 shows the results of evaluating the relationship between the cumulative irradiation amount and the crystal size by performing electron beam irradiation using TEM. In sample A, the crystals tended to grow larger with each electron beam irradiation. Here, the crystal size before electron beam irradiation may be set to a value in which the cumulative irradiation amount is 0 [e ⁻ / nm ^{2] in the approximate line shown in FIG. 55, for example.} In the heat-treated sample B, the change in crystal size was small. In addition, sampleC and sample with high film density
In D, the cumulative amount of electron beam irradiation is ^{4.2 × 10 8 [e - /} nm 2] significant changes in the size of the crystal in the range of up was observed.

In this example, the stability of the oxide semiconductor film was evaluated. Sample 1, Sample 2 and Sample 3
The production method of is shown below.

First, on a quartz substrate, In-Ga-Z having a thickness of 100 nm was subjected to the RF sputtering method.
n Oxide is formed. The target is polycrystalline In-Ga-Zn oxide (In: Ga: Z)
n = 1: 1: 1 [atomic number ratio]) was used. The film-forming gas was 2 sccm for oxygen gas and 98 sccm for argon gas. The electric power was set to 100 W. The substrate temperature at the time of film formation was room temperature. Here, the film forming pressure of Sample 1 was set to 0.4 Pa. The film forming pressure of Sample 2 was 1.0 Pa.

In sample 3, In-Ga having a thickness of 100 nm was subjected to a DC sputtering method on a quartz substrate.
-Zn oxide is formed. The target is In-Ga-Zn oxide (In: Ga: Zn =
1: 1: 1 [atomic number ratio]) was used. The film-forming gas was 10 sccm for oxygen gas and 20 sccm for argon gas. The electric power was set to 200 W. The substrate temperature at the time of film formation was 300 ° C. The film forming pressure was 0.4 Pa.

Next, the heat treatment was carried out for 1 hour in an atmosphere containing oxygen and nitrogen. Heat treatment temperature is 25
Five conditions were set: 0 ° C, 300 ° C, 350 ° C, 400 ° C, and 450 ° C. Then, the film densities of Sample 1, Sample 2, and Sample 3 were measured, including the condition that the heat treatment was not performed. For the measurement of film density, XRR by Bruker AXS X-ray diffractometer D8 ADVANCE
Was used. The result of sample 1 is shown in FIG. 58 (A), the result of sample 2 is shown in FIG. 58 (B), and the result of sample 3 is shown in FIG. 58 (C). The horizontal axis is the temperature of the heat treatment. The film density of sample 1 is 5.9 g / c
It was m ³ to 6.1 g / cm ³ . The film density of sample 2 is 5.6 g / cm ³ to 5.8 g /
It was in the range of cm ^3. The film density of Sample 3 was in the range of ^{6.2 g / cm 3} to 6.4 g / cm ^3.

Next, Sample 1, Sample 2, and Sample 3 were etched with an aqueous solution obtained by diluting phosphoric acid 100-fold with pure water. Then, the etching rate was measured by measuring the thickness before and after etching. The result of sample 1 is shown in FIG. 59 (A), the result of sample 2 is shown in FIG. 59 (B), and the result of sample 3 is shown in FIG. 59 (C). It was found that the higher the heat treatment temperature of Sample 1 and Sample 2, the lower the etching rate. It was found that the difference in sample 3 depending on the temperature of the heat treatment was small. In addition, the sample 1 that has not been heat-treated is better than the sample 2 that has been heat-treated.
It was found that the etching rate was low. Further, it was found that the etching rate of the sample 3 not subjected to the heat treatment was lower than that of the sample 1 subjected to the heat treatment.

Next, Sample 1, Sample 2, and Sample 3 were subjected to TDS analysis, and the amount of degassed (water) released having a mass-to-charge ratio of 18 was measured. For TDS analysis, the temperature-temperature desorption analyzer TDS-12 manufactured by Denshi Kagaku Co., Ltd.
00 was used. The result of sample 1 is shown in FIG. 60 (A), the result of sample 2 is shown in FIG. 60 (B), and sample 3 is shown.
The result of is shown in FIG. 60 (C). It was found that the higher the heat treatment temperature of Sample 1, Sample 2, and Sample 3, the smaller the amount of degassing with a mass-to-charge ratio of 18. Further, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in the sample 1 not subjected to the heat treatment than in the sample 2 subjected to the heat treatment. Further, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in the sample 3 not subjected to the heat treatment than in the sample 1 subjected to the heat treatment.

Next, the hydrogen concentrations of Sample 1 and Sample 2 were measured. The hydrogen concentration was measured by SIMS.
As SIMS, IMS 7fR manufactured by CAMECA was used. The results of Sample 1 are shown in FIGS. 61 (A) and 68 (A), and the results of Sample 2 are shown in FIGS. 61 (B) and 68 (B). here,
In FIGS. 68 (A) and 68 (B), the horizontal axis shows the depth from the film surface, and the vertical axis shows the hydrogen concentration. Further, FIGS. 61 (A) and 61 (B) show average values of hydrogen concentrations from a depth of 10 nm to 60 nm. Further, in FIGS. 68 (A) and 68 (B), after the region where the hydrogen concentration suddenly changes near a depth of 80 nm, the quartz substrate was measured without the In-Ga-Zn oxide film remaining. It may be. Further, in the region of less than 10 nm, it may be affected by the surface condition. Therefore, the hydrogen concentration of the In-Ga-Zn oxide film is, for example, a depth of 10.
It is preferably expressed as an average value from nm to 60 nm. It was found that the higher the heat treatment temperature of Sample 1 and Sample 2, the lower the hydrogen concentration. Further, it was found that the hydrogen concentration of the sample 1 not subjected to the heat treatment was lower than that of the sample 2 subjected to the heat treatment.

Next, changes in crystal size due to heat treatment of Sample 1, Sample 2, and Sample 3 were measured by TEM. The crystal size is indicated by an average value of 20 to 45 points. As the TEM, a Hitachi transmission electron microscope H-9000 NAR was used. The result of sample 1 is shown in FIG. 62 (A), and the result of sample 2 is shown in FIG.
The results of 2 (B) and sample 3 are shown in FIG. 62 (C). It was found that the crystal size of Sample 1 was about 1.4 nm regardless of the temperature of the heat treatment. Sample 2 had a crystal size of about 1.2 nm when it was not heat-treated (see FIG. 67), but grew to about 1.3 nm by heat treatment at 250 ° C., and was further heated at 300 ° C. It grew to about 1.6 nm by the treatment. In addition, no change was observed in the crystal size in the range of 300 ° C. to 450 ° C. Also, in sample 3, the crystal size is 1.5 to 1.6 nm regardless of the heat treatment temperature.
Met.

Next, changes in crystal size of Sample 1, Sample 2, and Sample 3 due to electron beam irradiation were measured by TEM. The result of sample 1 is shown in FIG. 63 (A), the result of sample 2 is shown in FIG. 63 (B), and the result of sample 3 is shown in FIG. 63 (C). In Sample 1 and Sample 3, almost no change in crystal size was observed regardless of the temperature of the heat treatment and also by electron beam irradiation. Sample 2 showed an increase in crystal size due to electron beam irradiation. Moreover, this tendency became more remarkable as the temperature of the heat treatment was lowered.

Looking at the change in crystal size due to heat treatment and the change in crystal size due to electron beam irradiation,
It can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When Sample 1, Sample 2 and Sample 3 are compared with the above-mentioned structural classification, Sample 1 becomes an nc-OS film, Sample 2 becomes an a-like OS film, and Sample 3 becomes CAAC-OS.

As described above, the nc-OS film has a higher film density, a lower etching rate, less degassing of water, and a lower hydrogen concentration than the a-like OS film. Further, the difference cannot be filled by the heat treatment after the film formation. That is, it is important to use an oxide semiconductor film which is an nc-OS film at the time of film formation for the transistor.

In this example, the localization level of the nc-OS film was evaluated. Evaluation of localization level is CPM (Con)
It was performed by the start photocurrent measurement) measurement.

For CPM measurement, the gate electrode (tungsten) on the glass substrate and nc- on the gate electrode
The OS film, the gate insulator (silicon oxide) between the gate electrode and the nc-OS film, and n
A pair of electrodes in contact with the c-OS film (a laminate formed in the order of tungsten, aluminum and titanium) and an insulator on the nc-OS film and a pair of electrodes (silicon oxide and silicon nitride in that order) were formed. (Laminate), and a sample having the above was prepared. In addition, nc-OS
The film was formed to a thickness of 35 nm by the AC sputtering method. The target is In
-Ga-Zn oxide (In: Ga: Zn = 1: 1: 1.2 [atomic number ratio]) was used. The film-forming gas was 10% by volume of oxygen gas and 90% by volume of argon gas. Also, the power is 2
.. It was set to 5 kW. The substrate temperature at the time of film formation was room temperature. The film forming pressure was 0.6 Pa.

Next, the prepared sample was heat-treated. The heat treatment was carried out in a nitrogen atmosphere for 1 hour, and then further in an atmosphere containing oxygen and nitrogen for 1 hour.

In CPM measurement, the amount of light radiated to the sample surface between the terminals is adjusted so that the light current value becomes constant while a voltage is applied between a pair of electrodes provided in contact with the nc-OS film, and the amount of irradiating light is used. Derivation of the absorption coefficient. Here, the absorption coefficient was derived at each wavelength. In CPM measurement, the absorption coefficient in energy (converted from wavelength) according to the localized level density increases. By multiplying this increase in the absorption coefficient by a constant, the localized level density of the sample can be derived.

Further, by removing the light absorption (arback tail) caused by the band tail from the curve of the light absorption spectrum, the absorption coefficient α due to the localized level can be calculated from the following equation.

α = ∫ [(α (E) -α _u ) / E] dE

Here, E represents the energy, α (E) represents the absorption coefficient at each energy, and α _u represents the absorption coefficient by the arbor tail.

The inclination of the arbuck tail is called arbuck energy. It can be said that the lower the arback energy is, the less defects there are, and the more ordered the semiconductor film is, the steeper the slope of the tail (hem) of the level at the band end of the valence band.

FIG. 64 shows the result of fitting the absorption coefficient (dotted line) measured by the spectrophotometer and the absorption coefficient (solid line) measured by the CPM in an energy range equal to or larger than the energy gap of the oxide semiconductor film. FIG. 64 (A) shows the result of the sample heat-treated at 300 ° C. after the film formation, and FIG. 64 (B) shows the result of the sample heat-treated at 400 ° C. after the film formation.
C) shows the results of the samples heat-treated at 450 ° C. after the film formation. Arbuck energies obtained from the absorption coefficient measured by CPM are 72.65 meV and 69, respectively.
.. It was 45 meV and 70.32 meV.

Further, in FIG. 64, the background (fine dotted line) was subtracted from the absorption coefficient derived by the CPM measurement, and the integrated value of the absorption coefficient was derived. The results are shown in FIG. The absorption coefficients by localization level are 6.27 x 10 ^-1 cm ^-1 and 4.19 x 10 ^-1 cm ^-1 and 2.29, respectively.
It was × 10 ^-1 cm ^-1 . The relationship between the heat treatment temperature and the absorption coefficient is shown in FIG. FIG. 66
Therefore, it can be seen that the higher the heat treatment temperature, the smaller the absorption coefficient, and therefore the smaller the localized level density.

11 Region 12 Region 13 Region 14 Region 15 Region 16 Region 21 Horizontal wire 22 Horizontal wire 23 Vertical wire 50 Substrate 51 Insulation film 100 Transistor 101 Semiconductor layer 101a Insulation layer 101b Semiconductor layer 101c Insulation layer 102 Gate insulating film 103 Gate electrode 104a Conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 116 Insulating film 123 Plug 124 Wiring 130 Transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating film 137 Insulating film 138 Insulating film 139 Plug 140 Plug 143 Conductive layer 150 Capacitive element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 Transistor 164 Plug 165 Plug 166 Wiring 171a Low resistance layer 171b Low resistance layer 176a Region 176b Region 181 Element separation layer 190 Transistor 191 Transistor 201 Semiconductor layer 201a Semiconductor layer 201b Semiconductor layer 202 Gate insulating film 202a Gate insulating film 202b Gate insulating film 203a Gate electrode 203b Electrode 204a Conductive layer 204b Conductive layer 214 Insulating film 215 Insulating film 216 Insulating film 218 Insulating film 251 Conductive layer 281 Hard mask 321 Plug 322 Plug 324 Area 501 Pixel circuit 502 Pixel part 504 Drive circuit part 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal part 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 57 Light emitting element 610 Electronic gun room 612 Optical system 614 Sample room 616 Optical system 618 Camera 620 Observation room 622 Film room 624 Electronic 632 Fluorescent plate 700 Display device 701 Board 702 Pixel part 704 Source driver circuit part 705 Board 706 Gate driver circuit part 708 FPC terminal part 710 Signal Wire 711 Wiring part 712 Sealing material 716 FPC
730 Insulation film 732 Encapsulation film 734 Insulation film 736 Colored film 738 Light-shielding film 750 Transistor 752 Transistor 760 Connection electrode 764 Insulation film 766 Insulation film 768 Insulation film 770 Flattening insulation film 772 Conductive layer 774 Conductive layer 775 Liquid crystal element 77 Liquid crystal layer 778 Structure 780 Anisometric conductive layer 782 Light emitting element 784 Conductive layer 786 EL layer 788 Conductive layer 790 Capacitive element 790a Capacitive element 790b Capacitive element 800 RF tag 801 Communicator 802 Antenna 803 Radio signal 804 Antenna 805 Rectification circuit 806 Constant voltage circuit 807 Demodition circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM
901 Housing 902 Housing 903 Display 904 Display 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display 914 Display 915 Connection 916 Operation key 921 Storage 922 Display 923 Keyboard 924 Pointing device 931 Housing 932 Cooling room door 933 Freezing room door 941 Housing 942 Housing 943 Display 944 Operation key 945 Lens 946 Connection 951 Body 952 Wheel 953 Dashboard 954 Light 2100 Transistor 2200 Transistor 4000 RF tag 5100 Pellet 5100a Pellet 5100b Pellet 5101 Ion 5120 Substrate 5130 Target 8000 Display Module 8001 Top Cover 8002 Bottom Cover 8003 FPC
8004 touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (1)

A display device having a source driver, a gate driver, and a pixel portion on a substrate.
Has a transistor and
The transistor has an oxide semiconductor layer and has an oxide semiconductor layer.
The oxide semiconductor layer has indium and zinc, and has at least one of aluminum, gallium, yttrium, or tin as the element M.
The ratio of the number of atoms of indium, element M and zinc contained in the oxide semiconductor layer satisfies indium: element M: zinc = x: y: z.
The x, the y, and the z are the first coordinate (x: y: z = 8: 14: 7) and the second coordinate in the equilibrium state diagram having the three elements of indium, element M, and zinc as apex. Coordinates (x: y: z = 2: 4: 3), third coordinates (x: y: z = 2: 5: 7), and fourth coordinates (x: y: z = 51: 149: 300), the fifth coordinate (x: y: z = 46: 288: 833), the sixth coordinate (x: y: z = 0: 2: 11), and the seventh coordinate (x: y). : Z = 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the first coordinate in order, the number of atoms in the range connected by a line segment. The range includes the first to sixth coordinates and does not include the seventh and eighth coordinates.
The electron diffraction pattern observed by irradiating the surface to be formed of the oxide semiconductor layer with an electron beam having a full width at half maximum of the probe diameter of 1 nm is a pattern in which the spots are not symmetrically arranged, or the spots are circular. A display device that is a pattern arranged to draw.

Images