KR20220146394A - Semiconductor film, semiconductor device, display device, module, and electronic device - Google Patents

Abstract

Good electrical characteristics are applied to a semiconductor device. With the use of an electron beam having a half-value width of a probe diameter of 1 nm, a surface to be formed of an oxide semiconductor film is irradiated with the electron beam while relatively moving the position of the film and the position of the electron beam, and thus a plurality of electron diffraction patterns are observed. The plurality of electron diffraction patterns have 50 or more electron diffraction patterns observed at places different from each other. The sum of the ratio that the 50 or more electron diffraction patterns include a first electron diffraction pattern and the ratio that the electron diffraction patterns include a second electron diffraction pattern is 100%. The ratio that the electron diffraction patterns include the first electron diffraction pattern is 50% or more. The first electron diffraction pattern has an observation point having no symmetry or a plurality of observation points arranged so as to draw a circle, and the second electron diffraction pattern has an observation point located at the vertex of a hexagon.

Description

A semiconductor film, a semiconductor device, and a display device, a module, and an electronic device

The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, machine, article, or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

In addition, in this specification etc., a semiconductor device refers to the general device which can function by using semiconductor characteristics. A transistor and a semiconductor circuit are one form of a semiconductor device. In addition, an arithmetic device, a memory device, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

The physical properties of oxides containing indium and zinc are interesting and have been extensively studied (Non-Patent Document 1 and Non-Patent Document 2). In Non-Patent Document 1, it is described that a homologous gas phase represented by In _1-x Ga _1+x O ₃ (ZnO) _m (x is a number satisfying -1≤x≤1, m is a natural number) exists. . Also described is the solid solution range of the homologous gas phase. For example, when powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and calcined at 1350° C., the solid solution capacity of the same gas phase when m=1 is that x is -0.33 to 0.08. There is a description, and there is a description that x is -0.68 to 0.32 in the solid solution region of the homologous gas phase in the case of m=2.

Moreover, as a compound which has a spinel crystal structure, the compound represented by AB ₂ O ₄ (A and B is a metal) is known. In addition, in Non-Patent Document 1, an example of In _x Zn _y Ga _z O _w is shown, and x, y and z are the compositions in the vicinity of ZnGa ₂ O ₄ , that is, x, y and z are (x, y, z) = (0). , 1, 2), it is described that a spinel crystal structure is easily formed or mixed.

Also, a technique for constructing a transistor using a semiconductor material is attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are attracting attention as other materials.

For example, a technique for fabricating a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Literature 1 and Patent Literature 2).

Moreover, in recent years, with the performance improvement, miniaturization, or weight reduction of an electronic device, the request|requirement of the integrated circuit which integrated semiconductor elements, such as a miniaturized transistor, at high density is increasing.

Japanese Laid-Open Patent Publication No. 2007-123861 Japanese Laid-Open Patent Publication No. 2007-96055

M. Nakamura, N. Kimizuka, and T. Mohri, 「The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃」, J. Solid State Chem., 1991, vol.93, pp.298-315 M. Nespolo, A. Sato, T. Osawa, and H. Ohashi, 「Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. X-ray Diffraction Study of 20kb Single Crystal and 50kb Twin by Reticular Merohedry” Cryst. Res. Technol., 2000 Vol.35, pp151-165

One aspect of the present invention makes it one of the problems to provide a semiconductor device with good electrical characteristics.

Alternatively, one of the problems is to provide a highly reliable semiconductor device.

Alternatively, one of the problems is to provide a good transistor with little variation in characteristics. Another object is to provide a semiconductor device having a memory element with good retention characteristics. Alternatively, one of the problems is to provide a semiconductor device suitable for miniaturization. Another object is to provide a semiconductor device having a reduced circuit area. Alternatively, one of the problems is to provide a semiconductor device having a novel configuration.

In addition, description of these subjects does not impede the existence of another subject. In addition, one aspect of this invention assumes that it is not necessary to solve all these problems. In addition, subjects other than these will become clear spontaneously from descriptions, such as a specification, drawing, a claim, and it is possible to extract the subject other than these from descriptions, such as a specification, drawings, and a claim.

One embodiment of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein element M is at least one element selected from aluminum, gallium, yttrium, or tin, and is composed of indium, element M and zinc. The atomic ratio satisfies indium:element M:zinc=x:y:z, and x, y and z are the first coordinates (x :y:z=8:14:7), the second coordinate (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), and the second coordinate (x:y:z=2:4:3) 4 coordinates (x:y:z=51:149:300), 5th coordinate (x:y:z=46:288:833), and 6th coordinate (x:y:z=0:2:11) ), the seventh coordinates (x:y:z=0:0:1), the eighth coordinates (x:y:z=1:0:0), and the first coordinates are sequentially connected by a line segment. Formation of an oxide semiconductor film by using an electron beam having an atomic ratio within the range, including the first coordinate to the sixth coordinate, not including the seventh coordinate and the eighth coordinate, and having a probe diameter half-width of 1 nm When a plurality of electron diffraction patterns are observed by irradiating an electron beam while relatively moving the position of the oxide semiconductor film and the position of the electron beam relative to the surface, the plurality of electron diffraction patterns are 50 or more observed at different locations. It has an electron diffraction pattern, and among 50 or more electron diffraction patterns, the sum of the ratio having the first electron diffraction pattern and the ratio having the second electron diffraction pattern is 100%, and the first electron diffraction pattern has no symmetry The second electron diffraction pattern is an oxide semiconductor film having observation points, or a plurality of observation points arranged in a circle, and having observation points located at the vertices of a hexagon.

Alternatively, in one embodiment of the present invention, a plurality of electron beams are irradiated while relatively moving the position of the oxide semiconductor film and the position of the electron beam with respect to the surface to be formed of the oxide semiconductor film using an electron beam having a probe diameter of half width of 1 nm. In the case of observing the electron diffraction pattern of , the sum of the proportions having the second electron diffraction pattern is 100%, the proportion having the first electron diffraction pattern is 50% or more, and the first electron diffraction pattern is an observation point having no symmetry or arranged in a circle The second electron diffraction pattern is an oxide semiconductor film having observation points positioned at the vertices of a hexagon.

Alternatively, one embodiment of the present invention is an oxide semiconductor film represented by an atomic ratio of In:M(Al, Ga, Y, or Sn):Zn=x:y:z, with coordinates x:y:z=1: In the equilibrium diagram with 0:0, coordinates x:y:z=0:1:0, and coordinates x:y:z=0:0:1 as vertices, the first coordinate (x:y:z= 8:14:7), the second coordinate (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), and the fourth coordinate (x: y:z=51:149:300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh The coordinates (x:y:z=0:0:1), the eighth coordinates (x:y:z=1:0:0), and the first coordinates are within a range connected by a line segment in order, and the oxide By relatively moving the position of the oxide semiconductor film and the position of the electron beam having a half width at half maximum width of 1 nm with respect to the surface to be formed of the semiconductor film, 50 or more electron diffraction patterns are observed at different locations, and 50 or more electron diffraction patterns are , at least one of an electron diffraction pattern having a plurality of asymmetrically arranged spots, an electron diffraction pattern having a plurality of spots arranged in a circle, and an electron diffraction pattern having spots arranged at vertices of a hexagon, is an oxide semiconductor film characterized in that it includes the first to sixth coordinates and does not include the seventh and eighth coordinates.

Further, in the above configuration, the oxide semiconductor film has indium, elements M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin, and the atomic ratio of indium, element M and zinc is, Indium:element M:zinc = x:y:z, and x, y, and z are indium, element M, and an equilibrium state diagram with three elements as vertices, the first coordinate (x:y:z =8:14:7), the second coordinate (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), and the fourth coordinate (x :y:z=51:149:300), the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), An atom within a range in which the seventh coordinate (x:y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by a line segment With the defense, it is preferable that the range includes the first coordinate to the sixth coordinate, and not the seventh coordinate and the eighth coordinate.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein the oxide semiconductor film has a plurality of randomly arranged crystal portions, and the average lengthwise diameter of the plurality of crystal portions is 1 nm or more. It is an oxide semiconductor film of 3 nm or less.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein element M is an element selected from at least one of aluminum, gallium, yttrium, and tin, indium, element M, and zinc The atomic ratio of indium:element M:zinc=x:y:z is satisfied, and x, y and z are the first coordinates ( x:y:z=8:14:7), the second coordinate (x:y:z=2:4:3), and the third coordinate (x:y:z=2:5:7), The fourth coordinate (x:y:z=51:149:300), the fifth coordinate (x:y:z=46:288:833), and the sixth coordinate (x:y:z=0:2:11) ), the seventh coordinate (x:y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are sequentially connected by line segments having an atomic ratio within a range, the range includes the first coordinate to the sixth coordinate, and does not include the seventh coordinate and the eighth coordinate, and the density of the oxide semiconductor film is 90% of the density of a single crystal having the same atomic ratio It is an oxide semiconductor film which is more than one.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, element M, and zinc, wherein element M is an element selected from at least one of aluminum, gallium, yttrium, and tin, and the oxide semiconductor film is randomly It has a plurality of crystal portions to be arranged, the plurality of crystal portions do not have orientation, and has crystals of 1 nm or more and 3 nm or less with a diameter in the longitudinal direction of the plurality of crystal portions, and the density of the oxide semiconductor film is 90 of the density of single crystals having the same atomic ratio % or more of the oxide semiconductor film.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, wherein the oxide semiconductor film has a plurality of crystal portions, the plurality of crystal portions do not have orientation, and the average of the longitudinal diameters of the plurality of crystal portions Silver is 1 nm or more and 3 nm or less, and the density of an oxide semiconductor film is an oxide semiconductor film whose density is 5.7 g/cm<3> or more and 6.49 g/cm<3> or less. Moreover, in the said structure, it is preferable that the density of an oxide semiconductor film is 90% or more of the density of the single crystal which has the same atomic ratio.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, wherein the oxide semiconductor film has a plurality of randomly arranged crystal portions, the plurality of crystal portions do not have orientation, and the length of the plurality of crystal portions The average A [nm] of the directional diameter is 1 nm or more and 3 nm or less, and the electron beam energy is 1×10 ⁷ [e ^- /nm2] or more and 4×10 ⁸ [e ^- /nm2] after irradiation, crystal The average B [nm] of the negative longitudinal diameter is an oxide semiconductor film larger than A×0.7 and smaller than A×1.3.

In addition, in the above structure, the oxide semiconductor film is formed by sputtering, and the target used for the sputtering method has indium, element M, and zinc, and the atomic ratio of indium, element M, and zinc that the target has is indium. : Element M: Zinc = a: b: c, and a, b, and c are the first coordinates (a: b: c=8:14:7), the second coordinate (a:b:c=2:4:3), the third coordinate (a:b:c=1:2:5.1), and the fourth coordinate ( a:b:c=1:0:1.7), the fifth coordinate (a:b:c=8:0:1), and the sixth coordinate (a:b:c=6:2:1); It is preferable that the first coordinates have an atomic ratio within a range in which the first coordinates are sequentially connected by line segments, and the range includes the first coordinates to the sixth coordinates.

Alternatively, one embodiment of the present invention is a semiconductor device having the oxide semiconductor film described above. In addition, in the above configuration, it has a first conductive layer, a first insulating film in contact with an upper surface and a side surface of the first conductive layer, and a pair of electrodes in contact with the upper surface of the oxide semiconductor film, wherein the oxide semiconductor film is in contact with the upper surface of the first insulating film. It is desirable to have an area. Further, in the above configuration, the first conductive layer, the first insulating film in contact with the upper surface and the side surface of the first conductive layer, the second insulating film in contact with the upper surface of the oxide semiconductor film, the upper surface of the oxide semiconductor film, and the upper surface and the side surface of the second insulating film It is preferable that the oxide semiconductor film has a region in contact with the upper surface of the first insulating film. Moreover, in the said structure, it is preferable to have a 2nd oxide film in contact with the upper surface of an oxide semiconductor film. Moreover, in the said structure, it is preferable that the electron affinity of the oxide which an oxide semiconductor film has is larger than the electron affinity of the oxide which a 2nd oxide film has. Further, in the above configuration, the second oxide film has indium, elements M, and zinc, and the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin, and indium, element M and The atomic ratio of zinc is expressed as indium:element M:zinc=x ₂ :y ₂ :z ₂ , where (x ₂ :y ₂ :z ₂ ) has three elements as indium, element M, and zinc as its vertices. In the equilibrium diagram, the first coordinate (8:14:7), the second coordinate (2:4:3), the third coordinate (2:5:7), and the fourth coordinate (51:149:300) ), the fifth coordinate (1:4:10), the sixth coordinate (1:1:4), the seventh coordinate (2:2:1), and the first coordinate are sequentially connected by a line segment It is preferable that the atomic ratio is within one range, and the range includes the first coordinates to the seventh coordinates.

Alternatively, one embodiment of the present invention is a display device including the semiconductor device described above and a display element.

Alternatively, one embodiment of the present invention is a module including the semiconductor device described above or the display device described above and an FPC.

Alternatively, one embodiment of the present invention is an electronic device including the semiconductor device described above, the display device described above, or the module described above, and a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, good electrical characteristics can be provided to a semiconductor device. In addition, it is possible to provide a semiconductor device with high reliability.

Also, it is possible to provide a transistor with little non-uniformity. Further, it is possible to provide a semiconductor device having a memory element having good holding characteristics. Further, it is possible to provide a semiconductor device suitable for miniaturization. Further, it is possible to provide a semiconductor device having a reduced circuit area. In addition, a semiconductor device having a novel configuration can be provided. Note that the description of these effects does not prevent the existence of other effects. In addition, one aspect of this invention does not necessarily have to have all these effects. In addition, effects other than these will become apparent by itself from descriptions, such as a specification, drawing, a claim, and it is possible to extract effects other than these from descriptions, such as a specification, drawings, and a claim.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure explaining the atomic ratio of the oxide film which concerns on one Embodiment of this invention.
Fig. 2 is a view for explaining the atomic ratio of an oxide film according to one embodiment of the present invention;
Fig. 3 is a diagram for explaining an atomic ratio;
Fig. 4 is a view for explaining the atomic ratio of an oxide film according to one embodiment of the present invention;
It is a figure explaining the atomic ratio of the target which concerns on one Embodiment of this invention.
6 is a diagram for explaining an atomic ratio;
7 is a diagram showing a nanobeam electron diffraction pattern of an oxide semiconductor film, and a diagram showing an example of a transmission electron diffraction measuring apparatus;
Fig. 8 is a diagram showing the results of analysis by the nc-OS X-ray diffraction apparatus.
Fig. 9 is a diagram showing an electron diffraction pattern of an nc-OS.
FIG. 10 is a diagram for explaining a crystal of InGaZnO ₄ .
Fig. 11 is a diagram showing a band structure of a part of a transistor according to one embodiment of the present invention;
12 is a diagram showing an example of a transistor according to one embodiment of the present invention.
Fig. 13 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 14 is a diagram showing an example of a transistor according to one embodiment of the present invention;
15 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 16 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 17 is a diagram showing Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS.
Fig. 18 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of the CAAC-OS.
Fig. 19 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of the CAAC-OS.
Fig. 20 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS.
Fig. 21 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS.
Fig. 22 is a graph showing the pellet sizes observed by Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS and their frequencies;
Fig. 23 is a diagram showing the relationship between the atomic ratio of the target and the atomic ratio of the oxide semiconductor film;
It is a schematic diagram explaining the film-forming model of nc-OS, and the figure which shows a pellet.
25 is a schematic diagram for explaining a film forming apparatus;
26 is a block diagram and a circuit diagram illustrating a display device;
27 is a diagram of a display module, according to an embodiment;
28 is a configuration example of an RF tag according to the embodiment;
Fig. 29 is a diagram showing an example of a transistor;
Fig. 30 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 31 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 32 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 33 is a diagram showing an example of a transistor according to one embodiment of the present invention;
Fig. 34 is a top view showing one form of a display device;
Fig. 35 is a cross-sectional view showing one form of a display device;
Fig. 36 is a cross-sectional view showing one form of a display device;
37 is a circuit diagram, according to an embodiment.
Fig. 38 is a diagram showing an example of a semiconductor device according to one embodiment of the present invention;
Fig. 39 is a diagram showing a method of manufacturing a semiconductor device according to one embodiment of the present invention;
Fig. 40 is a diagram showing a method of manufacturing a semiconductor device according to one embodiment of the present invention;
Fig. 41 is a diagram showing a method of manufacturing a semiconductor device according to one embodiment of the present invention;
Fig. 42 is a diagram showing a method of manufacturing a semiconductor device according to one embodiment of the present invention;
43 is an XRD evaluation result of an oxide semiconductor film according to one embodiment of the present invention.
44 is an electron diffraction pattern of an oxide semiconductor film;
45 is an electron diffraction pattern of an oxide semiconductor film.
46 is an electron diffraction pattern of an oxide semiconductor film;
47 is an electron diffraction pattern of an oxide semiconductor film.
48 is an electron diffraction pattern of an oxide semiconductor film.
49 is an electron diffraction pattern of an oxide semiconductor film.
Fig. 50 is an electron diffraction pattern of an oxide semiconductor film;
51 is an electron diffraction pattern of an oxide semiconductor film.
52 is an electron diffraction pattern of an oxide semiconductor film;
Fig. 53 is an electron diffraction pattern of an oxide semiconductor film.
54 is a TDS analysis result of an oxide semiconductor film;
Fig. 55 is a diagram showing changes in crystals caused by electron beam irradiation;
56 is an example of use of an RF tag according to the embodiment;
57 is an electronic device, according to an embodiment.
58 is a diagram showing the film density of an oxide semiconductor film;
59 is a diagram showing an etching rate of an oxide semiconductor film;
Fig. 60 is a diagram showing an emission amount of a desorption gas of an oxide semiconductor film;
61 is a diagram showing the hydrogen concentration of an oxide semiconductor film;
62 is a diagram showing the crystal size of an oxide semiconductor film;
63 is a diagram showing the crystal size of an oxide semiconductor film;
Fig. 64 is a diagram showing a CPM measurement result of an oxide semiconductor film;
Fig. 65 is a diagram showing a CPM measurement result of an oxide semiconductor film;
Fig. 66 is a diagram showing a CPM measurement result of an oxide semiconductor film;
Fig. 67 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of an a-like OS;
68 is a diagram showing a hydrogen concentration in an oxide semiconductor film;

EMBODIMENT OF THE INVENTION Embodiment is demonstrated in detail using drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, this invention is limited to the description of embodiment shown below and is not interpreted.

In addition, in the configuration of the invention described below, the same reference numerals are commonly used between different drawings for the same parts or parts having the same functions, and repeated explanations thereof are omitted. In addition, when referring to the same function, hatch patterns are made the same, and a code|symbol in particular may not be attached|subjected.

In addition, in each drawing demonstrated in this specification, the size of each structure, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

In addition, ordinal numbers such as "first" and "second" in this specification and the like are added in order to avoid confusion of constituent elements, and are not limited to numbers.

In addition, in this specification, "parallel" means the state in which two straight lines are arrange|positioned at the angle of -10 degrees or more and 10 degrees or less. Accordingly, the case of -5° or more and 5° or less is also included. In addition, "approximately parallel" means the state in which two straight lines are arrange|positioned at the angle of -30 degrees or more and 30 degrees or less. In addition, "vertical" means the state in which two straight lines are arrange|positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. In addition, "approximately perpendicular|vertical" means the state in which two straight lines are arrange|positioned at the angle of 60 degrees or more and 120 degrees or less.

In addition, in this specification, when a crystal|crystallization is trigonal or a rhombohedral crystal, it is represented as a hexagonal system.

A transistor is a type of semiconductor element, and can realize amplification of current or voltage, and a switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT:Thin Film Transistor).

(Embodiment 1)

In this embodiment, an example of the oxide semiconductor film which is one aspect of this invention is demonstrated.

The oxide semiconductor film is roughly divided into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

A single crystal may be formed, for example, by firing at a high temperature of about 1000°C or higher. Therefore, it can be said that it is preferable from an industrial viewpoint because a semiconductor device can be manufactured more cheaply by using the non-single-crystal oxide semiconductor film which can be formed at a lower temperature.

It is so preferable that there are few grain boundaries of an oxide semiconductor film. By reducing the grain boundary, for example, carrier mobility can be increased. By fabricating a transistor using an oxide semiconductor film with few grain boundaries, for example, a transistor with high field-effect mobility can be realized in some cases. Although described in detail later, examples of the non-single crystal oxide semiconductor film having few grain boundaries include an nc-OS film and a CAAC-OS film.

On the other hand, the oxide semiconductor film may have a crystal of a spinel structure. When crystals of the spinel structure are mixed in the CAAC-OS film or the nc-OS film, a clear boundary portion (or grain boundary) may be formed. At the boundary, for example, carrier scattering increases and the carrier mobility may decrease. In addition, since the boundary portion is considered to be a path for the movement of impurities and to easily trap impurities, there is a fear that the impurity concentration of the oxide semiconductor film becomes high. In addition, when a conductive film is formed on an oxide semiconductor film, an element of the conductive film, for example, a metal, may diffuse into the boundary between the spinel and other regions. Therefore, it is more preferable that the oxide semiconductor film does not contain a spinel-type crystal structure or has a small amount.

Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When the oxide semiconductor contains indium, for example, carrier mobility (electron mobility) increases. Moreover, it is preferable when the oxide semiconductor contains the element M. The element M is preferably aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. However, as the element M, there may be cases in which a combination of a plurality of the above elements may be used. The element M is, for example, an element with high binding energy with oxygen. For example, it is an element with a higher binding energy with oxygen than indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Further, the oxide semiconductor preferably contains zinc. When an oxide semiconductor contains zinc, it may become easy to crystallize. Here, an oxide containing indium, element M, and zinc is denoted as an In-M-Zn oxide.

[About Atomic Defense]

The atomic ratio of the In-M-Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, is expressed as In:M:Zn=x:y:z. Preferred ranges of x, y and z will be described with reference to Figs.

Here, the atomic ratio of each element is demonstrated using FIG. 3 is a diagram showing the ranges of x, y and z when the atomic ratio of the elements X, Y, and Z is x:y:z in the X-Y-Z oxide film. On the other hand, the atomic ratio of oxygen is not described in FIG. 3 . In addition, FIG. 3 is sometimes called an equilibrium state diagram. 3A and 3B, an equilateral triangle having X, Y, and Z as vertices and a coordinate R (4:2:1) are shown as examples of coordinates. Here, each vertex represents an element X, Y, and Z, respectively. The value of each term in the atomic ratio is higher as the coordinates are closer to each vertex, and lower as the coordinates are farther away. Further, as shown in Fig. 3A, the value of each term in the atomic ratio is expressed by the length of the perpendicular from the coordinate to the opposite side of the vertex of the triangle. For example, if it is an element X, it is expressed by the length of the perpendicular 21 from the coordinate to the opposite side of the vertex X, that is, the side YZ. Therefore, in the coordinate R shown in FIG. 3, the atomic ratio of the element X, the element Y, and the element Z is the ratio of the lengths of the perpendicular 21, the perpendicular 22, and the perpendicular 23, that is, x:y:z=4. : indicates that it is 2:1. Also, the point where the straight line passing through the vertex X and the coordinate R intersects the side YZ is defined as γ. At this time, if the ratio of the length of the line segment Yγ to the length of the line segment γZ is Yγ:γZ, Yγ:γZ = (the number of atoms of the element Z): (the number of atoms of the element Y).

Further, as shown in Fig. 3B, three straight lines are drawn through the coordinate R and parallel to the three sides of the triangle, respectively. At this time, using the intersection of three straight lines and three sides, x, y, and z can be expressed as shown in Fig. 3B.

In Fig. 6, in the case where x:y:z satisfies the following formula in the In-M-Zn oxide film, the range is indicated by a broken line.

x:y:z=(1-α):(1+α):m(-1≤α≤1)

Here, FIG. 6 shows the case where m=1, 2, 3, 4, 5.

As described in Non-Patent Document 1, in In-M-Zn oxide, it is known that a homologous gas phase (homologous gas series) represented by InMO ₃ (ZnO) _m (m is a natural number) exists. Here, as an example, consider the case where the element M is Ga. It is known that the region indicated by a thick straight line in FIG. 6 can form a single phase solid solution when, for example, powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and fired at 1350° C. there is a composition It is known that the solid solution expands as the value of m increases, ie, the proportion of zinc increases.

In addition, the coordinates shown by the square symbols in FIG. 6 are as described in Non-Patent Document 1, for example, In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders are mixed and fired at 1350°C. In this case, it is a known composition that a spinel crystal structure tends to be mixed. As shown in FIG. 6 , when the composition near ZnGa ₂ O ₄ , that is, x, y, and z has values close to (x,y,z)=(0,2,1), the spinel crystal structure is It is described in Non-Patent Document 1 that is easy to form or to be mixed.

In the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention, it is preferable to increase the ratio of indium. In the In-M-Zn oxide film, mainly the s orbitals of metal atoms contribute to carrier conduction, and since more s orbitals are overlapped by increasing the indium content, the higher the indium content, the higher the carrier mobility. By fabricating a transistor using such a film for the channel region, it is possible to realize, for example, a transistor having high field-effect mobility. For example, x/y>0.5 is preferable, x/y≧0.75 is more preferable, and x/y≧1 is still more preferable. Further, (x+y)≥z is preferable.

Accordingly, x, y, and z preferably have an atomic ratio in the region 11 shown in Fig. 1, and more preferably have an atomic ratio in the region 12 shown in Fig. 2A. Here, the region 11 has a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate L (x:y:z=2:5:7), the fourth coordinate M (x:y:z=51:149:300), and the fifth coordinate N (x:y:z=46:288:833) and, the sixth coordinate O(x:y:z=0:2:11), the seventh coordinate P(x:y:z=0:0:1), and the eighth coordinate Q(x:y:z) =1:0:0) and the first coordinate K are in a region connected by a line segment in order. In addition, the region 11 includes a line segment connecting eight points. In addition, the coordinates P and Q are excluded from the region 11 , and other coordinates are included in the region 11 . In addition, the region 12 includes a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate L (x :y:z=2:5:7), the fourth coordinate S (x:y:z=1:0:1), and the fifth coordinate Q (x:y:z=1:0:0) , is within a region in which the first coordinate K is sequentially connected by line segments. In addition, the region 12 includes a line segment connecting five points. In addition, the coordinate Q is excluded from the area|region 12, and other coordinates are included in the area|region 12.

[Structure of oxide semiconductor film]

Next, the structure of the oxide semiconductor film will be described.

First, the CAAC-OS film will be described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis oriented crystal portions.

A plurality of crystal portions can be confirmed by observing a bright field image of the CAAC-OS film and a composite analysis image of a diffraction pattern (also referred to as a high-resolution TEM image) with a transmission electron microscope (TEM). On the other hand, a clear boundary between crystal parts, that is, a grain boundary (also called a grain boundary) cannot be confirmed even by a high-resolution TEM image. For this reason, in the CAAC-OS film, it can be said that the decrease in electron mobility due to the grain boundary hardly occurs.

When the high-resolution TEM image of the cross section of the CAAC-OS film is observed in a direction substantially parallel to the sample plane, it can be confirmed that the metal atoms are arranged in a layered manner in the crystal part. Each layer of metal atoms has a shape reflecting the unevenness of the surface (also referred to as a formed surface) or upper surface forming the film of the CAAC-OS film, and is arranged parallel to the formed surface or upper surface of the CAAC-OS film.

On the other hand, when the high-resolution TEM image of the plane of the CAAC-OS film is observed in a direction substantially perpendicular to the sample plane, it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

In addition, when electron diffraction is performed on the CAAC-OS film, spots (bright spots) showing orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of, for example, 1 nm or more and 30 nm or less is performed on the formed surface or top surface of the CAAC-OS film, spots are observed (Fig. 7). See (B).).

The high-resolution TEM image of the cross section and the high-resolution TEM image of the plane show that the crystal part of the CAAC-OS film has orientation.

In addition, most of the crystal portions included in the CAAC-OS film are sized to fit within a cube having one side less than 100 nm. Accordingly, the crystal portion included in the CAAC-OS film includes a case of a size that fits within a cube of less than 10 nm, less than 5 nm, or less than 3 nm on one side. However, one large crystal region may be formed by connecting a plurality of crystal portions included in the CAAC-OS film. For example, in a planar high-resolution TEM image, a crystal region of 2500 nm 2 or more, 5 µm 2 or more, or 1000 µm 2 or more is sometimes observed.

When the structure of the CAAC-OS film is analyzed using an X-ray diffraction (XRD) device, for example, the CAAC-OS film having an InGaZnO ₄ crystal is out-of-plane (out-of-plane). In the analysis by the plane) method, a peak may appear in the vicinity of 31° of the diffraction angle (2θ). Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, it can be confirmed that the crystal of the CAAC-OS film has a c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the surface to be formed or the top surface.

On the other hand, in analysis by an in-plane method in which X-rays are incident on the CAAC-OS film in a direction substantially perpendicular to the c-axis, a peak at 2θ may appear around 56°. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , if 2θ is fixed at around 56°, and analysis (φ scan) is performed while rotating the sample using the normal vector of the sample plane as the axis (φ axis), it is equivalent to the (110) plane Six peaks attributed to the crystal plane are observed. In contrast, in the case of the CAAC-OS film, a clear peak does not appear even when 2θ is fixed around 56° and φ scan is performed.

From the above points, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal portions, but it has a c-axis orientation and the c-axis is oriented in a direction parallel to the normal vector of the surface to be formed or the image. Able to know. Therefore, each layer of metal atoms arranged in a layered form confirmed by the high-resolution TEM observation of the cross section is a plane parallel to the ab plane of the crystal.

Further, the crystal portion is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface to be formed or the upper surface of the CAAC-OS film.

In addition, in the CAAC-OS film, the distribution of c-axis oriented crystal portions may not be uniform. For example, when the crystal portion of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region near the upper surface has a higher ratio of c-axis-oriented crystal portions than the region near the surface to be formed. there is Also, in the CAAC-OS film to which impurities are added, the impurity-added regions may be altered to form regions with different proportions of crystal portions partially oriented in the c-axis.

In addition, in the analysis by the out-of-plane method of the CAAC-OS film having an InGaZnO ₄ crystal, a peak may appear in the vicinity of 36° in 2θ in addition to the peak in the vicinity of 31°. The peak at which 2θ is around 36° indicates that a part of the CAAC-OS film contains crystals having no c-axis orientation. In the CAAC-OS film, it is preferable that 2θ shows a peak around 31° and does not show a peak at 2θ around 36°.

The CAAC-OS film is an oxide semiconductor film having a low impurity concentration. An impurity is an element other than the main component of an oxide semiconductor film, such as hydrogen, carbon, silicon, and a transition metal element. In particular, an element, such as silicon, which has a stronger bonding force with oxygen than a metal element constituting the oxide semiconductor film, by taking oxygen from the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film, thereby reducing crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained in the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, and a factor that reduces crystallinity do. In addition, impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

In addition, for example, oxygen vacancies in the oxide semiconductor film may become carrier traps or may become carrier generation sources by trapping hydrogen. The CAAC-OS film is an oxide semiconductor film having a low density of defect states. Specifically, it is less than 8×10 ¹¹ /cm 3 , preferably less than 1×10 ¹¹ /cm 3 , more preferably less than 1×10 ¹⁰ /cm 3 , and is an oxide semiconductor having a carrier density of 1×10 ^-9 /cm 3 or more. can do.

In addition, in the transistor using the CAAC-OS film, fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light are small.

Next, the polycrystalline oxide semiconductor film will be described.

In the polycrystalline oxide semiconductor film, crystal grains can be confirmed on a high-resolution TEM image. The crystal grains contained in the polycrystalline oxide semiconductor film have, for example, a particle diameter of 2 nm or more and 300 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in high-resolution TEM images in many cases. In addition, in the polycrystal oxide semiconductor film, a crystal grain boundary can be confirmed by a high-resolution TEM image in some cases.

The polycrystal oxide semiconductor film has a plurality of crystal grains, and the orientation of the crystals may be different between the plurality of crystal grains. In addition, when structural analysis of a polycrystalline oxide semiconductor film is performed using an XRD apparatus, for example, in an analysis by an out-of-plane method of a polycrystalline oxide semiconductor film having an InGaZnO ₄ crystal, 2θ is a peak near 31° , a peak in which 2θ is around 36° or other peaks may appear.

Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Accordingly, the transistor using the polycrystalline oxide semiconductor film has high field effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at grain boundaries. Further, the grain boundary of the polycrystalline oxide semiconductor film becomes a defect level. In a polycrystalline oxide semiconductor film, a crystal grain boundary may serve as a carrier trap or a carrier generation source. Therefore, a transistor using the polycrystalline oxide semiconductor film may have a large variation in electrical characteristics, resulting in a transistor with low reliability.

Next, the microcrystalline oxide semiconductor film will be described.

The microcrystalline oxide semiconductor film has a region in which a crystal part can be confirmed and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. The crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in many cases. In particular, an oxide semiconductor film having microcrystals (nc: nanocrystals) of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, is called an nc-OS (nanocrystalline oxide semiconductor) film. Further, in the nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries cannot be clearly identified in some cases.

The nc-OS film has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, in the nc-OS film, there is no regularity in the crystal orientation between different crystal portions. For this reason, the orientation does not appear in the whole film|membrane. Therefore, the nc-OS film may not be distinguished from the amorphous oxide semiconductor film depending on the analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of the crystal part, in the analysis by the out-of-plane method, the nc-OS film is located in the vicinity of 31° representing the crystal plane. No peak is detected (see Fig. 8). In addition, when electron diffraction (also referred to as limited field electron diffraction) is performed on the nc-OS film using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of the crystal part, a diffraction pattern similar to a halo pattern is observed. . On the other hand, when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to the size of the crystal part or smaller than the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed as if drawing a circle (in a ring shape). In addition, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region. For example, as shown in Fig. 9(A), when nanobeam electron diffraction is performed with a probe diameter of 30 nm, 20 nm, 10 nm or 1 nm on an nc-OS having a thickness of about 50 nm, a circle is drawn. A region with high luminance (in a ring shape) is observed. Moreover, when the probe diameter is made small, it turns out that a ring-shaped area|region is formed from several spots.

For further detailed structural analysis, the nc-OS film is thinned to a thickness of several nm (about 5 nm), and a transmission electron diffraction pattern is obtained using an electron beam having a probe diameter of 1 nm. As a result, a transmission electron diffraction pattern having spots showing crystallinity shown in Fig. 9B was obtained.

In addition, when nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions may be observed.

The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. For this reason, the density of defect states of the nc-OS film is lower than that of the amorphous oxide semiconductor film.

Also, in the nc-OS film, there is no regularity in the crystal orientation between different crystal portions. For this reason, the density of defect states of the nc-OS film is higher than that of the CAAC-OS film. Therefore, the nc-OS film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with a high carrier density may have high electron mobility. Therefore, a transistor using the nc-OS film may have high field effect mobility.

The nc-OS film can be formed at a lower temperature than the CAAC-OS film. Also, there are cases where the nc-OS film can be formed even if it contains a relatively large amount of impurities. Therefore, the nc-OS film may be easier to form than the CAAC-OS film. For this reason, a semiconductor device including a transistor using an nc-OS film can be manufactured with high productivity in some cases.

In addition, the nc-OS film may have moderate oxygen permeability. When it has an appropriate oxygen permeability, for example, oxygen released from the film having excess oxygen tends to diffuse throughout the nc-OS film. Therefore, in the nc-OS film, it is easy to reduce oxygen vacancies in some cases.

A thing with a low impurity concentration and a low density of defect states (with few oxygen vacancies) is called high-purity intrinsic or substantially high-purity intrinsic. Since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has few carrier generation sources, the carrier density can be made low. Accordingly, the transistor using the oxide semiconductor film rarely has an electrical characteristic (also referred to as normally-on) in which the threshold voltage becomes negative. In addition, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has few carrier traps. For this reason, the transistor using the said oxide semiconductor film becomes a reliable transistor with small fluctuation|variation in electrical characteristics. In addition, the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. For this reason, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

Next, the amorphous oxide semiconductor film will be described.

The amorphous oxide semiconductor film is an oxide semiconductor film having an irregular arrangement of atoms in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed on a high-resolution TEM image.

When the amorphous oxide semiconductor film is subjected to structural analysis using an XRD apparatus, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Moreover, when nanobeam electron diffraction is performed with respect to the amorphous oxide semiconductor film, a spot is not observed but a halo pattern is observed.

The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration. The amorphous oxide semiconductor film is an oxide semiconductor film having a high density of defect states.

The oxide semiconductor film with a high impurity concentration and a high density of defect states is an oxide semiconductor film with many carrier traps and carrier generation sources.

Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. For this reason, a transistor using the amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, there are cases where it can be suitably used for transistors requiring normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect states, the number of carrier traps may increase. Accordingly, a transistor using the amorphous oxide semiconductor film has a large variation in electrical characteristics compared to a transistor using a CAAC-OS film or an nc-OS film, and thus a transistor with low reliability.

Next, the single crystal oxide semiconductor film will be described.

The single crystal oxide semiconductor film is an oxide semiconductor film having a low impurity concentration and a low density of defect states (with few oxygen vacancies). For this reason, a carrier density can be made low. Accordingly, a transistor using a single crystal oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, carrier traps may decrease. Accordingly, a transistor using the single crystal oxide semiconductor film has a small variation in electrical characteristics and is a highly reliable transistor.

Moreover, the density of an oxide semiconductor film becomes high when there are few defects. Moreover, the density of an oxide semiconductor film becomes high when crystallinity is high. In addition, the density of the oxide semiconductor film becomes high when the concentration of impurities such as hydrogen is low. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. In addition, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. Further, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. Further, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

Further, the oxide semiconductor film may have a structure exhibiting physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is specifically called an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, voids (also referred to as voids) may be observed on a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has a region where a crystal part can be clearly confirmed and a region where a crystal part cannot be confirmed. In the a-like OS film, crystallization may occur and growth of a crystal part may appear by irradiation with electrons with a small degree of observation by TEM. On the other hand, in the case of a high-quality nc-OS film, crystallization by electron irradiation with a very small degree of observation by TEM hardly appears.

In addition, the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, the crystal of InGaZnO ₄ has a layered structure, and has two Ga-Zn-O layers between In-O layers. The unit lattice of the crystal of InGaZnO ₄ has three In-O layers and six Ga-Zn-O layers, and has a structure in which 9 layers in total are superimposed on the c-axis direction. Therefore, the spacing between these adjacent layers is about the same as the lattice spacing of the (009) plane (also referred to as a d value), and the value is found to be 0.29 nm from crystal structure analysis. For this reason, paying attention to the lattice fringes in the high-resolution TEM image, it was considered that each lattice fringe corresponds to the ab-plane of the InGaZnO ₄ crystal in a location where the intervals between the lattice fringes are 0.28 nm or more and 0.30 nm or less. The maximum length in the region where the lattice fringes are observed is the size of the crystal portion of the a-like OS film and the nc-OS film. In addition, the size of the crystal part is selectively evaluated to be 0.8 nm or more.

In addition, since it has a cavity, the a-like OS has a low density structure compared to nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the single crystal density of the same composition.

In addition, there are cases where single crystals of the same composition do not exist. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining the single crystals from which a composition differs in arbitrary ratios. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio of combining single crystals with different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

The oxide semiconductor film may be, for example, a laminated film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

[Nanobeam electron diffraction]

Next, nanobeam electron diffraction will be described.

When the oxide semiconductor film has a plurality of structures, structural analysis may become possible by using nanobeam electron diffraction.

7C, an electron gun chamber 610, an optical system 612 under the electron gun chamber 610, a sample chamber 614 under the optical system 612, and an optical system under the sample chamber 614 ( 616), an observation chamber 620 under the optical system 616, a camera 618 installed in the observation chamber 620, and a transmission electron diffraction measurement apparatus having a film chamber 622 under the observation chamber 620. show The camera 618 is installed toward the inside of the observation room 620 . In addition, it does not matter even if it does not have the film chamber 622.

Fig. 7(D) shows the internal structure of the transmission electron diffraction measuring apparatus shown in Fig. 7(C). In the transmission electron diffraction measuring apparatus, electrons emitted from the electron gun installed in the electron gun chamber 610 are irradiated to the material 628 disposed in the sample chamber 614 via the optical system 612 . Electrons passing through the material 628 are incident on the fluorescent plate 632 installed in the observation chamber 620 via the optical system 616 . In the fluorescent plate 632 , the transmitted electron diffraction pattern can be measured by displaying a pattern according to the intensity of the incident electron.

The camera 618 is installed to face the fluorescent plate 632 , and it is possible to photograph the pattern displayed on the fluorescent plate 632 . The angle formed by the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70° or less. The smaller the angle, the greater the deformation of the transmission electron diffraction pattern photographed by the camera 618 . However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. In addition, there may be a case where the camera 618 may be installed in the film chamber 622 . For example, you may install the camera 618 in the film chamber 622 so that the incident direction of the electron 624 may be opposite. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back surface of the fluorescent plate 632 .

The sample chamber 614 is provided with a holder for holding the material 628 as a sample. The holder has a structure that transmits electrons passing through the material 628 . The holder may have, for example, a function of moving the substance 628 in the X-axis, Y-axis, Z-axis, or the like. The movement function of the holder may have an accuracy of moving in the range of, for example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 µm or less. These ranges may be optimally set according to the structure of the substance 628 .

Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measuring apparatus will be described.

For example, as shown in FIG. 7D , by changing (scanning) the irradiation position of the electrons 624, which are nanobeams, in the material, it can be confirmed that the structure of the material is changing. At this time, if the material 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 7B is observed. Alternatively, if the material 628 is an nc-OS film, a diffraction pattern as shown in FIG. diffraction pattern) is observed. In addition, the diffraction pattern shown in FIG. 7A has bright spots that are not symmetrically arranged (not symmetrical).

As shown in Fig. 7B, in the diffraction pattern of the CAAC-OS film, spots located at, for example, hexagonal vertices are confirmed. In the CAAC-OS film, by scanning the irradiation position, the direction of this hexagon is not constant, and it appears that it rotates little by little. Also, the angle of rotation has a certain width.

Alternatively, in the diffraction pattern of the CAAC-OS film, by scanning the irradiation position, a state of slightly rotating about the c-axis appears. This can be said, for example, that the surface formed by the a-axis and the b-axis is rotating.

However, in the material 628, a region in which a diffraction pattern similar to the CAAC-OS film is observed (hereinafter, referred to as a region having a CAAC structure) and a region in which a diffraction pattern such as an nc-OS film is observed (hereinafter referred to as an nc structure). It is referred to as having a region). Here, the ratio of the region where the diffraction pattern of the CAAC-OS film is observed in a certain range can be expressed as the CAAC ratio (also referred to as the CAAC ratio). Similarly, the ratio of a region where a diffraction pattern is observed, such as an nc-OS film, can be expressed as an nc ratio (also referred to as an nc ratio).

Hereinafter, a method for evaluating the CAAC ratio of the CAAC-OS film will be described. A measurement point is randomly selected, a transmission electron diffraction pattern is acquired, and the ratio of the number of measurement points where the diffraction pattern of a CAAC-OS film|membrane is observed with respect to the total number of measurement points is calculated. Here, the measurement score is preferably 50 points or more, and more preferably 100 points or more.

As a method of randomly selecting a measurement point, for example, the irradiation position may be scanned on a straight line, and a diffraction pattern may be acquired for each time at regular intervals. It is preferable because the boundary between the area having the CAAC structure and the other areas can be confirmed by scanning the irradiation position. In addition, also about the nc formation rate, similarly, it can select a measurement point at random, acquire a transmission electron diffraction pattern, and can calculate it.

If such a measurement method is used, structural analysis of an oxide semiconductor film having a plurality of structures may become possible.

In the oxide semiconductor film of one embodiment of the present invention, for example, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, preferably 95% or more and 100% or less, 98% It is preferable that it is 100 % or more, and it is more preferable that it is 99 % or more and 100 % or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film with few clear grain boundaries can be realized. By decreasing the clear grain boundary, the carrier mobility of the oxide semiconductor film can be increased, for example.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 2)

In this embodiment, an example of the oxide semiconductor film which is one aspect of this invention is demonstrated.

In some cases, the nc-OS film can be formed even at a relatively low film formation temperature compared to the CAAC-OS film. For example, it may be formed without using heating to a board|substrate. Therefore, a semiconductor device including a transistor using the nc-OS film can be manufactured with high productivity in some cases.

Further, since the nc-OS film has moderate oxygen permeability, oxygen is easily diffused throughout the film, and oxygen vacancies can be easily reduced in some cases. Therefore, there are cases where an oxide semiconductor film with a low defect density can be realized. Accordingly, in some cases, the characteristics of a semiconductor device having a transistor using the nc-OS film can be improved. Moreover, reliability may be improved.

Here, both the nc-OS film and the CAAC-OS film have an atomic arrangement superimposed in a layered manner. Such a layered superimposed atomic arrangement can be observed using, for example, TEM or the like.

Here, images (also referred to as TEM images) obtained by transmission electron microscopy (TEM) using a spherical aberration corrector function are observed for the nc-OS film and the CAAC film. In addition, the complex analysis image of the bright field image by TEM observation and a diffraction pattern is called a high-resolution TEM image. Incidentally, a high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. In addition, acquisition of a Cs correction|amendment high-resolution TEM image can be performed by the Nippon Electronics Co., Ltd. atomic resolution analysis electron microscope JEM-ARM200F etc., for example.

In CAAC-OS and nc-OS, crystal size and orientation are investigated by analyzing Cs-corrected high-resolution cross-sectional TEM images in more detail. Hereinafter, the crystal part of the nc-OS is sometimes called a pellet. For the size and orientation of crystals, the pellets are extracted in a range of, for example, 20 nm or more on a cross-sectional TEM image, and the size and direction are investigated.

17A is a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. 17B is a Cs-corrected high-resolution cross-sectional TEM image of the nc-OS. In addition, in the figure on the left and right, the same place was observed, and the auxiliary line which shows a pellet is drawn in the figure on the right.

18A is a cross-sectional TEM image of a CAAC-OS formed by DC sputtering. 18B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part thereof. In Fig. 18(B), the number of pellets is counted, and the frequency distribution is made with respect to the size and direction (refer to Fig. 22(A)). Here, an arrow shown in Fig. 18A indicates a direction perpendicular to the sample plane. In addition, the direction of the white line shown in FIG.18(B) shows the direction of a pellet, and the length of a white line shows the magnitude|size of a pellet.

19A is a cross-sectional TEM image of the CAAC-OS formed by the RF sputtering method. 19B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part thereof. In Fig. 19(B), the number of pellets is counted, and the frequency distribution is made with respect to the size and direction (refer to Fig. 22(B)).

Fig. 20(A) is a cross-sectional TEM image of an nc-OS formed by DC sputtering. 20(B) is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged. In Fig. 20(B), the number of pellets is counted, and the frequency distribution is made with respect to the size and direction (refer to Fig. 22(C)).

Fig. 21A is a cross-sectional TEM image of an nc-OS formed by RF sputtering. Moreover, FIG. 21B is a Cs correction|amendment high-resolution cross-sectional TEM image which expanded the part. In Fig. 21(B), the number of pellets is counted, and the frequency distribution is made with respect to the size and direction (refer to Fig. 22(D)).

The table below is the result of putting together FIG. 22. Here, the direction of the pellet represents the absolute value of the angle with respect to the sample plane.

The nc-OS preferably has, for example, pellets having a size of preferably 0.5 nm or more and 3 nm or less, more preferably 1 nm or more and 3 nm or less. In addition, in nc-OS, it turns out that the direction of a pellet is oriented in the direction perpendicular|vertical to a sample surface rather than a DC sputtering method by an RF sputtering method. Here, the ratio of the direction of the pellet of the nc-OS to 0° or more and less than 30° with respect to the sample plane is, for example, preferably 0% or more and 70% or less, and the ratio of 30° or more and less than 60° is, for example, 10 % or more and 60% or less are preferable, and, as for the ratio of 60 degrees or more and less than 90 degrees, 0% or more and 60% or less are preferable, for example. It can be seen that the direction of the pellets is random in nc-OS compared to CAAC-OS.

An oxide semiconductor film having such pellets can be described, for example, by the following film formation model.

[Film formation model]

Hereinafter, the film formation model of the nc-OS will be described.

Fig. 24 is a schematic diagram in the deposition chamber showing the state in which the nc-OS is formed by sputtering.

The target 5130 is glued onto the backing plate. A plurality of magnets are disposed under the target 5130 and the backing plate. A magnetic field is generated on the target 5130 by the plurality of magnets. The sputtering method which increases the film-forming speed|rate using the magnetic field of a magnet is called the magnetron sputtering method.

The target 5130 has a polycrystalline structure, and any one of the crystal grains includes a cleaved surface. In addition, the detail of a cleavage surface is mentioned later.

The substrate 5120 is disposed to face the target 5130, and the distance d (target-to-substrate distance (also referred to as distance between TS)) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. The inside of the film formation chamber is mostly filled with a film formation gas (for example, oxygen, argon, or a mixed gas containing oxygen in a proportion of 50 vol% or more), and is 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Controlled. Here, by applying a voltage greater than or equal to a certain level to the target 5130 , discharge is started and plasma is confirmed. In addition, a high-density plasma region is formed by the magnetic field on the target 5130 . In the high-density plasma region, ions 5101 are generated by ionization of the film-forming gas. The ion 5101 is, for example, a cation of oxygen (O ⁺ ) or a cation of argon (Ar ⁺ ).

The ions 5101 are accelerated toward the target 5130 by the electric field and collide with the target 5130 immediately. At this time, the pellets 5100a and 5100b, which are flat or pellet-shaped sputtered particles, are peeled off from the cleavage surface, and are thrown out. In addition, the pellet 5100a and the pellet 5100b may have a deformation|transformation in structure by the collision impact of the ion 5101.

The pellets 5100a are sputtered particles in the form of flat plates or pellets having a triangular, for example, an equilateral triangular plane. The pellets 5100b are sputtered particles in the form of a flat plate or pellets having a hexagonal plane, for example, a regular hexagonal plane. In addition, flat or pellet-shaped sputtered particles, such as the pellets 5100a and the pellets 5100b, are collectively called a pellet. The shape of the plane of the pellet is not limited to a triangle or a hexagon. For example, there is a case where two or more triangles are combined with six or less. For example, there is a case where two equilateral triangles are combined to form a quadrilateral.

The thickness of the pellets is determined according to the type of film-forming gas and the like. It is preferable to make the thickness of a pellet uniform. Further, the sputtered particles are more preferably in the form of pellets without thickness than in the form of dice with thickness.

A pellet may receive an electric charge when passing through a plasma, so that a side surface may be electrically charged negatively or positively. The pellets have oxygen atoms on their sides, which are likely to be negatively charged.

As shown in FIG. 24 , for example, the pellets fly like a kite in the plasma and fly up to the top of the substrate 5120 flutteringly. Since the pellets have an electric charge, a repulsive force is generated when the region on which other pellets have already been deposited comes close. Here, on the upper surface of the substrate 5120 , a magnetic field in a direction parallel to the upper surface of the substrate 5120 is generated. In addition, since a potential difference is provided between the substrate 5120 and the target 5130 , a current flows from the substrate 5120 toward the target 5130 . Accordingly, the pellet receives a force (Lorentz force) by the action of a magnetic field and an electric current on the upper surface of the substrate 5120 . In addition, in order to increase the force applied to the pellets, in the upper surface of the substrate 5120, the magnetic field in a direction parallel to the upper surface of the substrate 5120 is 10G or more, preferably 20G or more, more preferably 30G or more, More preferably, an area of 50 G or more may be provided. Alternatively, in the upper surface of the substrate 5120 , the magnetic field in a direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more than the magnetic field in a direction perpendicular to the upper surface of the substrate 5120 , more What is necessary is just to provide the area|region which preferably becomes 3 times or more, More preferably, it becomes 5 times or more.

Based on the above model, it is considered that the pellets are deposited on the substrate 5120 . Accordingly, it can be seen that, unlike epitaxial growth, an nc-OS film can be formed even when the surface to be formed does not have a crystal structure. For example, even if the structure of the upper surface (formed surface) of the substrate 5120 is an amorphous structure, it is possible to form an nc-OS into a film.

Since the nc-OS is formed by such a model, it is preferable that the sputtered particles are in the form of pellets without thickness. In addition, when the sputtered particles have a dice shape with a thickness, the surface of the sputtered particles directed above the substrate 5120 is not constant, so that the thickness and orientation of the crystals cannot be uniform in some cases.

In addition, when the substrate 5120 is heated, the resistance such as friction between the pellets and the substrate 5120 is in a smaller state. As a result, the pellets move as if gliding over the upper surface of the substrate 5120 . The movement of the pellets occurs with the flat surface of the pellets facing the substrate 5120 . After that, when it reaches the side surfaces of the other pellets 5100 that have already been deposited, the side surfaces are bonded to each other to obtain a CAAC-OS film.

When the substrate 5120 is not heated, the resistance such as friction between the pellet and the substrate 5120 is higher. As a result, it is difficult for the pellets to move as if gliding on the upper surface of the substrate 5120 , and nc-OS can be obtained by falling down irregularly.

In CAAC-OS, a film is formed by heating the substrate 5120 , whereas in the nc-OS, film formation is possible without heating the substrate 5120 .

For example, as shown in FIG. 25 , the atmosphere in the chamber may be heated to preferably room temperature or more and 500°C or less, and more preferably 200°C or more to 400°C or less. For heating the atmosphere, a lamp 5140 such as a halogen lamp may be used, for example. By heating the atmosphere, there is a possibility that, for example, pellets flying in the chamber are heated, so that defects are reduced. In addition, there is a possibility that the pellet size increases. In addition, by heating the atmosphere, for example, moisture in the chamber is easily evaporated, and the degree of vacuum can be further increased.

[Cleavage side]

Below, the cleavage plane of the target described in the film-forming model of the nc-OS is demonstrated.

First, the cleavage plane of a target is demonstrated using FIG. 10 shows the structure of an InGaZnO ₄ crystal. Also, FIG. 10(A) shows the structure when the crystal of InGaZnO ₄ is observed in a direction parallel to the b-axis with the c-axis facing upward. In addition, FIG. 10B shows the structure when the crystal of InGaZnO ₄ is observed in a direction parallel to the c-axis.

The energy required for cleavage in each crystal plane of the InGaZnO ₄ crystal is calculated by first-principle calculation. In addition, a density functional program (CASTEP) using a pseudo potential and a plane wave basis is used for calculation. In addition, an ultra soft-type pseudo potential is used for a pseudo potential. In addition, GGA PBE is used for functional functions. In addition, the cut-off energy is set to 400 eV.

The structural energy in the initial state is derived after structural optimization including the cell size is performed. In addition, the structural energy after cleavage in each surface is derived after performing structural optimization of the atomic arrangement in a state where the cell size is fixed.

Based on the structure of the InGaZnO ₄ crystal shown in Fig. 10, a structure cleaved on any one of the first, second, third, and fourth surfaces is fabricated, and structure optimization calculation is performed with a fixed cell size. . Here, the first plane is a crystal plane between the Ga-Zn-O layer and the In-O layer, and is a crystal plane parallel to the (001) plane (or the ab plane) (see Fig. 10(A)). The second plane is a crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and is a crystal plane parallel to the (001) plane (or the ab plane) (see Fig. 10(A)). The third plane is a crystal plane parallel to the (110) plane (refer to (B) of FIG. 10). The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (refer to (B) of FIG. 10).

Under the conditions described above, the structural energy after cleavage at each surface is calculated. Next, by dividing the difference between the structural energy after cleavage and the structural energy in the initial state by the area of the cleavage plane, the cleavage energy, which is a measure of cleavage easiness in each plane, is calculated. In addition, the structural energy is energy in consideration of the kinetic energy of electrons and the interactions between atoms, between atoms and electrons, with respect to atoms and electrons included in the structure.

As a result of the calculation, the cleavage energy of the first surface is 2.60J/m2, the cleavage energy of the second surface is 0.68J/m2, the cleavage energy of the third surface is 2.18J/m2, and the cleavage energy of the fourth surface is 2.12J/m2 m 2 (see table below).

By this calculation, in the structure of the InGaZnO ₄ crystal shown in Fig. 10, the cleavage energy at the second surface is the lowest. That is, it can be seen that the surface between the Ga-Zn-O layer and the Ga-Zn-O layer is the most likely to be cleaved (cleaved surface). Therefore, in this specification, when it describes as a cleavage surface, the 2nd surface which is the surface most easily cleaved is shown.

Since the second surface between the Ga-Zn-O layer and the Ga-Zn-O layer has a cleavage surface, the InGaZnO ₄ crystal shown in FIG. can do. Therefore, when an ion or the like collides with a target, it is considered that the unit on the wafer (we call this a pellet) cleaved at the plane with the lowest cleavage energy will protrude as the smallest unit. In that case, the pellet of InGaZnO ₄ becomes three layers of a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

Further, rather than the first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer and parallel to the (001) plane (or ab plane)), the third plane (a crystal plane parallel to the (110) plane) ) and the fourth plane (crystal plane parallel to the (100) plane (or bc plane)) have low cleavage energy, suggesting that the planar shape of the pellets has many triangular or hexagonal shapes.

[Membrane Density]

Next, the density of the In-M-Zn oxide film was evaluated. A polycrystalline In-Ga-Zn oxide of In:Ga:Zn=1:1:1 was used as a target, and an nc-OS was formed by DC sputtering. The pressure was 0.4 Pa, the film forming temperature was room temperature, the power supply was 100 W, and argon and oxygen were used as the film forming gases, and the respective flow rates were 98 sccm for argon and 2 sccm for oxygen. The density of the obtained In-Ga-Zn oxide was 6.1 g/cm 3 . Here, the density of InGaZnO ₄ of a single crystal is 6.357 g/cm<3> rather than nonpatent literature 2. In addition, as described in JCPDS card, No. 00-038-1097, it is known that the density of single crystal In ₂ Ga ₂ ZnO ₇ is 6.494 g/cm 3 . Therefore, it can be seen that the obtained nc-OS film is an excellent film having a high density.

The density of the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention is preferably 85% or more, more preferably 90% or more, and 95% or more of the density of single crystals having substantially the same atomic ratio. This is more preferable.

Alternatively, when the element M is gallium, the density of the oxide semiconductor film of one embodiment of the present invention is, for example, preferably 5.7 g/cm 3 or more and 6.49 g/cm 3 or less, and 5.75 g/cm 3 or more and 6.49 g/cm 3 or less. Preferably, 5.8 g/cm 3 or more and 6.33 g/cm 3 or less are more preferable, and 5.85 g/cm 3 or more and 6.33 g/cm 3 or less are still more preferable.

Here, the substantially identical atomic ratio refers to, for example, that the difference between the atomic ratios is within 10%.

Here, for example, the density of a single crystal may be estimated from the density of two or more In-M-Zn oxide films having different atomic ratios. Here, the density of a single crystal having an atomic ratio of In:M:Zn=1:1:1 is D ₁ , and the density of a single crystal having an atomic ratio In:M:Zn=2:2:1 is D ₂ . The density of the In-M-Zn oxide film in which the atomic ratio of indium, element M, and zinc is 1:1:0.8 is predicted to take a value between D ₁ and D ₂ . Therefore, as the density of the single crystal, for example, the average value of D ₁ and D ₂ may be calculated and referred to, or any one of D ₁ and D ₂ , for example, a value closer to the atomic ratio may be referred to. When calculating _{an average} value using D1 and D2, what is necessary is just to set it as _0.6xD1 + _0.4xD2 , for example. Let D α be the density of a single crystal with an atomic ratio of In:M:Zn=A:B:C, and D _β is the density of a single crystal with an atomic _ratio of In:M:Zn=D:E:F. The density of a single crystal having an atomic ratio of In:M:Zn=X:Y:Z may be calculated, for example, as follows.

First, α and β are calculated so that (αA+βD):(αB+βE):(αC+βF)=X:Y:Z. Next, using the obtained α and β, the density of the single crystal may be calculated as {α/(α+β)}D _α + {β/(α+β)}D _β .

Next, an example of a method for manufacturing the nc-OS film will be described.

As a general method for forming an oxide semiconductor film, for example, a sputtering method, a chemical vapor deposition (CVD) method (a metal organometallic chemical deposition (MOCVD) method, an atomic layer deposition (ALD) method, or a plasma chemical vapor deposition (PECVD) method). included), a vacuum deposition method or a pulsed laser deposition (PLD) method, and the like.

The nc-OS film is preferably formed using a sputtering method. As a target used for the sputtering method, In-M-Zn oxide can be used.

In addition, it is preferable that the target has a polycrystalline In-M-Zn oxide. For example, when a target having polycrystalline In-M-Zn oxide is used, the target has cleavage properties and there is a possibility that an nc-OS film is easily formed, which is more preferable.

As a target, an In-M-Zn oxide can be produced by using a mixture of indium oxide, an oxide having element M, and zinc oxide in some cases, but it is preferable to use a target having polycrystalline In-M-Zn oxide. do.

In addition, the nc-OS film can be formed at about room temperature in some cases, so it is preferable. For example, it may be formed even if it does not heat to a board|substrate, and it is preferable. Further, for example, the atmosphere in the chamber may be preferably heated at room temperature or higher and 500°C or lower, more preferably 200°C or higher and 400°C or lower.

[About Atomic Defense]

Here, it is preferable to use, for example, an In-M-Zn oxide film as the oxide semiconductor film of one embodiment of the present invention. Let the atomic ratio of In, M, and Zn of the In-M-Zn oxide be In:M:Zn=x:y:z.

In the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention, for example, it is preferable to increase the proportion of indium.

Moreover, it is so preferable that there are few grain boundaries of an oxide semiconductor film. Examples of the non-single crystal oxide semiconductor film having few grain boundaries include an nc-OS film and a CAAC-OS film. In addition, the oxide semiconductor film may have both an nc-OS film and a CAAC-OS film.

In addition, the oxide semiconductor film of one embodiment of the present invention preferably has a region (nc structure) in which the diffraction pattern of the nc-OS film is observed when nanobeam electron diffraction is performed. In addition, the oxide semiconductor film of one embodiment of the present invention may have a region in which the diffraction pattern of the nc-OS film is observed and a region (CAAC structure) in which the diffraction pattern of the CAAC-OS film is observed.

In addition, it is preferable that the oxide semiconductor film of one embodiment of the present invention has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. Further, in the oxide semiconductor film of one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, preferably 95% or more and 100% or less, 98% or more It is preferable that it is 100% or less, and it is more preferable that it is 99% or more and 100% or less.

In the oxide semiconductor film of one embodiment of the present invention, a plurality of films may be laminated. Further, the respective nc ratios and CAAC ratios of the plurality of films may be different. Moreover, it is preferable that at least one film|membrane among the laminated|stacked film|membrane has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. In addition, among the plurality of laminated films, in the film of at least one layer, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less, and 95% or more and 100% or less, It is preferable that they are 98 % or more and 100 % or less, and it is more preferable that they are 99 % or more and 100 % or less.

As shown in FIG. 6 , when powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and calcined at 1350° C., it is non-patent document 1 that the high solution capacity is widened by increasing the proportion of zinc. is described in Here, the CAAC ratio of the oxide semiconductor film of one embodiment of the present invention may be higher by setting the atomic ratio of the In-Ga-Zn oxide to a range where a high solution can be taken. Therefore, by making the ratio of zinc small, the nc ratio of the oxide semiconductor film of one embodiment of the present invention can be made higher in some cases. Let the atomic ratio of indium, element M, and zinc in the oxide semiconductor film be indium: element M: zinc = x: y: z. For example, by increasing the ratio of x+y to z, that is, (x+y)/z, the nc ratio can be further increased in some cases. Specifically, for example, (x+y)>z is preferable, (x+y)≧1.5z is preferable, and (x+y)≧2z is preferable.

Further, when the crystals of the spinel structure are mixed with the CAAC-OS film or the nc-OS film, a clear grain boundary or boundary portion may be formed. Therefore, it is preferable to move away from the atomic ratio in which crystals of the spinel structure are more likely to be formed.

Therefore, the atomic ratios x, y, and z of In, element M, and zinc in the In-M-Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention are atoms in the region 13 shown in Fig. 4A. It is preferable to have an atomic ratio, and it is more preferable to have an atomic ratio of the area|region 14 shown in FIG.4(B). Here, the region 13 has a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate V (x:y:z=1:2:3), the fourth coordinate S(x:y:z=1:0:1), and the fifth coordinate T(x:y:z=8:0:1) ), the sixth coordinate U (x:y:z=6:2:1), and the first coordinate K are sequentially connected to each other by a line segment. In addition, the region 13 includes a line segment connecting six points. In addition, the region 13 includes all coordinates. In addition, the region 14 includes a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate V( x:y:z=1:2:3), fourth coordinate W (x:y:z=7:1:8), and fifth coordinate X (x:y:z=7:1:1) , and the sixth coordinate U (x:y:z=6:2:1) and the first coordinate K are in a region connected by a line segment in order. Also, the region 14 includes a line segment connecting the six points. Region 14 also includes all coordinates.

Moreover, when forming an oxide semiconductor film into a film by sputtering method, the atomic ratio of the film|membrane obtained may deviate from the atomic ratio of a target. In particular, in the case of zinc, the zinc ratio of the obtained film may be smaller than the zinc ratio of the target. Specifically, the zinc ratio of the obtained film|membrane may be 40 atomic% or more and 90 atomic% or less of the zinc ratio of a target, for example.

Here, when an In-Ga-Zn oxide is formed into a film by sputtering, the relationship between the atomic ratio of the target to be used and the atomic ratio of the resulting film was investigated.

As the film forming conditions, argon and oxygen were used as the film forming gas, and the oxygen flow rate was set to 33%. Here, the oxygen flow rate ratio is a quantity expressed by oxygen flow rate ÷ (oxygen flow rate + argon flow rate) x 100 [%]. In addition, the pressure was made into the range of 0.4 Pa to 0.7 Pa, the board|substrate temperature was 200 degreeC - 300 degreeC, and the power supply power was 0.5 kW (DC).

Fig. 23 shows the relationship between the value of the atomic ratio when focusing on two elements of the target and the residual rate of zinc. Numerals in the figure indicate the atomic ratio of In:Ga:Zn of the target. Here, the residual rate of zinc is demonstrated. The value obtained by dividing the value of the zinc term in the atomic ratio of the film by the sum of the values of the indium, gallium, and zinc terms of the film is defined as Zn(Film). In addition, let Zn (Target) be the value which divided the value of the zinc term in the atomic ratio of a target by the sum of the values of indium, gallium, and zinc of a target. Here, the residual rate of zinc is defined as a value expressed by A=Zn(Film)÷Zn(Target)×100 [%].

In addition, the atomic ratio of indium, gallium, and zinc of the In-Ga-Zn oxide target used is shown by a:b:c.

23A is a value (c/b) of a ratio of zinc to gallium of the target on the abscissa axis, and FIG. 23B is a value (b) of a ratio of gallium to indium atomic ratio of the target on the abscissa axis /a), and FIG. 23(C) shows the value (c/a) of the ratio of zinc to indium of the target on the horizontal axis, respectively. In addition, each vertical axis represents the residual rate A of zinc.

Here, from FIG. 23, it turns out that the zinc residual rate of the film|membrane obtained by the sputtering method is about 50 % or more and 90 % or less. In addition, it can be said that indium and gallium do not change greatly from the atomic ratio of a target compared with zinc. In addition, when the value (c/b) of the ratio of zinc to gallium of the target is, for example, 1, the zinc residual rate A is about 66%, when it is 2, it is about 74%, and when it is 3, it is about 83%. to be.

Moreover, it turns out that FIG.23(A) shows that there exists a favorable correlation between the value (c/b) of the ratio of zinc to gallium of a target, and the residual rate of zinc. That is, the one where there is little zinc with respect to gallium is lower than the residual rate.

In view of the above, in order to obtain the oxide semiconductor film of the region 13 shown in Fig. 4A by sputtering, for example, the target zinc ratio to the target zinc ratio value. The value of is preferably 1.7 times or more, more preferably 1.5 times or more. Therefore, it is preferable that indium, gallium, and zinc of the target have an atomic ratio of the region 15 shown in FIG. Here, the region 15 has a first coordinate K (a:b:c=8:14:7), a second coordinate R (a:b:c=2:4:3), and a third coordinate Y (a:b:c=1:2:5.1), the fourth coordinate Z(a:b:c=1:0:1.7), and the fifth coordinate T(a:b:c=8:0:1) ), the sixth coordinate U (a:b:c=6:2:1), and the first coordinate K are sequentially connected to each other by a line segment. In addition, the region 15 includes a line segment connecting six points. Region 15 contains all coordinates.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 3)

In the present embodiment, an example of a transistor using an oxide semiconductor film as one embodiment of the present invention will be described.

[Example 1 of transistor]

An example of a transistor using an oxide semiconductor film will be described with reference to FIG. 12 .

12A shows a top view of the transistor 100 . Fig. 12(B) shows a cross section along the dash-dotted line X-X' shown in Fig. 12(A), and Fig. 12(C) shows a cross-section along the dash-dotted line Y-Y'. . The transistor 100 shown in FIG. 12 includes a substrate 50 , an insulating film 51 in contact with the upper surface of the substrate 50 , an insulating film 114 in contact with the upper surface of the insulating film 51 , and an insulating film 114 . A semiconductor layer 101 in contact with the upper surface, a conductive layer 104a and a conductive layer 104b, a gate insulating film 102 on the semiconductor layer 101, and a semiconductor layer 101 with a gate insulating film 102 interposed therebetween; It has an overlapping gate electrode 103 . Further, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100 . In addition, the transistor 100 may have a conductive layer 105 . In addition, it is not necessary to provide an insulating film between the substrate 50 and the insulating film 114 .

The semiconductor layer 101 may be formed in a single layer, more preferably in a laminated structure of the first to third layers. The second layer is provided in contact with the first layer, and the third layer is provided in contact with the second layer. Here, in the transistor of one embodiment of the present invention, the first layer and the third layer have regions in which current hardly flows compared to the second layer. Therefore, the first layer and the third layer are sometimes referred to as an insulator layer. Accordingly, as in the example shown in Fig. 12, the semiconductor layer 101 is preferably formed in a laminated structure of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c. Moreover, it is good also as a structure which does not have either the insulator layer 101a or the insulator layer 101c. In the example shown in FIG. 12, the semiconductor layer 101b is in contact with the upper surface of the insulator layer 101a. In addition, the conductive layer 104a and the conductive layer 104b are in contact with the upper surface of the semiconductor layer 101b and are spaced apart in a region overlapping the semiconductor layer 101b. Further, the insulator layer 101c is in contact with the upper surface of the semiconductor layer 101b. In addition, the gate insulating film 102 is in contact with the upper surface of the insulator layer 101c. In addition, the gate electrode 103 overlaps the semiconductor layer 101b with the gate insulating layer 102 and the insulating layer 101c interposed therebetween.

Further, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100 . The insulating film 112 and the insulating film 113 will be described in detail in the embodiments to be described later.

The conductive layer 104a and the conductive layer 104b have a function as a source electrode or a drain electrode. Alternatively, a voltage lower or higher than that of the source electrode may be applied to the conductive layer 105 to change the threshold voltage of the transistor in the positive direction or the negative direction. By varying the threshold voltage of the transistor in the positive direction, normally off can be realized in which the transistor is in a non-conductive state (off state) even when the gate voltage is 0V. In addition, the voltage applied to the conductive layer 105 may be variable or may be fixed. When the voltage applied to the conductive layer 105 is made variable, a circuit for controlling the voltage may be connected to the conductive layer 105 . In addition, the conductive layer 105 may be connected to the gate electrode 103 .

The upper surface of the insulating film 114 is preferably planarized by a planarization process using a CMP (Chemical Mechanical Polishing) method or the like.

The insulating film 114 preferably contains an oxide. In particular, it is preferable to contain an oxide material from which a part of oxygen is desorbed by heating. Suitably, it is preferred to use oxides containing more oxygen than oxygen to satisfy the stoichiometric composition. In the oxide film containing more oxygen than oxygen satisfying the stoichiometric composition, a part of oxygen is desorbed by heating. Oxygen desorbed from the insulating film 114 is supplied to the semiconductor layer 101 which is an oxide semiconductor, and it becomes possible to reduce oxygen vacancies in the oxide semiconductor. As a result, variations in the electrical characteristics of the transistor can be suppressed and reliability can be improved.

The oxide film containing more oxygen than oxygen satisfying the stoichiometric composition is, for example, by temperature elevated desorption gas spectroscopy analysis (TDS analysis), the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 ¹⁸ atoms/cm 3 or more, preferably It is an oxide film of 3.0×10 ²⁰ atoms/cm 3 or more. Moreover, as a surface temperature of the film|membrane at the time of the said TDS analysis, the range of 100 degreeC or more and 700 degrees C or less, or 100 degreeC or more and 500 degrees C or less is preferable.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide may be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. In addition, in this specification, silicon oxynitride refers to the material with more content of oxygen than nitrogen as its composition, and silicon nitride oxide shows the material with much content of nitrogen than oxygen as its composition.

Further, in order to make the insulating film 114 contain oxygen excessively, oxygen may be introduced into the insulating film 114 to form a region containing excessive oxygen. For example, oxygen (containing at least any one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after formation to form a region containing excess oxygen. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like can be used.

The semiconductor layer 101 includes an oxide semiconductor. The oxide semiconductor is preferable because the current in the OFF state of the transistor can be reduced when a semiconductor material having a wider band gap than silicon and a smaller carrier density is used. In addition, since the semiconductor layer 101 includes an oxide semiconductor, variations in electrical characteristics are suppressed, and a highly reliable transistor can be realized.

Here, as the semiconductor layer 101, the oxide semiconductor shown in Embodiment 1 or Embodiment 2 can be used, for example.

In addition, in this specification, etc., when it is called substantially intrinsic, the carrier density of an oxide semiconductor layer is less than 1x10 ¹⁷ /cm<3>, less than 1x10 ¹⁵ /cm<3>, or less than 1x10 ¹³ /cm<3>. By making the oxide semiconductor layer highly purified intrinsic, stable electrical characteristics can be imparted to the transistor.

Here, a case in which a laminated film of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c is used as the semiconductor layer 101 will be described in detail. For the semiconductor layer 101b, it is preferable to use an oxide having a higher electron affinity than that of the insulator layer 101a and the insulator layer 101c. For example, as the semiconductor layer 101b, the electron affinity of the insulator layer 101a and the insulator layer 101c is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more. Large oxides of 0.4 eV or less are used. Also, the electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.

When an electric field is applied to the gate electrode by using an oxide having a larger electron affinity than the insulator layer 101a and the insulator layer 101c as the semiconductor layer 101b, the insulator layer 101a, the semiconductor layer 101b, and the insulator layer In 101c, a channel is formed in the semiconductor layer 101b having a high electron affinity. Here, when a channel is formed in the semiconductor layer 101b, for example, since the channel formation region moves away from the interface with the gate insulating film 102, the influence of scattering at the interface with the gate insulating film can be reduced. Accordingly, the field effect mobility of the transistor can be increased. Here, since the elements constituting the semiconductor layer 101b and the insulator layer 101c are in common as will be described later, interfacial scattering hardly occurs.

In addition, when a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, or a silicon nitride film is used for the gate insulating film, silicon contained in the gate insulating film may be mixed into the oxide semiconductor film. When silicon is contained in an oxide semiconductor film, the fall of the crystallinity of an oxide semiconductor film, the fall of carrier mobility, etc. may occur. Therefore, in order to reduce the impurity concentration, for example, silicon concentration, of the semiconductor layer 101b in which the channel is formed, it is preferable to provide the insulator layer 101c between the semiconductor layer 101b and the gate insulating film. For the same reason, in order to reduce the influence of impurity diffusion from the insulating film 114 , it is preferable to provide the insulating layer 101a between the semiconductor layer 101b and the insulating film 114 .

As the semiconductor layer 101b, for example, an oxide semiconductor film containing indium, element M, and zinc may be used. For example, it is preferable to use the oxide semiconductor film shown in Embodiment 1 and Embodiment 2.

For the semiconductor layer 101b, for example, an oxide having a large energy gap is used. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.7 eV or more and 3.7 eV or less, and more preferably 2.8 eV or more and 3.3 eV or less.

Next, the insulator layer 101a and the insulator layer 101c will be described. For example, the insulator layer 101a and the insulator layer 101c are oxides composed of one or more or two or more elements other than oxygen constituting the semiconductor layer 101b. Since the insulator layer 101a and the insulator layer 101c are composed of one or more or two or more elements other than oxygen constituting the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b. , and at the interface between the semiconductor layer 101b and the insulator layer 101c, it is difficult to form an interface state.

Here, the band structure is shown in FIG. 11 shows the vacuum level (represented as vacuum level), the energy at the lower end of the conduction band of each layer (represented as Ec), and the energy at the upper end of the valence band (represented as Ev) of each layer.

Here, a mixed region of the insulator layer 101a and the semiconductor layer 101b may be provided between the insulator layer 101a and the semiconductor layer 101b. In addition, a mixed region of the semiconductor layer 101b and the insulator layer 101c may be provided between the semiconductor layer 101b and the insulator layer 101c. The mixed region has a lower density of interfacial states. For this reason, the laminate of the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c has a band structure in which energy continuously changes (also referred to as continuous junction) in the vicinity of each interface.

At this time, electrons mainly move in the semiconductor layer 101b, not in the insulator layer 101a and in the insulator layer 101c. As described above, by lowering the density of interfacial states at the interface between the insulator layer 101a and the semiconductor layer 101b and the density of interfacial states at the interface between the semiconductor layer 101b and the insulator layer 101c, the semiconductor layer In (101b), the movement of electrons is less inhibited, and the on-state current of the transistor can be increased.

In addition, although FIG. 11 shows the case where Ec of the insulator layer 101a and the insulator layer 101c are the same, each may be different. For example, Ec of the insulator layer 101c may have a higher energy than that of the insulator layer 101a.

As shown in FIG. 12B , the side surface of the semiconductor layer 101b is in contact with the conductive layer 104a and the conductive layer 104b. In addition, as shown in FIG. 12C , the electric field of the gate electrode 103 can electrically surround the semiconductor layer 101b (the electric field of the conductor electrically surrounds the semiconductor). The structure of the transistor is called a surrounded channel (s-channel) structure). When the gate electrode 103 is provided to face the upper surface and the side surface of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the upper surface of the semiconductor layer 101b but also in the entire (bulk) area. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on current) at the time of conduction can be increased.

Since a high on-current is obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since the transistor can be miniaturized, the semiconductor device including the transistor can be a highly integrated, high-density semiconductor device. For example, the transistor has a region in which the channel length is preferably 40 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, further preferably has a region of 30 nm or less, more preferably 20 nm or less. In particular, the smaller the channel width is, the wider the region where the channel is formed even inside the semiconductor layer 101b.

As the insulator layer 101a and the insulator layer 101c, for example, In-M-Zn oxide can be used.

Moreover, indium gallium oxide has a small electron affinity and high oxygen barrier property. For this reason, for example, the insulator layer 101c may contain indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

Moreover, it is more preferable that the insulator layer 101c contains gallium oxide. When gallium oxide is contained in the insulator layer 101c, a lower off-state current can be realized in some cases.

In addition, it is preferable to use an nc-OS film or a CAAC-OS film for the insulator layer 101a and the insulator layer 101c. Here, by increasing the nc ratio and CAAC ratio of the insulator layer 101a or the insulator layer 101c, for example, defects can be further reduced. Further, for example, the region having spinel crystals can be reduced. Moreover, for example, carrier scattering can be made small. Moreover, for example, it can be set as the film|membrane with high barrier property with respect to an impurity. In addition, mixing of impurities into the semiconductor layer 101b can be suppressed, and the impurity concentration of the semiconductor layer 101b can be reduced.

The nc ratio of the insulator layer 101a and the insulator layer 101c is, for example, preferably 10% or more, preferably 30% or more, preferably 50% or more, preferably 80% or more, and 90% or more. This is preferable, and 95% or more is preferable.

Here, the case where the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are made of In-M-Zn oxide is considered. Let the atomic ratios of In, the elements M, and Zn in the insulator layer 101a be x _a , y _a and z _a . Similarly, the atomic ratios of In, the elements M, and Zn in the semiconductor layer 101b are x _b , y _b and z _b . Similarly, the atomic ratios of In, the elements M, and Zn in the insulator layer 101c are x _c , y _c and z _c . Each preferable value is demonstrated below.

x _b , y _b and z _b are the ranges of any one of the regions 11 , 12 , 13 and 14 shown in FIGS. 1 , 2A and 4 . it is preferable

It is preferable that the insulator layer 101a and the insulator layer 101c do not contain a spinel crystal structure or have a small amount. Therefore, x _a :y _a :z _a and x _c :y _c :z _c are, for example, within the range of the region 11 of FIG. 1 and have a smaller electron affinity than the semiconductor layer 101b. It is preferable to take

Here, in order to make the electron affinity of the semiconductor layer 101b larger than that of the insulator layer 101a and the insulator layer 101c, for example, the indium content of the semiconductor layer 101b is increased in the insulator layer 101a and the insulator layer ( 101c) is preferred.

For example, x _b /(x _b +y _b +z _b )>x _a /(x _a +y _a +z _a ), and x _b /(x _b +y _b +z _b )>x _c / It is desirable to satisfy (x _c +y _c +z _c ).

For example, preferably x _a /(x _a +y _a )<0.5, more preferably x _a /(x _a +y _a )<0.33, still more preferably x _a /(x _a + y _a )<0.25. Further, preferably x _b /(x _b +y _b )≥0.25, more preferably x _b /(x _b +y _b )≥0.34. Further, preferably x _c /(x _c +y _c ) <0.5, more preferably x _c /(x _c +y _c ) < 0.33, still more preferably x _c /(x _c +y _{c )} ) < 0.25.

Alternatively, x _a , y _a , z _a , and x _c , y _c , z _c preferably have an atomic ratio in the region 16 shown in FIG. 2B . Here, the region 16 has a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate L (x:y:z=2:5:7), the fourth coordinate M (x:y:z=51:149:300), and the fifth coordinate B (x:y:z=1:4:10) ), the sixth coordinate C (x:y:z=1:1:4), the seventh coordinate A (x:y:z=2:2:1), and the first coordinate K, in order A region connected by a line segment. Also, region 16 includes all coordinates.

In addition, when the transistor has an s-channel structure, a channel is formed in the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-state current of the transistor can be. For example, the semiconductor layer 101b may have a region having a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of a semiconductor device may fall, it is good to set it as the semiconductor layer 101b which has the area|region with a thickness of 300 nm or less, for example, Preferably it is 200 nm or less, More preferably, it is 150 nm or less.

In addition, in order to increase the on-state current of the transistor, it is preferable that the thickness of the insulator layer 101c be smaller. For example, the insulator layer 101c may have a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the insulator layer 101c has a function of blocking entry of elements other than oxygen (hydrogen, silicon, etc.) constituting the adjacent insulator into the semiconductor layer 101b in which the channel is formed. For this reason, it is preferable that the insulator layer 101c has a certain thickness. For example, the insulator layer 101c may have a region having a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. In addition, in order to suppress outward diffusion of oxygen emitted from the gate insulating film 102 or the like, the insulator layer 101c preferably has a property of blocking oxygen.

In addition, in order to increase reliability, it is preferable that the insulator layer 101a is thick and that the insulator layer 101c is thin. For example, the insulator layer 101a may have a region having a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably 60 nm or more. By increasing the thickness of the insulator layer 101a, the distance from the interface between the adjacent insulator and the insulator layer 101a to the semiconductor layer 101b in which the channel is formed can be increased. However, since the productivity of the semiconductor device may be lowered, the insulator layer 101a may have a thickness of, for example, 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.

When the oxide semiconductor film contains a large amount of hydrogen or water, a donor level due to hydrogen may be formed. Due to the formation of the donor level, the threshold value of the transistor may shift in the negative direction. Therefore, it is preferable to perform a dehydration treatment (dehydrogenation treatment) after formation of the oxide semiconductor film to remove hydrogen or moisture to achieve high purity so as not to contain impurities as much as possible.

In addition, oxygen may also be reduced at the same time by the dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, it is preferable to supply oxygen after the dehydration treatment to compensate for oxygen vacancies in the oxide semiconductor film. In this specification and the like, supplying oxygen to the oxide semiconductor film may be referred to as an addition oxygenation treatment. Alternatively, a process in which the ratio of oxygen contained in the oxide semiconductor film is made higher than the stoichiometric composition is sometimes described as a peroxygenation treatment.

In this way, by removing hydrogen or moisture by dehydration treatment and supplementing oxygen vacancies by addition oxygenation treatment, i-type (intrinsic) or substantially i-type (intrinsic) oxide semiconductor very close to i-type barrier can be realized. In addition, substantially intrinsic means that the number of carriers derived from the donor in the oxide semiconductor film is very small (close to zero), and the carrier density is 1×10 ¹⁷ /cm 3 or less, 1×10 ¹⁶ /cm 3 or less, 1×10 ¹⁵ /cm 3 or less. Hereinafter, it refers to 1×10 ¹⁴ /cm 3 or less and 1×10 ¹³ /cm 3 or less.

A transistor including an i-type or substantially i-type oxide semiconductor film can realize an extremely excellent off-state current. For example, the off current of a transistor using an oxide semiconductor film is 1×10 ^-18 A or less at room temperature (about 25° C.), preferably 1×10 ^-21 A or less, more preferably 1×10 ^-24 A or less. or less, or 1×10 ^-15 A or less at 85°C, preferably 1×10 ^-18 A or less, and more preferably 1×10 ⁻²¹ A or less. Here, the off current refers to a drain current when the transistor is in an off state. Incidentally, the off state of the transistor means a state in which the gate voltage is sufficiently smaller than the threshold value in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or more, 2 V or more, or 3 V or more less than the threshold, the transistor is turned off.

One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode.

The conductive layer 104a and the conductive layer 104b have a single-layer structure or a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing this as a main component. It is used as a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film , a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or titanium nitride film, and an aluminum film or a copper film are laminated on the titanium film or titanium nitride film, and A three-layer structure on which a titanium film or a titanium nitride film is formed, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film are laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is formed thereon There are three-layer structures. Moreover, you may use the transparent electrically-conductive material containing indium oxide, a tin oxide, or zinc oxide.

The gate insulating film 102 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based metal oxide, silicon nitride, etc. do.

In addition, as the gate insulating film 102 , hafnium silicate (HfSiO _x ), nitrogen-doped hafnium silicate (HfSi _x O _y N _z ), nitrogen-doped hafnium aluminate (HfAl _x O _y N _z ), yttrium oxide, etc. of high-k material may be used.

Further, as the gate insulating film 102, an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, etc. , a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixed material thereof.

Further, as the gate insulating film 102, it is preferable to use an oxide insulating film containing more oxygen than oxygen satisfying the stoichiometric composition, like the insulating film 114 .

In addition, when a specific material is used for the gate insulating film, electrons can be trapped in the gate insulating film under specific conditions, and the threshold voltage can be shifted in the positive direction. For example, a material having many electron trapping levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for a part of the gate insulating film, such as a laminated film of silicon oxide and hafnium oxide, and a higher temperature (use temperature of a semiconductor device) is used. or at a temperature higher than the storage temperature, or 125°C or more and 450°C or less, typically 150°C or more and 300°C or less), the potential of the gate electrode is set higher than the potential of the source electrode or the drain electrode for 1 second or more, typically By holding for 1 minute or longer, electrons move from the semiconductor layer toward the gate electrode, and some of them are trapped in the electron trapping level.

The gate electrode 103 is made of, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above metals, an alloy combining the above metals, or the like. can be formed Moreover, you may use the metal selected from any one or a plurality of manganese and zirconium. Further, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. In addition, the gate electrode 103 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, tantalum nitride There are a two-layer structure in which a tungsten film is laminated on a rum film or a tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are laminated on the titanium film, and a titanium film is further formed thereon. Moreover, you may use the alloy film or nitride film which combined aluminum with one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium.

In addition, the gate electrode 103 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, A light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can also be applied. Moreover, it may be set as the laminated structure of the said electroconductive material which has the said light-transmitting property, and the said metal.

Further, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, and an In-Zn-based acid are interposed between the gate electrode 103 and the gate insulating film 102 . A nitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and have a value larger than the electron affinity of the oxide semiconductor. of switching elements can be realized. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, an In-Ga-Zn-based oxynitride semiconductor film with a nitrogen concentration at least higher than that of the semiconductor layer 101, specifically 7 atomic% or more, is used.

The above is the description of the transistor 100 .

In addition, the channel length is, for example, in the top view of the transistor, in the region where the semiconductor (or the portion in which the current flows in the semiconductor when the transistor is on) and the gate electrode overlap, or in the region where the channel is formed. , refers to the distance between the source (source region or source electrode) and drain (drain region or drain electrode). In addition, in one transistor, it is not limited that the channel length takes the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. For this reason, in this specification, the channel length is set to any one of a value, a maximum value, a minimum value, or an average value in the area|region in which a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion of a semiconductor in which a current flows when the transistor is on) overlaps with a gate electrode, or a portion where a source and a drain face each other in a region where a channel is formed. say the length of In addition, in one transistor, it is not limited that the channel width takes the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. For this reason, in this specification, the channel width is made into any one value, a maximum value, a minimum value, or an average value in the area|region in which a channel is formed.

In addition, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as apparent channel width) ) may be different. For example, in a transistor having a three-dimensional structure, the effective channel width becomes larger than the apparent channel width shown in the top view of the transistor, and the influence thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor to the ratio of the channel region formed on the upper surface of the semiconductor may increase. In that case, the effective channel width in which the channel is actually formed becomes larger than the apparent channel width shown in the top view.

However, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate an effective channel width from a design value, it is necessary to assume that the shape of the semiconductor is already known. Therefore, when the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, in the top view of the transistor, in the region where the semiconductor and the gate electrode overlap, the apparent channel width, which is the length of the portion where the source and the drain face each other, is referred to as "Surrounded Channel Width (SCW)". Channel Width)” in some cases. In addition, in this specification, when simply describing a channel width, it may refer to a surround channel width or an apparent channel width. Alternatively, in this specification, when simply referring to the channel width, the effective channel width may be indicated in some cases. The channel length, channel width, effective channel width, apparent channel width, surround channel width, etc. can be determined by acquiring a cross-sectional TEM image or the like and analyzing the image.

In addition, when calculating and obtaining the field effect mobility of a transistor, a current value per channel width, etc., it may be calculated using the surround channel width. In that case, a value different from the case of calculation using the effective channel width may be taken.

[Example 2 of transistor]

An example of a structure different from that of FIG. 12 of a transistor using an oxide semiconductor film according to one embodiment of the present invention will be described with reference to FIG. 13 . Fig. 13(A) is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and Fig. 13(B) is a view taken between the dash-dotted line X1-X2 shown in Fig. 13(A). It corresponds to the cross-sectional view of a cross section, and FIG. 13(C) corresponds to the cross-sectional view of the cut surface in between dashed-dotted line Y1-Y2 shown in FIG. 13(A).

The transistor 100 has a gate electrode 203a functioning as a gate electrode over the substrate 50 , a gate insulating film 202 over the substrate 50 and the gate electrode 203a , and a semiconductor over the gate insulating film 202 . It has a layer 201 and a conductive layer 204a and a conductive layer 204b functioning as source and drain electrodes electrically connected to the semiconductor layer 201 . In addition, an insulating film 214, an insulating film 216, and an insulating film 218 are sequentially stacked on the transistor 100, more specifically, on the conductive layer 204a, the conductive layer 204b, and the semiconductor layer 201. is installed

Next, components included in the transistor of the present embodiment will be described.

As the gate electrode 203a functioning as the gate electrode of the transistor 100 , the description of the gate electrode 103 may be referred to.

As the gate insulating film 202 functioning as the gate insulating film of the transistor 100 , the description of the gate insulating film 102 may be referred to. In addition, a laminated film of two or more layers may be used as the gate insulating film 202 . For example, as shown in FIG. 13, it is good also as a two-layer structure of the gate insulating film 202a and the gate insulating film 202b. In that case, for example, a film having a function as a blocking film for suppressing the permeation of oxygen to the lower layer, here the gate insulating film 202a, may be used. As a film having a function as a blocking film, for example, a barrier film 111 or the like described later may be referred to.

As the semiconductor layer 201, the oxide semiconductor film shown in Embodiment 1 or Embodiment 2 may be used. As the semiconductor layer 201 , reference may be made to the description of the semiconductor layer 101 . In addition, the semiconductor layer 201 may use a laminated|multilayer film of two or more layers.

The insulating film 214 , the insulating film 216 , and the insulating film 218 have a function as a protective insulating film of the transistor 100 . The insulating film 214 also functions as a damage mitigating film to the semiconductor layer 201 when the insulating film 216 is formed.

It is more preferable that the insulating film 214 and the insulating film 216 have, for example, a region containing oxygen excessively than the stoichiometric composition (oxygen excess region) like the insulating film 114 described above.

In addition, the insulating film 214 preferably has a small amount of defects. Typically, by ESR measurement, it is preferable that the spin density of a signal appearing at g = 2.01 derived from the dangling bond of silicon is 3×10 ¹⁷ spins/cm 3 or less. do. When the density of defects contained in the insulating film 214 is large, oxygen bonds to the defects, and the amount of oxygen permeated through the insulating film 214 is reduced.

In the insulating film 214 , all oxygen entering the insulating film 214 from the outside does not move to the outside of the insulating film 214 , but some oxygen stays in the insulating film 214 . In addition, when oxygen enters the insulating film 214 and oxygen contained in the insulating film 214 moves to the outside of the insulating film 214 , movement of oxygen in the insulating film 214 occurs in some cases. When an oxide insulating film that can transmit oxygen is formed as the insulating film 214 , oxygen desorbed from the insulating film 216 provided on the insulating film 214 is moved to the semiconductor layer 201 via the insulating film 214 . can

In addition, the insulating film 214 may be formed using an oxide insulating film having a low density of nitrogen oxide levels between the energy E _{v_os} at the upper end of the valence band and the energy E _{c_os} at the lower end of the conduction band of the oxide semiconductor film. Between E _{v_os} and E _{c_os} , as the oxide insulating film having a low nitrogen oxide level density, a silicon oxynitride film with a small amount of nitrogen oxide emitted, an aluminum oxynitride film with a small amount of nitrogen oxide emitted, or the like can be used.

In addition, the silicon oxynitride film with a small amount of nitrogen oxide emitted is a film in which the amount of ammonia molecules released is greater than that of nitrogen oxides in the temperature elevated desorption gas analysis method, and typically the amount of ammonia molecules released is 1×10 ¹⁸ pieces/cm 3 or more. 5×10 ¹⁹ pieces/cm 3 or less. Incidentally, the release amount of ammonia molecules is defined as the amount released by heat treatment at a film surface temperature of 50°C or more and 650°C or less, preferably 50°C or more and 550°C or less.

Nitrogen oxide (NO _x , x is greater than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO ₂ or NO, forms a level in the insulating film 214 or the like. The level is located in the energy gap of the semiconductor layer 201 . For this reason, when nitrogen oxide diffuses to the interface between the insulating film 214 and the semiconductor layer 201 , the level may trap electrons on the insulating film 214 side. As a result, since the trapped electrons stay near the interface between the insulating film 214 and the semiconductor layer 201, the threshold voltage of the transistor is shifted in the positive direction.

In addition, nitrogen oxide reacts with ammonia and oxygen in heat processing. Since the nitrogen oxide contained in the insulating film 214 reacts with ammonia contained in the insulating film 216 in the heat treatment, the nitrogen oxide contained in the insulating film 214 is reduced. For this reason, in the interface between the insulating film 214 and the semiconductor layer 201, an electron is hard to be trapped.

Further, in the semiconductor layer 201 , the insulating film 214 is in contact with the semiconductor layer 201 on the opposite side of the region where the channel is formed (hereinafter, referred to as the back channel region), thereby forming the semiconductor layer 201 . It has a function of protecting the back channel area.

As the insulating film 214, by using an oxide insulating film having a low density of nitrogen oxide states between E _{v_os} and E _{c_os} , it is possible to reduce the shift of the threshold voltage of the transistor, thereby reducing the fluctuation of the electrical characteristics of the transistor. have.

Further, in the oxide insulating film having a low density of nitrogen oxide levels between E _{v_os} and E _{c_os} , the nitrogen concentration measured by SIMS is 6×10 ²⁰ atoms/cm 3 or less.

In addition, the insulating film 216 preferably has a small amount of defects. Typically, by ESR measurement, the spin density of the signal at g = 2.01 derived from the dangling bond of silicon is less than 1.5×10 ¹⁸ spins/cm 3 , In addition, it is preferable that it is 1×10 ¹⁸ spins/cm 3 or less. In addition, since the insulating film 216 is separated from the semiconductor layer 201 compared to the insulating film 214 , the defect density may be higher than that of the insulating film 214 .

The transistor 100 may have a structure shown in FIGS. 14 and 15 . Here, the transistor 100 shown in FIG. 13 is a channel etch type transistor, but the transistor 100 shown in FIGS. 14 and 15 is a channel protection type transistor.

Fig. 14A is a top view of a transistor 100 that is a semiconductor device of one embodiment of the present invention, and Fig. 14B is a cross-dotted line X1-X2 shown in Fig. 14A. It corresponds to the cross-sectional view of the cut surface in FIG. 14(C), and corresponds to the cross-sectional view of the cut surface in the dashed-dotted line Y1-Y2 shown in FIG. 14(A). The transistor 100 shown in FIG. 14 includes a gate electrode 203a provided over a substrate 50 , a gate insulating film 202 formed over the substrate 50 and the gate electrode 203a , and a gate insulating film 202 . via the semiconductor layer 201 overlapping the gate electrode 203a, the gate insulating film 202 and the insulating film 214 on the semiconductor layer 201, the insulating film 216 on the insulating film 214, The insulating film 214 and the openings 141a and 141b of the insulating film 216 have a pair of conductive layers 204a and 204b in contact with the semiconductor layer 201 . In addition, the insulating film 218 may be provided on the transistor 100 , more specifically, on the conductive layer 204a , the conductive layer 204b , and the insulating film 216 .

Fig. 15A is a top view of a transistor 100 which is a semiconductor device according to one embodiment of the present invention, and Fig. 15B is a dash-dotted line X1-X2 shown in Fig. 15A. It corresponds to the cross-sectional view of the cross section of FIG. 15(C), and corresponds to the cross-sectional view of the cross-section in the dashed-dotted line Y1-Y2 shown in FIG. 15(A). The transistor 100 shown in FIG. 15 differs from the transistor 100 shown in FIG. 14 in the shape of the insulating films 214 and 216 . Specifically, the insulating films 214 and 216 of the transistor 100 shown in FIG. 15 are provided in an island shape on the channel region of the semiconductor layer 101 . The other configuration is the same as that of the transistor 100 shown in Fig. 14, and the same effect is exhibited.

In each of the transistors 100 shown in FIGS. 14 and 15 , a semiconductor layer 201 is covered with an insulating film 214 and an insulating film 216 when a pair of conductive layers 204a and 204b are formed. Therefore, the semiconductor layer 201 is not damaged by etching to form the pair of conductive layers 204a and 204b. In addition, by forming the insulating film 214 and the insulating film 216 as oxide insulating films containing nitrogen and having a small amount of defects, variations in electrical characteristics are suppressed and a transistor with improved reliability can be manufactured.

In addition, the transistor 100 may have an electrode 203b over the insulating film 218 as shown in FIG. 16 . Fig. 16(A) is a top view of a transistor 100 that is a semiconductor device of one embodiment of the present invention, and Fig. 16(B) is between the dashed-dotted line X1-X2 shown in Fig. 16(A). It corresponds to the cross-sectional view of the cut surface in FIG. 16(C), and corresponds to the cross-sectional view of the cross-section in the dashed-dotted line Y1-Y2 shown in FIG. 16(A). 16 shows a configuration in which the electrode 203b is connected to the gate electrode 203a via the opening 142c and the opening 142d provided in the insulating film 214 and the insulating film 216, but the electrode 203b It is good also as a structure which does not connect and the gate electrode 203a. When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the respective electrodes.

As shown in Fig. 16, when the side surface of the semiconductor layer 201 and the electrode 203b face each other in the channel width direction, or in the channel width direction, the gate electrode 203a and the electrode 203b, By surrounding the semiconductor layer 201 with the gate insulating film 202 and the insulating film 214 , the insulating film 216 and the insulating film 218 interposed therebetween, the region through which carriers flow in the semiconductor layer 201 is the gate insulating film 202 . ) and in the interface between the insulating film 214 and the semiconductor layer 201 as well as in the interior of the semiconductor layer 201 , the carrier movement amount in the transistor 100 increases. As a result, the on-state current of the transistor 100 increases and the field effect mobility increases. In addition, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201 or an end including the side surface and its vicinity, the generation of a parasitic channel in the side surface or the end of the semiconductor layer 201 is suppressed. can do.

In addition, in FIG. 16, as an example of the semiconductor layer 201, the structure which laminates|stacks the semiconductor layer 201b on the semiconductor layer 201a is shown. Here, for example, in the semiconductor layer 201b, the energy at the lower end of the conduction band is closer to the vacuum level than that of the semiconductor layer 201a. The difference in energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less. , or 0.4 eV or less.

As the semiconductor layer 201a, the semiconductor layer 101b shown in Embodiment 3 may be referred to. For example, you may refer to the preferable range of the atomic ratio of indium, element M, and zinc which the semiconductor layer 101b has. In addition, as the semiconductor layer 201b, the insulator layer 101c shown in Embodiment 3 may be referred. For example, you may refer to the preferable range of the atomic ratio of indium, element M, and zinc which the insulator layer 101c has.

[Modified example of transistor]

Modified examples of the transistor 100 are shown in FIGS. 30 to 33 . For example, the transistor 100 may have a structure shown in FIG. 30 . Fig. 30 is different from Fig. 12 in the shape of the conductive layer 104a and the conductive layer 104b. Fig. 30(B) shows a cross section of a plane perpendicular to Fig. 30(A) passing through the dash-dotted line A-B shown in Fig. 30(A).

In addition, the transistor 100 may have the structure shown in FIG. In Fig. 12, the insulator layer 101c is in contact with the upper surfaces of the conductive layer 104a and the conductive layer 104b, whereas in Fig. 31, the insulator layer 101c is in contact with the lower surfaces of the conductive layer 104a and the conductive layer 104b. Fig. 31(B) shows a cross section of a plane perpendicular to Fig. 31(A) passing through the dash-dotted line A-B shown in Fig. 31(A). With such a configuration, when forming each film constituting the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c, the film can be continuously formed without contact with the atmosphere, so that each interfacial defect can be formed. can be reduced.

In addition, the transistor 100 may have the structure shown in FIG. Fig. 32(B) shows a cross section of a plane perpendicular to Fig. 32(A) passing through the dash-dotted line AB shown in Fig. 32(A). FIG. 32 is different from FIG. 12 in that it does not include the conductive layer 104a and the conductive layer 104b. Here, as shown in FIG. 32C, the transistor 100 may include a low resistance layer 171a and a low resistance layer 171b. The low-resistance layer 171a and the low-resistance layer 171b preferably function as a source region or a drain region. In addition, impurities may be added to the low-resistance layer 171a and the low-resistance layer 171b. By adding impurities, the resistance of the semiconductor layer 101 can be lowered. Examples of impurities to be added include argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, zirconium, It is preferable to add at least one selected from niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. The low-resistance layer 171a and the low-resistance layer 171b, for example, contain the above impurity elements in the semiconductor layer 101 at 5×10 ¹⁹ atoms/cm 3 or more, preferably 1×10 ²⁰ atoms/cm 3 or more. , more preferably 2×10 ²⁰ atoms/cm 3 or more, more preferably 5×10 ²⁰ atoms/cm 3 or more. Fig. 32D is an enlarged view of the region 324 of Fig. 32C.

In addition, there are cases where impurities such as unnecessary hydrogen can be trapped in a region having such a low resistance. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region is lowered, so that good characteristics can be obtained as characteristics of the transistor 100 .

In addition, the transistor 100 may have the structure shown in FIG. In FIG. 33 , the shapes of the insulator layer 101c and the gate insulating film 102 are different from those of FIG. 32 . Fig. 33(B) shows a cross section of a plane perpendicular to Fig. 33(A) passing through the dash-dotted line A-B shown in Fig. 33(A).

In addition, in the structure shown in FIGS. 30 to 33, the structure in which the insulator layer 101a and the insulator layer 101c are provided in contact with the semiconductor layer 101b has been described, but the insulator layer 101a or the insulator layer 101c It is good also as a structure which does not provide one or both of them.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 4)

In this embodiment, an example of the display device including the transistor illustrated in the above embodiment will be described below with reference to FIGS. 34 to 36 .

34 is a top view showing an example of a display device. The display device 700 shown in FIG. 34 includes a pixel portion 702 provided on a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701; a sealant 712 disposed to surround the pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 , and a second substrate 705 provided to face the first substrate 701 . . Further, the first substrate 701 and the second substrate 705 are sealed with a sealing material 712 . That is, the pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 are sealed by the first substrate 701 , the sealing material 712 , and the second substrate 705 . Although not shown in FIG. 34 , a display element is provided between the first substrate 701 and the second substrate 705 .

In addition, the display device 700 has a pixel portion 702 , a source driver circuit portion 704 , and a gate driver circuit portion 706 in an area different from the area surrounded by the sealant 712 on the first substrate 701 . , and an FPC terminal portion 708 (FPC: Flexible printed circuit) electrically connected to the gate driver circuit portion 706 are provided. Further, an FPC 716 is connected to the FPC terminal 708, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716. . A signal line 710 is connected to the pixel portion 702 , the source driver circuit portion 704 , the gate driver circuit portion 706 , and the FPC terminal portion 708 , respectively. Various signals supplied by the FPC 716 are a pixel portion 702 , a source driver circuit portion 704 , and a gate driver circuit portion 706 via a signal line 710 .

In addition, a plurality of gate driver circuit units 706 may be provided in the display device 700 . Note that, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702 is shown, but it is limited to this configuration doesn't happen For example, only the gate driver circuit portion 706 may be formed on the first substrate 701 , or only the source driver circuit portion 704 may be formed on the first substrate 701 . In this case, a substrate on which a source driver circuit or a gate driver circuit is formed (eg, a driving circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701 . In addition, the connection method of the separately formed driving circuit board is not specifically limited, COG (Chip On Glass) method, a wire bonding method, etc. can be used.

In addition, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a wiring portion or a plurality of transistors, and include a semiconductor device of one embodiment of the present invention. can be applied.

Also, the display device 700 may include various elements. The element is, for example, a liquid crystal element, an EL (electroluminescence) element (an EL element containing an organic and inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue color) LEDs, etc.), transistors (transistors that emit light according to current), electron-emitting devices, electronic inks, electrophoretic devices, grating light valves (GLVs), plasma displays (PDPs), MEMS (micro-electro-mechanical systems) Display element, digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type MEMS display element, optical interference method MEMS display element , an electrowetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, and the like. Besides these, you may have a display medium whose contrast, luminance, reflectance, transmittance, etc. are changed by an electrical or magnetic action. As an example of a display device using an EL element, there is an EL display or the like. As an example of a display device using an electron-emitting device, there is a field emission display (FED) or a surface-conduction electron-emitter display (SED). Examples of the display device using the liquid crystal element include a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, and a projection liquid crystal display). An example of a display device using electronic ink or an electrophoretic element includes electronic paper and the like. In the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, part or all of the pixel electrode may be made of aluminum, silver, or the like. In that case, it is also possible to provide a storage circuit such as an SRAM under the reflective electrode. Thereby, power consumption can be further reduced.

In addition, as a display method in the display device 700, a progressive method, an interlace method, etc. can be used. In addition, color elements controlled by pixels in color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in the pentile arrangement, one color element may be constituted by two color components among RGB, and two different colors may be selected and constituted by the color element. Alternatively, one or more colors of yellow, cyan, magenta and the like may be added to RGB. Further, the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display display device, and may be applied to a monochrome display display device.

In addition, in order to use white light W for a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) to display a display device in full color, you may use a coloring layer (it is also called a color filter.). The colored layer can be used, for example, in an appropriate combination of red (R), green (G), blue (B), yellow (Y), and the like. By using a colored layer, color reproducibility can be made high compared with the case where a colored layer is not used. At this time, by arranging the area|region which has a colored layer and the area|region which does not have a colored layer, you may use the white light in the area|region which does not have a colored layer directly for display. By arranging the region having no colored layer in a part, the decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30% in some cases. However, in the case of full-color display using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having respective emission colors. By using a self-luminous element, power consumption can be reduced further than the case where a colored layer is used in some cases.

In this embodiment, the structure using a liquid crystal element and an EL element as a display element is demonstrated using FIG.35 and FIG.36. Fig. 35 is a cross-sectional view taken along the dashed-dotted line Q-R shown in Fig. 34, and is a configuration in which a liquid crystal element is used as a display element. Fig. 36 is a cross-sectional view taken along the dash-dotted line Q-R shown in Fig. 34, and is a configuration in which an EL element is used as a display element.

First, common parts shown in FIGS. 35 and 36 will be described first, and then, different parts will be described below.

[Explanation of common parts of display devices]

The display device 700 shown in FIGS. 35 and 36 includes a lead wiring part 711 , a pixel part 702 , a source driver circuit part 704 , and an FPC terminal part 708 . In addition, the lead wiring unit 711 has a signal line 710 . Further, the pixel portion 702 includes a transistor 750 and a capacitor 790 (a capacitor 790a or a capacitor 790b). Also, the source driver circuit portion 704 has a transistor 752 .

Further, the signal line 710 is formed in the same process as the conductive film serving as the source electrode and the drain electrode of the transistors 750 and 752 . The signal line 710 may be a conductive film formed by a process different from that of the source and drain electrodes of the transistors 750 and 752, for example, a conductive film functioning as a gate electrode. When a material containing, for example, a copper element is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

As the transistor 750 and the transistor 752, the above-described transistors can be used. Although an example in which the structure of the transistor 100 shown in FIG. 13 is used for the transistor 750 and the transistor 752 is shown here, other transistors described above may be used.

In addition, the structure of the transistor 100 shown in FIG. 16 may be used for the transistor 750 and the transistor 752, for example. In this case, the electrode 203b can be formed using, for example, the same process as the formation of the conductive layer 772 and the conductive layer 784 . By using the structure of the transistor 100 shown in Fig. 16, for example, the on-state current of the transistor 750 and the transistor 752 can be increased, and the circuit operation speed can be increased. Further, in some cases, the channel width of the transistor 750 or the transistor 752 can be reduced, so that circuit integration is possible.

The transistor used in the present embodiment has an oxide semiconductor film that is highly purified and suppresses the formation of oxygen vacancies. The transistor can lower the current value (off current value) in the off state. Accordingly, the holding time of an electric signal such as an image signal can be lengthened, and the recording interval can also be set long in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, the effect of suppressing power consumption is exhibited.

In addition, the transistor used in the present embodiment can be driven at a high speed because a relatively high field effect mobility is obtained. For example, by using such a high-speed driving transistor in a liquid crystal display device, the switching transistor of the pixel part and the driver transistor used in the driving circuit part can be formed on the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driving circuit, the number of parts of the semiconductor device can be reduced. Also in the pixel portion, a high-quality image can be provided by using a transistor capable of high-speed driving.

In addition, the FPC terminal portion 708 has a connection electrode 760 , an anisotropic conductive layer 780 , and an FPC 716 . Further, the connection electrode 760 is formed in the same process as the conductive film serving as the source electrode and the drain electrode of the transistors 750 and 752 . Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive layer 780 .

In addition, as the 1st board|substrate 701 and the 2nd board|substrate 705, a glass substrate can be used, for example. Further, as the first substrate 701 and the second substrate 705 , a flexible substrate may be used. As a board|substrate which has the said flexibility, a plastic substrate etc. are mentioned, for example.

By using a flexible substrate, a flexible display device can be manufactured. When a display device has flexibility, it becomes possible to bond on a curved surface or an irregular shape, and various uses are implement|achieved.

For example, by using a flexible substrate such as a plastic substrate, the display device can be reduced in thickness and weight. In addition, for example, a display device using a flexible substrate such as a plastic substrate is difficult to break, and for example, durability against an impact at the time of dropping can be improved.

Further, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the colored film 736 are provided. is installed

In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705 . The structure 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705 . In addition, as the structure 778, a spherical spacer may be used. In addition, although the structure in which the structure 778 is provided in the 2nd board|substrate 705 side was illustrated in FIG. 35, it is not limited to this. For example, as shown in FIG. 36, the structure 778 is provided on the first substrate 701 side, or the structure 778 is provided on both the first substrate 701 and the second substrate 705. It may be configured as

35 and 36 , insulating films 764 , 766 , and 768 are provided over the transistor 750 and the transistor 752 .

The insulating films 764, 766, and 768 can be formed using the same material and manufacturing method as the insulating films 214, 216, and 218 shown in the above embodiments, respectively.

[Configuration example of a display device using a liquid crystal element as a display element]

The display device 700 shown in FIG. 35 includes a capacitor 790a. The capacitor 790a has a structure having a dielectric between a pair of electrodes. More specifically, as one electrode of the capacitor 790a, a highly conductive oxide semiconductor film formed through the same process as the oxide semiconductor film functioning as the semiconductor layer of the transistor 750 is used, and the other electrode of the capacitor 790a is used. As the side electrode, a conductive layer 772 electrically connected to the transistor 750 is used. In addition, the insulating film 768 is used as a dielectric material sandwiched between a pair of electrodes.

Here, an oxide semiconductor film with high conductivity serving as one of a pair of electrodes of the capacitor 790a will be described below.

[About highly conductive oxide semiconductor film]

When hydrogen is added to the oxide semiconductor in which oxygen vacancies are formed, hydrogen enters the oxygen vacancies sites and a donor level is formed in the vicinity of the conduction band. As a result, the oxide semiconductor becomes high in conductivity and becomes a conductor. A conductive oxide semiconductor can be referred to as an oxide conductor. In general, since an oxide semiconductor has a large energy gap, it has transparency to visible light. On the other hand, the oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band. Therefore, the effect of absorption by the donor level is small, and it has the same transmittance as the oxide semiconductor for visible light.

Here, the temperature of resistivity in each of a film formed of an oxide semiconductor (hereinafter, referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film (OC)). Describe dependencies.

The temperature dependence of the resistivity in the oxide conductor film OC is smaller than the temperature dependence of the resistivity in the oxide semiconductor film OS. Typically, the change rate of the resistivity of the oxide conductor film OC at 80K or more and 290K or less is less than ±20%. Or the rate of change of the resistivity in 150K or more and 250K or less is less than ±10%. That is, the oxide conductor is a degenerate semiconductor, and it is assumed that the conduction band and the Fermi level coincide or approximately coincide. For this reason, it is possible to use the oxide conductor film for one electrode of the capacitor 790a. Here, the oxide conductor film can be formed by, for example, forming silicon nitride on an In-M-Zn oxide.

In addition, the display device 700 shown in FIG. 35 includes a liquid crystal element 775 . The liquid crystal element 775 has a conductive layer 772 , a conductive layer 774 , and a liquid crystal layer 776 . The conductive layer 774 is provided on the side of the second substrate 705 and has a function as a counter electrode. In the display device 700 shown in FIG. 35, the alignment state of the liquid crystal layer 776 is changed according to the voltage applied to the conductive layer 772 and the conductive layer 774, so that light transmission and non-transmission are controlled, and an image is displayed. can be displayed

Further, the conductive layer 772 is connected to a conductive film serving as a source electrode and a drain electrode included in the transistor 750 . The conductive layer 772 is formed over the insulating film 768 and functions as a pixel electrode, that is, one electrode of the display element.

As the conductive layer 772, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc A conductive material having light transmission properties such as oxide or indium tin oxide to which silicon oxide is added can be used.

Moreover, although not shown in FIG. 35, it is good also as a structure in which an orientation film is provided respectively on the side of the conductive layers 772 and 774 in contact with the liquid crystal layer 776. As shown in FIG. In addition, although not shown in FIG. 35, you may provide optical members (optical board|substrate), such as a polarizing member, a retardation member, and an antireflection member, etc. suitably. For example, circularly polarized light by a polarizing substrate and a retardation substrate may be used. Moreover, you may use a backlight, a side light, etc. as a light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.

Moreover, when using a transverse electric field system, you may use the liquid crystal which shows a blue phase which does not use an alignment film. The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is raised, the blue phase is expressed immediately before transition from the cholesteric phase to the isotropic phase. Since the blue phase is only expressed in a narrow temperature range, a liquid crystal composition in which several wt% or more of a chiral agent is mixed is used for the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing the liquid crystal which shows a blue phase and a chiral agent has a short response speed, and since it is optically isotropic, an orientation treatment is unnecessary, and the viewing angle dependence is small. Moreover, since a rubbing process is also unnecessary by not having to provide an alignment film, the electrostatic breakdown caused by a rubbing process can be prevented, and the defect and damage of the liquid crystal display device in a manufacturing process can be reduced.

In addition, when a liquid crystal element is used as a display element, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB ( An Optical Compensated Birefringence) mode, a Ferroelectric Liquid Crystal (FLC) mode, an Antiferroelectric Liquid Crystal (AFLC) mode, and the like may be used.

Moreover, it is good also as a normally black type liquid crystal display device, for example, the transmissive type liquid crystal display device which employ|adopted the vertical alignment (VA) mode. Although several are mentioned as a vertical alignment mode, For example, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[Display device using light emitting element as display element]

The display device 700 shown in FIG. 36 includes a capacitor 790b. The capacitor 790b has a structure having a dielectric between a pair of electrodes. More specifically, as one electrode of the capacitor 790b, a conductive film formed in the same process as the conductive film serving as the gate electrode of the transistor 750 is used, and as the other electrode of the capacitor 790b, the transistor ( 750), a conductive film functioning as a source electrode or a drain electrode is used. In addition, an insulating film functioning as a gate insulating film of the transistor 750 is used as the dielectric interposed between the pair of electrodes.

In addition, in FIG. 36 , a planarization insulating film 770 is provided on the insulating film 768 .

As the planarization insulating film 770 , an organic material having heat resistance such as polyimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Further, the planarization insulating film 770 may be formed by laminating a plurality of insulating films formed of these materials. Moreover, as shown in FIG. 35, it is good also as a structure in which the planarization insulating film 770 is not provided.

In addition, the display device 700 shown in FIG. 36 includes a light emitting element 782 . The light emitting element 782 has a conductive layer 784 , an EL layer 786 , and a conductive layer 788 . The display device 700 shown in FIG. 36 can display an image when the EL layer 786 included in the light emitting element 782 emits light.

Further, the conductive layer 784 is connected to a conductive film serving as a source electrode and a drain electrode included in the transistor 750 . The conductive layer 784 is formed on the planarization insulating film 770 to function as a pixel electrode, that is, one electrode of the display element. As the conductive layer 784, a transparent conductive film in visible light or a reflective conductive film in visible light can be used. As the conductive film having transparency to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having reflection in visible light, for example, a material containing aluminum or silver may be used.

In the display device 700 shown in FIG. 36 , an insulating film 730 is provided over the planarization insulating film 770 and the conductive layer 784 . The insulating film 730 covers a part of the conductive layer 784 . In addition, the light emitting element 782 has a top emission structure. Accordingly, the conductive layer 788 has light-transmitting properties and transmits the light emitted from the EL layer 786 . In addition, in this embodiment, although the top emission structure is illustrated, it is not limited to this. For example, it can be applied to a bottom emission structure in which light is emitted to the conductive layer 784 side, or a dual emission structure in which light is emitted to both the conductive layer 784 and the conductive layer 788 .

In addition, a colored film 736 is provided at a position overlapping the light emitting element 782 , and a light blocking film 738 is provided at a position overlapping the insulating film 730 , the lead wiring unit 711 , and the source driver circuit unit 704 . this is installed In addition, the colored film 736 and the light-shielding film 738 are covered with an insulating film 734 . Further, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732 . In addition, in the display device 700 shown in FIG. 36, although the structure which provides the colored film 736 was illustrated, it is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, a configuration in which the colored film 736 is not provided may be employed.

The structure shown in this embodiment can be used, combining suitably with the structure shown in another embodiment.

(Embodiment 5)

In this embodiment, the display device including the semiconductor device of one embodiment of the present invention will be described with reference to FIG. 26 .

The display device shown in FIG. 26A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502 ) and a circuit disposed outside the pixel portion 502 to drive the pixel. It has a circuit part (hereinafter, referred to as a driving circuit unit 504) having an element, a circuit having an element protection function (hereinafter, referred to as a protection circuit 506), and a terminal unit 507. In addition, it is good also as a structure in which the protection circuit 506 is not provided.

Part or all of the driving circuit portion 504 is preferably formed on the same substrate as the pixel portion 502 . Thereby, the number of parts and the number of terminals can be reduced. When a part or all of the driving circuit unit 504 is not formed on the same substrate as the pixel unit 502 , a part or all of the driving circuit unit 504 is formed by COG or Tape Automated Bonding (TAB). , can be mounted.

The pixel unit 502 has a circuit (hereinafter referred to as the pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more); The driving circuit unit 504 includes a circuit for outputting a signal (scan signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving the display element of the pixel (hereinafter referred to as a gate driver 504a) Hereinafter, it has a driving circuit such as a source driver 504b).

The gate driver 504a has a shift register or the like. The gate driver 504a receives a signal for driving the shift register via a terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of wirings to which scanning signals are applied (hereinafter referred to as scanning lines GL_1 to GL_X). In addition, a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited thereto, and the gate driver 504a may supply a separate signal.

The source driver 504b has a shift register or the like. The source driver 504b receives, via a terminal portion 507, a signal (image signal) underlying the data signal in addition to a signal for driving the shift register. The source driver 504b has a function of generating a data signal to be written to the pixel circuit 501 based on the image signal. In addition, the source driver 504b has a function of controlling the output of the data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, or the like. In addition, the source driver 504b has a function of controlling the potential of the wiring to which the data signal is applied (hereinafter referred to as the data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited thereto, and the source driver 504b may supply a separate signal.

The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b may output a signal obtained by time division of an image signal as a data signal by sequentially turning on a plurality of analog switches. Alternatively, the source driver 504b may be configured using a shift register or the like.

Each of the plurality of pixel circuits 501 receives a pulse signal through one of the plurality of scan lines GL to which the scan signal is applied, and receives data through one of the plurality of data lines DL to which the data signal is applied. A signal is input. In each of the plurality of pixel circuits 501, data writing and holding of data signals is controlled by the gate driver 504a. For example, in the pixel circuit 501 of the m row and the nth column, a pulse signal is input from the gate driver 504a via a scanning line GL_m (m is a natural number equal to or less than X), and is applied to the potential of the scanning line GL_m. Accordingly, a data signal is input from the source driver 504b via the data line DL_n (n is a natural number less than or equal to Y).

The protection circuit 506 shown in FIG. 26A is connected to, for example, a scan line GL that is a wiring between the gate driver 504a and the pixel circuit 501 . Alternatively, the protection circuit 506 is connected to the data line DL, which is a wiring between the source driver 504b and the pixel circuit 501 . Alternatively, the protection circuit 506 may be connected to a wiring between the gate driver 504a and the terminal portion 507 . Alternatively, the protection circuit 506 may be connected to a wiring between the source driver 504b and the terminal portion 507 . In addition, the terminal unit 507 refers to a portion provided with terminals for inputting power and control signals and image signals to the display device from an external circuit.

The protection circuit 506 is a circuit that makes the wiring and other wirings in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected.

As shown in FIG. 26(A), by providing a protection circuit 506 in each of the pixel unit 502 and the driving circuit unit 504, overcurrent generated by ESD (Electro Static Discharge), etc. The tolerance of the display device can be improved. However, the configuration of the protection circuit 506 is not limited to this, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. It can be done in one configuration. Alternatively, the protection circuit 506 may be connected to the terminal portion 507 .

Also, in Fig. 26A, an example in which the drive circuit portion 504 is formed by the gate driver 504a and the source driver 504b is shown, but it is not limited to this configuration. For example, it may be configured such that only the gate driver 504a is formed, and a separately prepared substrate on which the source driver circuit is formed (eg, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted.

In addition, the plurality of pixel circuits 501 shown in FIG. 26A may have a configuration shown in FIG. 26B, for example.

The pixel circuit 501 shown in FIG. 26B includes a liquid crystal element 570 , a transistor 550 , and a capacitor 560 . The transistor shown in the above embodiment can be applied to the transistor 550 .

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specification of the pixel circuit 501 . The alignment state of the liquid crystal element 570 is set by the recorded data. In addition, a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501 . In addition, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, as a driving method of a display device including the liquid crystal element 570 , TN mode, STN mode, VA mode, Axially Symmetric Aligned Micro-cell (ASM) mode, Optically Compensated Birefringence (OCB) mode, and Ferroelectric (FLC) mode. Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Alignment) mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode may be used. Further, as a driving method of the display device, in addition to the above-described driving method, there are an Electrically Controlled Birefringence (ECB) mode, a Polymer Dispersed Liquid Crystal (PDLC) mode, a Polymer Network Liquid Crystal (PNLC) mode, a guest host mode, and the like. However, it is not limited to this, and various methods can be used as a liquid crystal element and its driving method.

In the pixel circuit 501 of the m-th row and the n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is the pair of the liquid crystal element 570 . It is electrically connected to the other of the electrodes. In addition, the gate electrode of the transistor 550 is electrically connected to the scan line GL_m. The transistor 550 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 is electrically connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is connected to the other of the pair of electrodes of the liquid crystal element 570 . electrically connected. In addition, the value of the potential of the potential supply line VL is appropriately set according to the specification of the pixel circuit 501 . The capacitor 560 has a function as a storage capacitor for holding recorded data.

For example, in a display device having the pixel circuit 501 of FIG. 26B, for example, the pixel circuit 501 of each row is caused by the gate driver 504a shown in FIG. 26A. are sequentially selected, and the transistor 550 is turned on to write data of the data signal.

The pixel circuit 501 in which data has been written enters the holding state when the transistor 550 is turned off. By doing this sequentially for each row, an image can be displayed.

In addition, the plurality of pixel circuits 501 shown in FIG. 26A may have a configuration shown in FIG. 26C, for example.

In addition, the pixel circuit 501 shown in FIG. 26C includes transistors 552 and 554 , a capacitor 562 , and a light emitting element 572 . The transistor shown in the above embodiment can be applied to either or both of the transistor 552 and the transistor 554 .

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is applied (hereinafter referred to as a signal line DL_n). Further, a gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is applied (hereinafter referred to as a scan line GL_m).

The transistor 552 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is the source electrode and drain electrode of the transistor 552 . electrically connected to the other side.

The capacitor 562 has a function as a storage capacitor for holding recorded data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552 .

One of the anode and the cathode of the light emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554 .

As the light emitting element 572, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used, for example. However, the light emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.

Further, a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other side.

In the display device having the pixel circuit 501 in FIG. 26C, for example, the pixel circuit 501 in each row is sequentially selected by the gate driver 504a shown in FIG. 26A. Then, the transistor 552 is turned on to write the data of the data signal.

The pixel circuit 501 in which data has been written enters the holding state when the transistor 552 is turned off. In addition, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the recorded data signal, and the light emitting element 572 emits light with a luminance according to the amount of current flowing. By doing this sequentially for each row, an image can be displayed.

The structure shown in this embodiment can be used, combining suitably with the structure shown in another embodiment.

(Embodiment 6)

Hereinafter, an example of a semiconductor device using the oxide semiconductor of one embodiment of the present invention will be described.

[Example of semiconductor device]

37A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device shown in FIG. 37A includes a transistor 100, a transistor 130, a capacitor 150, a wiring WBL, a wiring RBL, a wiring WL, It has a wiring CL, a wiring BG, and a wiring SL.

In the transistor 130 , one of a source or a drain is electrically connected to the wiring RBL and the other is electrically connected to the wiring SL, and a gate is one of the source or the drain of the transistor 100 and a capacitor element. Electrically connected to one electrode of (150). In the transistor 100, the other side of the source or the drain is electrically connected to the wiring WBL, and the first gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. Also, the wiring BG is electrically connected to the second gate of the transistor 100 . Further, a node between the gate of the transistor 130 , one of the source or drain of the transistor 100 , and one electrode of the capacitor 150 is referred to as a node FN.

In the semiconductor device shown in FIG. 37A , when the transistor 100 is in the conduction state (on state), a potential corresponding to the potential of the wiring WBL is applied to the node FN. In addition, when the transistor 100 is in a non-conductive state (off state), it has a function of holding the potential of the node FN. That is, the semiconductor device shown in FIG. 37A has a function as a memory cell of a memory device. A memory device (memory cell array) can be configured by arranging the semiconductor devices shown in FIG. 37A in a matrix.

In the case of having a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to the node FN, the semiconductor device of FIG. 37A can also function as a pixel of the display device.

The selection of the conduction state and the non-conduction state of the transistor 100 can be controlled by a potential applied to the wiring WL or the wiring BG. In addition, the threshold value of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with a small off-state current as the transistor 100, the potential of the node FN in the non-conductive state can be maintained for a long period of time. Accordingly, the refresh frequency of the semiconductor device can be reduced, and a semiconductor device with low power consumption can be realized. By using, for example, a transistor using an oxide semiconductor film as the transistor 100, a transistor with a small off-state current can be realized.

In addition, a positive potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. By using the change in the conduction state and the non-conduction state of the transistor 130 due to a change in the apparent threshold voltage, information on the potential held at the node FN can be read as data.

In addition, in order to maintain the potential held at the node FN for 10 years (3.15×10 ⁸ seconds) at 85°C, the value of the off current per 1 fF of capacitance and per 1 μm of the channel width of the transistor is 4.3 yA (Yocto Ampere: 1 yA is 10 It is preferable that it is less than ^-24 A). At this time, it is preferable that the allowable variation in the potential of the node FN is within 0.5V. Alternatively, at 95°C, the off current is preferably less than 1.5 yA.

Also, by increasing the capacitance, it is possible to hold the potential at the node FN for a longer period of time. That is, the holding time can be lengthened.

In the semiconductor device shown in FIG. 37A, by utilizing the feature that the potential of the gate electrode of the transistor 130 can be maintained, it is possible to write, hold, and read information as follows.

Recording and retention of information will be described. First, the potential of the wiring WL is set to the potential at which the transistor 100 is turned on, and the transistor 100 is turned on. Accordingly, the potential of the wiring WBL is applied to the gate electrode of the transistor 130 and the capacitor 150 . That is, a predetermined charge is applied to the gate electrode of the transistor 130 (writing). Here, it is assumed that any one of the charges (hereinafter referred to as low-level charges and high-level charges) imparting two different potential levels is applied. Thereafter, by setting the potential of the wiring WL to a potential at which the transistor 100 is turned off and turning off the transistor 100 , the charge applied to the gate electrode of the transistor 130 is maintained (retained). ).

Since the off current of the transistor 100 is very small, the electric charge of the gate electrode of the transistor 130 is maintained for a long time.

Next, the reading of information will be described. When an appropriate potential (read potential) is applied to the wiring CL in a state in which a predetermined potential (positive potential) is applied to the wiring RBL, the wiring SL is generated according to the amount of charge held in the gate electrode of the transistor 130 takes different potentials. In general, when the transistor 130 is of the n-channel type, when a high-level charge is applied to the gate electrode of the transistor 130 , the apparent threshold value (V _{th_H} ) is low at the gate electrode of the transistor 130 . This is because it is lower than the apparent threshold value (V _{th_L} ) in the case where the level charge is applied. Here, the apparent threshold voltage refers to the potential of the wiring CL required to turn the transistor 130 into an “on state”. Accordingly, by setting the potential of the wiring CL to the potential V ₀ between V _{th_H} and V _{th_L} , the charge applied to the gate electrode of the transistor 130 can be discriminated. For example, in writing, when a high-level charge is applied, when the potential of the wiring CL becomes V ₀ (>V _{th_H} ), the transistor 130 is “on”. When a low level charge is applied, the transistor 130 remains "off state" even when the potential of the wiring CL becomes V ₀ (<V _{th_L} ). For this reason, by discriminating the potential of the wiring SL, the stored information can be read. On the other hand, in order to reduce the number of wirings, for example, WBL and RBL shown in Fig. 37A may be made conductive.

In addition, when the memory cells are arranged in an array and used, it is necessary to be able to read only the desired memory cell information. When the information is not read in this way, a potential at which the transistor 130 is in an "off state" regardless of the state of the gate electrode, that is, a potential smaller than V _{th_H} may be applied to the wiring CL. Alternatively, a potential at which the transistor 130 becomes "on", ie, a potential greater than V _{th_L} , may be applied to the wiring CL regardless of the state of the gate electrode.

The semiconductor device shown in FIG. 37B is different from FIG. 37A mainly in that the transistor 130 is not provided. Also in this case, the recording and maintaining operation of information is possible by the above operation.

Next, the reading of information will be described. When the transistor 100 is turned on, the floating wire BL and the capacitor 150 conduct electricity, and electric charges are redistributed between the wire BL and the capacitor 150 . As a result, the potential of the wiring BL is changed. The amount of change in the potential of the wiring BL takes a different value depending on the potential of one electrode of the capacitor 150 (or the charge accumulated in the capacitor 150 ).

For example, the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, the capacitance component of the wiring BL is CB, and the potential of the wiring BL before the charge is redistributed. When VB0 is set, the potential of the wiring BL after the electric charges are redistributed becomes (CB×VB0+C×V)/(CB+C). Accordingly, as the state of the memory cell, assuming that the potential of one electrode of the capacitor 150 takes two states, V1 and V0 (V1 > V0), the potential ( =(CB×VB0+C×V1)/(CB+C)) is the potential (=(CB×VB0+C×V0)/(CB+C) of the wiring BL when the potential V0 is maintained. ), it can be seen that the higher

Then, by comparing the potential of the wiring BL with a predetermined potential, information can be read.

The semiconductor device shown in FIG. 37(A) or FIG. 37(B) can also be used as a memory|storage device of a CPU, for example.

Fig. 38 shows an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in Fig. 37A. In addition, Fig. 38 shows an example in which the WBL and RBL are made conductive in order to reduce the number of wirings. Fig. 38(B) shows a cross section of a plane perpendicular to Fig. 38(A) passing through the dash-dotted line A-B shown in Fig. 38(A). Fig. 38(C) shows a cross section of a plane perpendicular to Fig. 38(A) passing through the dash-dotted line C-D shown in Fig. 38(A).

The transistor 100 is preferably provided above the transistor 130 . By stacking the transistor 100 and the transistor 130 , for example, a circuit area can be reduced. As the transistor 100, for example, the transistor shown in Embodiment 3 can be used. Fig. 38 shows an example in which the transistor 100 shown in Fig. 12 is used.

Transistor 130 is constructed containing a first semiconductor material. Further, the transistor 100 is constructed by containing a second semiconductor material. Examples of the semiconductor usable as the first semiconductor material or the second semiconductor material include a semiconductor material such as silicon, germanium, gallium or arsenic, a compound semiconductor material containing silicon, germanium, gallium, arsenic or aluminum, and an organic semiconductor. material or an oxide semiconductor material.

Although the same material may be sufficient as a 1st semiconductor material and a 2nd semiconductor material, it is more preferable to set it as different semiconductor materials. Here, the case where single crystal silicon is used as the first semiconductor material and an oxide semiconductor is used as the second semiconductor material will be described.

[First Transistor]

The transistor 130 is provided on the semiconductor substrate 131 , and includes a semiconductor layer 132 formed as a part of the semiconductor substrate 131 , a gate insulating film 134 , a gate electrode 135 , and a low electrode serving as a source region or a drain region. It has a resistive layer 133a and a low resistive layer 133b.

The transistor 130 may be either a p-channel type or an n-channel type, but an appropriate transistor may be used according to the circuit configuration or driving method.

In the region where the channel of the semiconductor layer 132 is formed or in its vicinity, and the low-resistance layer 133a and the low-resistance layer 133b serving as the source region or drain region, etc., include a semiconductor such as a silicon-based semiconductor. Preferably, single crystal silicon is included. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. It is good also as a structure using silicon|silicone which has strain in a crystal lattice. Alternatively, the transistor 130 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

Further, the transistor 130 may have a region 176a and a region 176b that are a lightly doped drain (LDD) region.

The low-resistance layer 133a and the low-resistance layer 133b include, in addition to the semiconductor material applied to the semiconductor layer 132 , an element that imparts n-type conductivity such as phosphorus, or an element that imparts p-type conductivity such as boron. contains elements.

The gate electrode 135 is formed of a semiconductor material such as silicon containing an element imparting n-type conductivity such as phosphorus, or an element imparting p-type conductivity such as boron, a metal material, an alloy material, a metal oxide material, or the like. of conductive materials can be used.

Here, a transistor 190 as shown in FIGS. 29A and 29B may be used instead of the transistor 130 . Fig. 29(B) shows a cross section of a plane perpendicular to Fig. 29(A) passing through the dashed-dotted line E-F shown in Fig. 29(A). In the transistor 190 , a semiconductor layer 132 (a part of a semiconductor substrate) in which a channel is formed has a convex shape, and a gate insulating layer 134 and a gate electrode 135 are provided along side and top surfaces thereof. In addition, an element isolation layer 181 is provided between the transistors. Such a transistor 190 is also called a FIN-type transistor because the convex part of the semiconductor substrate is used. Moreover, you may have an insulating film which is in contact with the upper part of a convex part and functions as a mask for forming a convex part. In addition, although the case where the convex part is formed by processing a part of a semiconductor substrate is shown here, you may process the SOI (Silicon on Insulator) substrate to form the semiconductor layer which has a convex shape.

To cover the transistor 130 , an insulating film 136 , an insulating film 137 , and an insulating film 138 are sequentially stacked and provided.

The insulating film 136 functions as a protective film upon activation of an element that imparts conductivity added to the low-resistance layer 133a and the low-resistance layer 133b in the manufacturing process of the semiconductor device. The insulating film 136 may not be provided if unnecessary.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By performing the heat treatment, the dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137 , and the reliability of the transistor 130 can be improved.

The insulating film 138 functions as a planarization layer for flattening the level difference generated by the transistor 130 provided thereunder. The upper surface of the insulating film 138 may be planarized by a CMP method or the like.

In addition, the insulating film 136 , the insulating film 137 , and the insulating film 138 have a plug 140 electrically connected to the low resistance layer 133a or the low resistance layer 133b , and a gate electrode 135 of the transistor 130 . A plug 139 or the like for electrically connecting to and may be embedded.

A barrier film 111 is provided between the transistor 130 and the transistor 100 . The barrier film 111 is a layer having a function of suppressing diffusion of water and hydrogen from the lower layer to the upper layer. In addition, the barrier film 111 preferably has low oxygen permeability. Here, the term that water and hydrogen are difficult to diffuse indicates that the permeability of water and hydrogen is lower than, for example, silicon oxide generally used as an insulating film or the like. In addition, the low oxygen permeability|permeability means that the permeability of oxygen is low compared with the silicon oxide etc. which are generally used as an insulating film, for example.

Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST). ) can be used as a single layer or a laminated insulating film containing a so-called high-k material. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided to form an oxynitride film. A silicon oxide, silicon oxynitride or silicon nitride may be laminated on the above insulating film and used. In particular, since it is excellent also in the barrier property with respect to water and hydrogen, aluminum oxide is more preferable.

Moreover, the above-mentioned material is a material excellent in the barrier property of oxygen in addition to hydrogen and water. Accordingly, it is possible to suppress diffusion of oxygen emitted when the insulating film 114 is heated to a lower layer than the barrier film 111 . As a result, the amount of oxygen that can be released from the insulating film 114 and supplied to the semiconductor layer of the transistor 100 can be increased.

Here, in the lower layer than the barrier film 111, it is preferable to reduce hydrogen, water, etc. by heat treatment, for example. The heat treatment conditions may be, for example, 170° C. or higher under an inert gas atmosphere or a reduced pressure atmosphere.

In the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment may also serve as a treatment (also referred to as hydrogenation treatment) of terminating the number of unpaired bonds in silicon (also referred to as dangling bonds) with hydrogen. can

A conductive layer 151 , a conductive layer 152a , and a conductive layer 152b are provided as if the barrier film 111 is interposed therebetween to form the capacitor 150 . The conductive layer 151 is electrically connected to the conductive layer 104a of the transistor 100 .

An insulating film 114 is provided to cover the barrier film 111 , the conductive layer 152a , the conductive layer 152b , the conductive layer 105 , and the like. For the insulating film 114 , for example, reference is made to the description of the insulating film 114 in FIG. 12 .

[Second Transistor]

A transistor 100 is provided on the insulating film 114 . In the example shown in FIG. 38 , the transistor shown in FIG. 12 is used as the transistor 100 .

Further, the transistor 100 shown in FIG. 38 has a conductive layer 105 functioning as a second gate electrode. The conductive layer 105 may be formed simultaneously with the conductive layer 152a and the conductive layer 152b which form part of the capacitor 150 . By forming these conductive layers simultaneously, for example, a process can be simplified.

Further, an insulating film 112 , an insulating film 113 , and an insulating film 116 are provided to cover the transistor 100 .

For the insulating film 112 , like the barrier film 111 , it is preferable to use a material in which water or hydrogen is difficult to diffuse. In particular, it is preferable to use a material that hardly permeates oxygen.

In addition, the insulating film 112 may have a laminated structure of two or more layers. In that case, for example, it is preferable that the insulating film 112 has a two-layer laminate structure, and a material in which water or hydrogen hardly diffuses is used for the upper layer. For the lower layer, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used. The insulating film provided as the lower layer is an insulating film from which oxygen is released by heating, such as the insulating film 114 , and may be configured to supply oxygen also from the upper side of the semiconductor layer 101 via the gate insulating film 102 .

By covering the semiconductor layer 101 with the insulating film 112 , it is possible to suppress the release of oxygen from the semiconductor layer 101 upward from the insulating film 112 . In addition, since oxygen desorbed from the insulating film 114 or the like can be confined below the insulating film 112 , the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

In addition, by providing the insulating film 112, it is possible to suppress mixing of water or hydrogen into the oxide semiconductor from the outside. Accordingly, it is possible to realize a highly reliable transistor in which variations in electrical characteristics are suppressed.

As the insulating film 113, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and is provided in a stacked or single layer.

The insulating film 116 covering the transistor 100 functions as a planarization layer covering the concavo-convex shape of the lower layer. In addition, the insulating film 113 may have a function as a protective film at the time of forming the insulating film 116 into a film. The insulating film 113 may not be provided if unnecessary. As the insulating film 116, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and it is provided in a stacked or single layer.

A plug 321 , a plug 322 , and a plug 123 electrically connected to the conductive layer 104b are embedded in the insulating film 112 , the insulating film 113 , and the insulating film 116 .

A wiring 124 and the like electrically connected to the plug 322 are provided on the insulating film 116 .

Moreover, as shown in FIG. 38, it is good also as a structure in which the insulating film 137 containing the same material as the barrier film 111 is provided on the insulating film 136 containing hydrogen. With such a configuration, it is possible to effectively suppress the upward diffusion of water and hydrogen remaining in the insulating film 136 containing hydrogen.

wirings such as wiring 124 and wiring 166 , conductive layers such as conductive layer 143 , conductive layer 151 , conductive layer 152a , conductive layer 152b and conductive layer 251 , and a plug; For the plugs such as 123, plug 139, plug 140, plug 164, and plug 165, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used as a material. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Further, a material such as titanium nitride or titanium may be used by laminating it with other materials.

[Example of production method]

Next, an example of a method of manufacturing the semiconductor device of FIG. 38 will be described with reference to FIGS. 39 to 42 .

First, the semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. In addition, as the semiconductor substrate 131, an SOI substrate may be used. Hereinafter, a case in which single crystal silicon is used as the semiconductor substrate 131 will be described.

Subsequently, an isolation layer (not shown) is formed on the semiconductor substrate 131 . The device isolation layer may be formed using a Local Oxidation of Silicon (LOCOS) method, a Shallow Trench Isolation (STI) method, a mesa isolation method, or the like.

When the p-type transistor and the n-type transistor are formed on the same substrate, an n-well or a p-well may be formed in a part of the semiconductor substrate 131 . For example, a p-well may be formed by adding an impurity element such as boron that imparts p-type conductivity to the n-type semiconductor substrate 131, and an n-type transistor and a p-type transistor may be formed on the same substrate. .

Subsequently, an insulating film serving as the gate insulating film 134 is formed on the semiconductor substrate 131 . For example, a silicon oxide layer is formed by oxidizing the surface of the semiconductor substrate 131 . Alternatively, after the silicon oxide is formed by the thermal oxidation method, the surface of the silicon oxide film is nitrided by performing a nitridation treatment to form a laminated structure of the silicon oxide film and the silicon oxynitride film. Alternatively, silicon oxide, silicon oxynitride, tantalum oxide that is a high-k material (also referred to as a high-k material), metal oxide such as hafnium oxide, hafnium oxide, hafnium silicate, zirconium oxide, aluminum oxide, titanium oxide, or lanthanum oxide A rare earth oxide or the like may be used.

The insulating film is formed by a sputtering method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic CVD (MOCVD) method, a plasma enhanced CVD (PECVD) method, etc.), a molecular beam epitaxy (MBE) method, and an atomic (ALD) method. You may form by forming into a film by the Layer Deposition method or the PLD (Pulsed Laser Deposition) method or the like.

Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like, or an alloy material or compound material containing these metals as a main component. Polycrystalline silicon to which impurities such as phosphorus have been added can also be used. Moreover, you may use the laminated structure of a metal nitride film and the said metal film. As the metal nitride, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing a metal nitride film, the adhesiveness of a metal film can be improved, and peeling can be prevented.

The conductive film can be formed by a sputtering method, vapor deposition method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.) or the like. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Then, a resist mask is formed on the conductive film by lithography or the like, and unnecessary portions of the conductive film are removed. Thereafter, by removing the resist mask, the gate electrode 135 can be formed.

Here, the processing method of the to-be-processed film is demonstrated. As the processing method, various microfabrication techniques can be used. For example, a method of applying a slimming treatment to a resist mask formed by a photolithography method or the like may be used. Alternatively, a dummy pattern may be formed by a photolithography method or the like, the dummy pattern may be removed after forming a sidewall on the dummy pattern, and the film to be processed may be etched using the remaining sidewall as a resist mask. In addition, as etching of the film to be processed, in order to realize a high aspect ratio, it is preferable to use anisotropic dry etching. Moreover, you may use the hard mask which consists of an inorganic film or a metal film.

As the light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet rays, KrF laser light, ArF laser light, etc. can also be used. Alternatively, exposure may be performed by an immersion exposure technique. In addition, as the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. Also, instead of the light used for exposure, an electron beam may be used. The use of extreme ultraviolet light, X-rays or electron beams is preferable because very fine processing is possible. In addition, when exposure is performed by scanning beams, such as an electron beam, a photomask is unnecessary.

Moreover, before forming the resist film used as a resist mask, you may form the organic resin film which has the function of improving the adhesiveness of a to-be-processed film and a resist film. The organic resin film can be formed to flatten the surface by covering the step difference in the lower layer by, for example, a spin coating method, and the thickness variation of the resist mask provided on the upper layer of the organic resin film can be reduced. In addition, when performing particularly fine processing, as the organic resin film, it is preferable to use a material that functions as an antireflection film for light used for exposure. As an organic resin film which has such a function, there exist a BARC (Bottom Anti-Reflection Coating) film|membrane etc., for example. The organic resin film may be removed simultaneously with the removal of the resist mask, or may be removed after the resist mask is removed.

After this, for the description of the processing using the resist mask, for example, the processing method described for the gate electrode 135 may be referred to. In addition, in this specification, description of the resist removal after etching a to-be-processed film may be abbreviate|omitted.

After the gate electrode 135 is formed, a sidewall covering the side surface of the gate electrode 135 may be formed. The sidewall may be formed by forming an insulating film thicker than the thickness of the gate electrode 135 and then applying anisotropic etching to leave the insulating film on only the side surface of the gate electrode 135 .

Although FIG. 39 shows an example in which the gate insulating film is not etched when the sidewall is formed, the insulating film serving as the gate insulating film 134 may be etched simultaneously when the sidewall is formed. In this case, the gate insulating layer 134 is formed under the gate electrode 135 and the sidewall.

Subsequently, an element imparting n-type conductivity, such as phosphorus, to a region where the gate electrode 135 (and sidewall) of the semiconductor substrate 131 is not provided, or an element imparting p-type conductivity such as boron add A schematic cross-sectional view at this stage corresponds to Fig. 39A.

Subsequently, after the insulating film 136 is formed, heat treatment is performed, for example, for activation of the above-described element imparting conductivity. The heat treatment can be performed under an atmosphere of an inert gas such as a rare gas or nitrogen gas, or under a reduced pressure atmosphere, for example, 400° C. or higher and less than the strain point of the substrate.

The insulating film 136 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and is provided as a laminate or a single layer. The insulating film 136 can be formed using a sputtering method, a CVD method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method, PLD method, or the like. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

At this stage, the transistor 130 is formed. In addition, the third transistor 160 may be formed in the same manner as in forming the transistor 130 .

Subsequently, an insulating film 137 and an insulating film 138 are formed.

For the insulating film 137 , silicon nitride (SiNOH) containing oxygen and hydrogen may be used in addition to the material that can be used for the insulating film 136 . In addition, the insulating film 138 is formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen or nitrous oxide in addition to the material that can be used for the insulating film 136, and is formed by reacting silicon oxide with good step coverage. It is preferable to use

The insulating film 137 and the insulating film 138 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. have. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Subsequently, the upper surface of the insulating film 138 is planarized using a CMP method or the like. In addition, a planarization film may be used as the insulating film 138 . In that case, it is not necessarily necessary to planarize by a CMP method or the like. For the formation of the planarization film, for example, an atmospheric pressure CVD method, a coating method, or the like can be used. As a film|membrane which can be formed using the atmospheric pressure CVD method, BPSG (Boron Phosphorus Silicate Glass) etc. are mentioned, for example. Moreover, as a film|membrane which can be formed using the coating method, HSQ (hydrogen silsesquioxane) etc. are mentioned, for example. Thereafter, a heat treatment for terminating the dangling bonds in the semiconductor layer 132 by hydrogen desorbed from the insulating film 137 may be performed.

Then, openings are formed in the insulating film 136, the insulating film 137, and the insulating film 138 to the low resistance layer 133a, the low resistance layer 133b, the gate electrode 135, and the like (Fig. 39(B)). ) Reference). Thereafter, a conductive film is formed so as to fill the opening (see Fig. 39(C)). Thereafter, a plug 139, a plug 140, or the like is formed by applying a planarization process to the conductive film so that the upper surface of the insulating film 138 is exposed (refer to FIG. 39(D)). The conductive film can be formed, for example, by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD.

Subsequently, an insulating film 215 is formed over the insulating film 138 . The insulating film 215 may be formed using the same material and method as the insulating film 136 . After the insulating film 215 is formed, heat treatment may be performed.

The third heat treatment can be performed under the conditions exemplified in the description of the laminate structure. For example, the conditions and the like described in the first heat treatment can be used.

Subsequently, an opening is formed in the insulating film 215 . Thereafter, a conductive film is formed to fill the opening, and planarization treatment is applied to the conductive film so that the upper surface of the insulating film 215 is exposed, whereby the conductive layer 251, the conductive layer 143, the conductive layer 151, etc. to form (see FIG. 39(E)). When a conductive film is formed in the opening, for example, after forming a material such as titanium nitride or titanium in the opening, another conductive material may be laminated. For example, by using titanium nitride or titanium as the lower layer of the laminated film, the adhesion to the opening can be improved.

Then, the barrier film 111 is formed into a film, and an opening part is formed (refer FIG. 40(A)). The barrier film 111 can be formed using, for example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, PLD method, or the like. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Subsequently, conductive films to be the conductive layer 105 , the conductive layer 152a , and the conductive layer 152b are formed. Thereafter, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see Fig. 40B).

Next, an insulating film 114 is formed. The insulating film 114 can be formed using, for example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, PLD method, or the like. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

In order to make the insulating film 114 contain oxygen excessively, for example, the insulating film 114 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after formation to form a region containing excessive oxygen, or both means may be combined.

For example, oxygen (containing at least any one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after formation to form a region containing excess oxygen. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like can be used.

For the oxygen introduction treatment, a gas containing oxygen can be used. As gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide etc. can be used, for example. In addition, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be contained. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

Further, after the insulating film 114 is formed, a planarization treatment using a CMP method or the like may be performed in order to increase the flatness of the upper surface thereof.

Next, a semiconductor film serving as the insulator layer 101a and a semiconductor film serving as the semiconductor layer 101b are sequentially formed (see Fig. 40(C)). It is preferable to continuously form the semiconductor film without contact with the atmosphere. The semiconductor serving as the insulator layer 101a and the semiconductor serving as the semiconductor layer 101b may be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

In addition, when an In-Ga-Zn oxide layer is formed as a semiconductor serving as the insulator layer 101a and a semiconductor serving as the semiconductor layer 101b by MOCVD, trimethylindium, trimethylgallium, dimethylzinc, etc. good to use Moreover, it is not limited to the combination of the said raw material gas, You may use triethyl indium etc. instead of trimethyl indium. Moreover, you may use triethyl gallium etc. instead of trimethyl gallium. Further, diethyl zinc or the like may be used instead of dimethyl zinc.

Here, after the insulator layer 101a is formed, oxygen may be introduced into the insulator layer 101a. For example, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after film formation to form a region containing excess oxygen. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like can be used.

For the oxygen introduction treatment, a gas containing oxygen can be used. As gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide etc. can be used, for example. In addition, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be contained. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

After the insulator layer 101a and the semiconductor layer 101b are formed, a heat treatment may be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. In addition, after heat processing in an inert gas atmosphere, you may perform the atmosphere of heat processing in the atmosphere containing 10 ppm or more of oxidizing gas in order to supplement the oxygen desorbed. The heat treatment may be performed immediately after forming the semiconductor film, or after processing the semiconductor film to form the island-shaped insulator layers 101a and 101b. By the heat treatment, oxygen is supplied to the semiconductor film from the insulating film 114 or the oxide film, and oxygen vacancies in the semiconductor film can be reduced.

Thereafter, using a resist mask, a laminated structure of the island-shaped insulator layer 101a and the island-shaped semiconductor layer 101b is formed (see Fig. 40(D)). In addition, when the semiconductor film is etched, a part of the insulating film 114 is etched, and the insulating film 114 in a region not covered with the insulator layer 101a and the semiconductor layer 101b is thinned in some cases. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 is not lost by the etching.

Further, depending on the etching conditions of the semiconductor film, the resist may be lost during the etching process. Therefore, a material with high etching resistance, for example, a so-called hard mask made of an inorganic film or a metal film may be used. Here, an example in which a conductive film is used as the hard mask 281 is shown. FIG. 41A shows an example in which a semiconductor film is processed using a hard mask 281 to form an insulator layer 101a and a semiconductor layer 101b. Here, when a material that can be used as the conductive layer 104a and the conductive layer 104b is used for the hard mask 281, the hard mask 281 is processed to form the conductive layer 104a and the conductive layer 104b. can be formed By using such a method, for example, the transistor 100 shown in FIG. 30 can be manufactured.

After the structure shown in FIG. 40D is formed, openings leading to the conductive layer 151, the conductive layer 251, etc. are provided in the insulating film 114 (refer to FIG. 41B). Thereafter, a conductive film to be the conductive layer 104a, the conductive layer 104b, or the like is formed so as to fill the opening provided in the insulating film 114 . Formation of the conductive film used as the conductive layer 104a, the conductive layer 104b, etc. is, for example, sputtering method, CVD method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or PLD method. It can be formed using a method or the like. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Next, using a resist mask, unnecessary portions of the conductive film to be the conductive layer 104a, the conductive layer 104b, etc. are removed by etching, and the conductive layer 104a, the conductive layer 104b, etc. are formed ( 41(C)). Here, when the conductive film is etched, a part of the upper part of the semiconductor layer 101b or the insulating film 114 is etched, and the conductive layer 104a and the portion not overlapping the conductive layer 104b are thinned in some cases. Therefore, it is preferable to form the thickness of the semiconductor film used as the semiconductor layer 101b in advance in consideration of the depth to be etched.

Next, an insulator layer 101c and a gate insulating film 102 are formed. Thereafter, processing is performed by etching using a resist mask (refer to Fig. 42A). Next, a conductive film to be the gate electrode 103 is formed, and the conductive film is processed using a resist mask to form the gate electrode 103 (see Fig. 42B).

In addition, regarding the film-forming method of the insulator layer 101c, it is good to refer to the insulator layer 101a, for example.

In addition, after forming the insulator layer 101c, oxygen may be introduced into the insulator layer 101c. For example, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101c after film formation to form a region containing excess oxygen. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like can be used.

For the oxygen introduction treatment, a gas containing oxygen can be used. As gas containing oxygen, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide etc. can be used, for example. In addition, in the oxygen introduction treatment, the gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be contained. For example, a mixed gas of carbon dioxide, hydrogen, and argon may be used.

At this stage, the transistor 100 is formed.

Next, an insulating film 112 is formed. The insulating film 112 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. In particular, when the insulating film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be improved. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

After the insulating film 112 is formed, a heat treatment may be performed. Oxygen vacancies in the semiconductor layer 101 can be reduced by supplying oxygen from the insulating film 114 or the like to the semiconductor layer 101 by the heat treatment.

In addition, the insulating film 112 may have a laminated structure of two or more layers.

Subsequently, the insulating film 113 is formed. The insulating film 113 can be formed using, for example, a sputtering method, a CVD method (including thermal CVD, MOCVD, PECVD, etc.), MBE method, ALD method, or PLD method. In particular, when the film is formed by a CVD method, preferably a plasma CVD method, it is preferable because the coating property can be made good. Further, in order to reduce the damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Then, in the insulating film 113 , the insulating film 112 , the gate insulating film 102 , and the insulating layer 101c , openings reaching the conductive layer 104a or the like are provided. Then, after a conductive film is formed to fill the opening, unnecessary portions are removed using a resist mask, and a plug 321 and a plug 322 are formed.

Subsequently, an insulating film 116 is formed. The insulating film 116 can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD. In the case where an organic insulating material such as an organic resin is used as the insulating film 116 , it may be formed using a coating method such as a spin coating method. In addition, after forming the insulating film 116, it is preferable to perform a planarization treatment on the upper surface thereof. As the insulating film 116 , a material or a forming method shown for the insulating film 138 may be used.

Subsequently, the plug 123 reaching the plug 322 and the like are formed on the insulating film 116 by the same method as described above.

Subsequently, a conductive film is formed over the insulating film 116 . Thereafter, an unnecessary portion of the conductive film is removed by etching using a resist mask in the same manner as described above to form the wiring 124 and the like.

Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 7)

In this embodiment, an example of a circuit using the transistor of one embodiment of the present invention will be described with reference to the drawings.

[Circuit configuration example]

In the structure shown in the semiconductor device to which Embodiment 1 is applied, various circuits can be comprised by making the connection structure of a transistor, wiring, and an electrode different. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device of one embodiment of the present invention will be described.

[CMOS circuit]

The circuit diagram shown in FIG. 37C shows the configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and each gate is connected. are doing In addition, in the figure, the symbol "OS" is attached|subjected to the transistor to which the 2nd semiconductor material was applied, and it is shown. Here, the CMOS circuit shown in the present embodiment can be used as a basic element of a logic circuit such as a NAND circuit, a NOR circuit, an encoder, a decoder, a MUX (multiplamplifier), and a DEMUX (demultiplexer).

[analog switch]

In addition, the circuit diagram shown in FIG. 37D shows the structure in which the source and drain of the transistor 2100 and the transistor 2200 are connected. By setting it as such a structure, it can make it function as a so-called analog switch.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 8)

In this embodiment, a display module including a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 27 .

The display module 8000 shown in FIG. 27 includes a touch panel 8004 connected to the FPC 8003 and a display panel 8006 connected to the FPC 8005 between the upper cover 8001 and the lower cover 8002 . ), a backlight 8007 , a frame 8009 , a printed circuit board 8010 , and a battery 8011 .

The semiconductor device of one embodiment of the present invention can be used for, for example, the display panel 8006 .

The shape and size of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

The touch panel 8004 can be used by superposing a resistive film type or capacitive type touch panel on the display panel 8006 . It is also possible to provide a touch panel function to the opposite substrate (sealing substrate) of the display panel 8006 . It is also possible to provide an optical sensor in each pixel of the display panel 8006 to form an optical touch panel.

The backlight 8007 has a light source 8008 . In addition, although the structure which arrange|positions the light source 8008 above the backlight 8007 was illustrated in FIG. 27, it is not limited to this. For example, it is good also as a structure which arrange|positions the light source 8008 at the edge part of the backlight 8007, and uses a light-diffusion plate further. Further, in the case of using a self-emission type light emitting element such as an organic EL element, or in the case of a reflective panel or the like, a configuration in which the backlight 8007 is not provided may be employed.

In addition to the function of protecting the display panel 8006 , the frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 . In addition, the frame 8009 may have a function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power supply for supplying power to the power supply circuit may be an external commercial power supply or a power supply using a separately installed battery 8011 . The battery 8011 may be omitted when commercial power is used.

In addition, the display module 8000 may be provided by adding members such as a polarizing plate, a retardation plate, and a prism sheet.

The display module 8000 shown in this embodiment may have flexibility. By having flexibility, it becomes possible to bond together on a curved surface or an irregular shape, and a great variety of uses is implement|achieved.

The structure shown in this embodiment can be used, combining suitably with the structure shown in another embodiment.

(Embodiment 9)

In this embodiment, the RF tag including the transistor or the memory|storage device illustrated in the said embodiment is demonstrated using FIG.

The RF tag in the present embodiment has a storage circuit inside, stores necessary information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. From these characteristics, the RF tag can be used for an individual authentication system or the like that identifies an article by reading individual information on the article or the like. In addition, very high reliability is required for use in these applications.

The configuration of the RF tag will be described with reference to FIG. 28 . 28 is a block diagram showing a configuration example of an RF tag.

As shown in Fig. 28, the RF tag 800 is an antenna for receiving a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as interrogator, reader/writer, etc.). 804). In addition, the RF tag 800 includes a rectifier circuit 805 , a constant voltage circuit 806 , a demodulation circuit 807 , a modulation circuit 808 , a logic circuit 809 , a memory circuit 810 , and a ROM 811 , have. In addition, a material capable of sufficiently suppressing the reverse current, for example, an oxide semiconductor, may be used for the transistor exhibiting the rectifying action included in the demodulation circuit 807 . Thereby, it is possible to suppress a decrease in the rectifying action due to the reverse current, and to prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made close to linear. In addition, the data transmission format is roughly divided into three types: an electromagnetic coupling method in which a pair of coils are arranged oppositely to communicate by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. . The RF tag 800 shown in this embodiment can also be used for any system.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 between the antennas 802 connected to the communication device 801 . In addition, the rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal with the antenna 804, for example, rectifies it to a half-wave double pressure, and smoothes the rectified signal by a capacitive element formed at the rear end. This is a circuit for generating an input potential. Further, a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805 . The limiter circuit is a circuit for controlling so that, when the amplitude of the input AC signal is large and the internally generated voltage is large, electric power greater than a predetermined electric power is not input to the circuit of the subsequent stage.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Further, the constant voltage circuit 806 may have a reset signal generating circuit therein. The reset signal generating circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

The demodulation circuit 807 is a circuit for demodulating an input AC signal by envelope detection and generating a demodulated signal. Further, the modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804 .

The logic circuit 809 is a circuit for analyzing and processing a demodulated signal. The storage circuit 810 is a circuit for holding input information, and has a row decoder, a column decoder, a storage region, and the like. Further, the ROM 811 is a circuit for storing a unique number (ID) and the like, and outputting according to processing.

In addition, each said circuit can cook suitably as needed.

Here, the memory circuit described in the above embodiment can be used for the memory circuit 810 . Since the memory circuit of one embodiment of the present invention can retain information even when the power is cut off, it can be suitably used for an RF tag. Further, in the memory circuit of one embodiment of the present invention, since the power (voltage) required for data writing is significantly smaller than that of a conventional nonvolatile memory, there is no difference in the maximum communication distance between data reading and writing. It is also possible In addition, it is possible to suppress the occurrence of a malfunction or erroneous recording due to insufficient power during data recording.

In addition, since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be applied to the ROM 811 . In that case, it is preferable that the producer separately prepares a command for writing data to the ROM 811 so that the user cannot freely rewrite it. By shipping the product after the producer writes down the unique number before shipment, it becomes possible to assign a unique number only to high quality products, rather than assigning a unique number to all of the manufactured RF tags. Since it is not continuous, customer management corresponding to the product after shipment becomes easy.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 10)

A semiconductor device according to one embodiment of the present invention provides a display capable of reproducing a recording medium such as a display device, a personal computer, and a recording medium (typically DVD: Digital Versatile Disc) and displaying the image. device) can be used. In addition, as electronic devices that can use the semiconductor device according to one embodiment of the present invention, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book, a video camera, a camera such as a digital still camera, a goggle type display ( head mounted display), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printers, multifunction printers, automatic teller machines (ATMs), vending machines, and the like. 57 shows a specific example of these electronic devices.

57A is a portable game machine, and includes a housing 901 , a housing 902 , a display unit 903 , a display unit 904 , a microphone 905 , a speaker 906 , an operation key 907 , and a stylus 908 . ), etc. Moreover, although the portable game machine shown in FIG.57(A) has the two display part 903 and the display part 904, the number of the display part which a portable game machine has is not limited to this.

57B is a portable data terminal, wherein the first housing 911, the second housing 912, the first display unit 913, the second display unit 914, the connection unit 915, and the operation keys 916 are shown. have the back The first display unit 913 is provided in the first housing 911 , and the second display unit 914 is provided in the second housing 912 . The first housing 911 and the second housing 912 are connected by a connecting portion 915 , and the angle between the first housing 911 and the second housing 912 is to the connecting portion 915 . can be changed by The image in the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection unit 915 . Moreover, you may make it use the display apparatus with which the function as a position input apparatus was added for at least one of the 1st display part 913 and the 2nd display part 914. In addition, the function as a position input device can be added by providing a touch panel in a display apparatus. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element also called a photosensor in the pixel portion of the display device.

FIG. 57C is a notebook PC, and includes a housing 921 , a display unit 922 , a keyboard 923 , a pointing device 924 , and the like.

57D is an electric refrigerator refrigerator, which includes a housing 931 , a door 932 for a refrigerating compartment, a door 933 for a freezer compartment, and the like.

57E is a video camera, and includes a first housing 941 , a second housing 942 , a display portion 943 , operation keys 944 , a lens 945 , a connection portion 946 , and the like. The operation key 944 and the lens 945 are provided in the first housing 941 , and the display portion 943 is provided in the second housing 942 . The first housing 941 and the second housing 942 are connected by a connecting portion 946 , and the angle between the first housing 941 and the second housing 942 is to the connecting portion 946 . can be changed by The image in the display unit 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection unit 946 .

57(F) is a normal automobile, and has a body 951, wheels 952, an instrument panel 953, a light 954, and the like.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

(Embodiment 11)

In the present embodiment, an example of use of the RF tag according to one embodiment of the present invention will be described using FIG. 56 . RF tags have a wide range of uses, but include, for example, banknotes, coins, securities, bearer bonds, identification documents (driver's license, resident's card, etc., see Fig. 56 (A)), packaging containers (wrap paper, bottles, etc.) . Glasses, etc.), food, plants, animals, human body, clothing, daily necessities, medical products including medicines or pharmaceuticals, or electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones), or It can be used by attaching to a tag attached to each article (refer to FIGS. 56(E) and 56(F)) or the like.

The RF tag 4000 according to one embodiment of the present invention is fixed to an article by attaching it to a surface or embedding it. For example, if it is a book, it is embedded in paper, and if it is a package made of an organic resin, it is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention does not impair the design of the article itself even after being fixed to the article in order to realize small size, thinness, and light weight. In addition, by installing the RF tag 4000 according to one embodiment of the present invention in banknotes, coins, securities, bearer bonds, or deeds, an authentication function can be installed, and by utilizing this authentication function, counterfeiting is prevented can be prevented In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal daily necessities, food, clothing, daily necessities, or electronic devices, etc., the efficiency of systems such as inspection systems can be improved. . In addition, in the case of vehicles, by attaching the RF tag according to one embodiment of the present invention, security against theft or the like can be improved.

As described above, by using the RF tag according to one embodiment of the present invention for each of the uses enumerated in the present embodiment, it is possible to reduce the operating power including writing and reading information, so that the maximum communication distance is long. becomes possible In addition, since information can be maintained for a very long period even when the power is cut off, it can be suitably used for applications where the frequency of writing or reading is low.

This embodiment can be implemented by appropriately combining at least a part of it with other embodiment described in this specification.

In addition, a drawing (part may be sufficient) described in any one embodiment is another part of the drawing, another drawing (part may be sufficient) described in the embodiment, and/or one or a plurality of other implementations. More drawings can be configured by combining the drawings (parts may be sufficient) described in the form.

In addition, regarding the content not prescribed in the drawings or text in the specification, one embodiment of the invention in which the content is excluded can be constituted. Alternatively, when a numerical range indicated by an upper limit value and a lower limit value is described for a certain value, an embodiment of the invention excluding a part of the range may be defined by arbitrarily narrowing the range or excluding one of the ranges. can Thereby, it can be prescribed|regulated that a prior art does not fall within the technical scope of one embodiment of this invention, for example.

As a specific example, a circuit diagram using the first to fifth transistors in a certain circuit is described. In that case, it is possible to stipulate that the circuit does not have the sixth transistor as an invention. Alternatively, it is possible to specify that the circuit does not have a capacitive element. Further, the invention can be constituted by stipulating that the circuit does not have a sixth transistor that has a certain specific connection structure. Alternatively, the invention can be constituted by stipulating that the circuit does not have a capacitive element having a specific connection structure. For example, it is possible to define the invention that the gate does not have a sixth transistor connected to the gate of the third transistor. Alternatively, it is possible to define the invention, for example, that the first electrode does not have a capacitor connected to the gate of the third transistor.

As another specific example, it is assumed that the property of a certain substance is described, for example, "a certain film is an insulating film". In that case, it is possible to define one aspect of the invention, for example, except when the insulating film is an organic insulating film. Alternatively, it is possible to define one aspect of the invention that, for example, the insulating film is an inorganic insulating film except for the case. Alternatively, it is possible to define one embodiment of the invention that, for example, the film is a conductive film except for the case. Alternatively, it is possible to define one embodiment of the invention, for example, except when the film is a semiconductor film.

As another specific example, it is assumed that a certain layered structure is described, for example, "a certain film is provided between the A film and the B film". In that case, it is possible to define the invention, for example, except for the case where the film is a laminated film of four or more layers. Alternatively, it is possible to define the invention, for example, except for the case where a conductive film is provided between the A film and the film.

In addition, in this specification and the like, it is possible to take out a part of drawings or sentences described in one embodiment to constitute one embodiment of the invention. Therefore, when a drawing or text describing a certain part is described, the content obtained by extracting the drawing or text of the part is also disclosed as one embodiment of the invention, and it is assumed that one embodiment of the invention can be constituted. And it can be said that one form of the invention is clear. For this reason, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, components, devices, and operation methods. In the drawings or sentences in which the , manufacturing method, etc. are described in the singular or plural number, it is assumed that a part thereof can be taken out to constitute one embodiment of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M<N) circuit elements (transistors, capacitors, etc.) It is possible to extract and constitute one embodiment of the invention. As another example, it is possible to extract M (M is an integer, M<N) layers from a cross-sectional view configured with N (N is an integer) layers to constitute one embodiment of the invention. As another example, it is possible to construct one embodiment of the invention by extracting M elements (M is an integer, and M<N) from a flowchart configured with N elements (N is an integer). Further, as another example, some elements are arbitrarily extracted from a sentence in which "A has B, C, D, E, or F", "A has B and E", "A It is possible to constitute one aspect of the invention such as "A has E and F", "A has C, E and F", or "A has B, C, and D and E". .

In addition, in this specification and the like, when at least one specific example is described in a drawing or text described in one embodiment, it can be easily understood by those skilled in the art to derive a higher concept of the specific example. Therefore, when at least one specific example is described in a drawing or sentence described in one embodiment, the higher concept of the specific example is also disclosed as one embodiment of the invention, and what constitutes one embodiment of the invention It is possible. And it can be said that one form of the invention is clear.

In addition, in this specification and the like, at least the contents described in the drawings (which may be a part of the drawings) are disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Therefore, if a certain content is described in the drawings, even if it is not described using text, the content is disclosed as one embodiment of the invention, and it is possible to constitute one embodiment of the invention. Similarly, a drawing from which a part of the drawing is taken out is also disclosed as one embodiment of the invention, and it is possible to constitute one embodiment of the invention. And it can be said that one form of the invention is clear.

(Example 1)

In this example, the evaluation result of the oxide semiconductor film of one embodiment of the present invention will be described.

[Production method]

Thermal oxidation was applied to the silicon wafer to form a silicon oxide film of 100 nm. Thereafter, 100 nm of In-Ga-Zn oxide was formed as an oxide semiconductor film by sputtering. As the conditions of the sputtering method, the target uses polycrystalline In-Ga-Zn oxide of In:Ga:Zn=1:1:1 (atomic ratio), the power is 0.5kW (DC), and the The distance was set to 60 mm. In addition, argon and oxygen were used as film-forming gases, and the respective flow rates were set to 30 sccm for argon and 15 sccm for oxygen. The pressure was set to 0.4 Pa. The substrate temperature was 170°C in the sample E1-1 and 300°C in the sample F1-1.

Next, heat treatment was performed. As the heat treatment conditions, heat treatment was performed at 450°C in a nitrogen atmosphere for 1 hour, and then heat treatment was performed in the same treatment chamber at 450°C in an oxygen atmosphere for 1 hour.

[XRD evaluation]

Next, the results of evaluation using the XRD apparatus will be described. The XRD apparatus evaluated each sample using the multifunctional thin film material evaluation X-ray-diffraction apparatus D8 DISCOVER Hybrid (made by Bruker AXS). 43 is an analysis result by the Out-0f-Plane method. Fig. 43 (A) shows the results of Sample E1-1 and (B) shows the results of Sample F1-1. A peak appeared in the vicinity of 2θ = 31° in any of the samples. Under the condition of forming a film at 170°C, the peak was broad, and under the condition of forming a film at 300°C, the peak tended to be sharper. Since this peak belongs to the (009) plane of the crystal|crystallization of _InGaZnO4 , it is suggested that the crystal|crystallization of the oxide semiconductor film which has c-axis orientation increases by making the film-forming temperature higher.

[Membrane density evaluation]

Next, the film density was measured. For evaluation of the film density, XRR (X-ray reflectometry) was used. The obtained film density was 6.18 [g/cm 3] for Sample E1-1 and 6.36 [g/cm 3 ] for Sample F1-1. A dense and favorable film|membrane was obtained in any condition.

[Nanobeam electron diffraction]

Next, sample E1-1 and sample F1-1 were analyzed by nanobeam electron diffraction. For the acquisition of electron diffraction, "HF-2000" manufactured by Hitachi High-Technologies was used. The acceleration voltage was set to 200 kV.

A transmission electron diffraction pattern was obtained while scanning the upper surface of each sample having the oxide semiconductor film by moving the sample stage little by little. As the electron beam, a nanobeam electron beam having a probe diameter of 1 nm was used. Moreover, the same measurement was performed in all three places of each sample. That is, in each sample, a total of three scans of scan1 to scan3 was performed.

The diffraction pattern was observed while scanning at a speed of 5 nm/sec, and a moving picture was acquired. Next, the diffraction pattern observed in the obtained moving image was converted into a still image every 0.5 seconds. The converted still image was analyzed and classified into three types: a pattern of an nc-OS film, a pattern of a CAAC-OS film, and a pattern of a spinel-type crystal structure. For Sample El-1 and Sample F1-1, Table 3 shows the number of images classified into each pattern in Scan1 to Scan3. 44 to 48 show the scan1 results of the electron diffraction pattern of the sample E1-1, and FIGS. 49 to 53 show the scan1 results of the sample F1-1. Also, among the electron diffraction results shown in Figs. 44 to 48, those judged to be the CAAC-OS film pattern are indicated by surrounding them with broken lines. In addition, among the electron diffraction results shown in Figs. 49 to 53, those judged to be the patterns of the nc-OS film are indicated by surrounding them with broken lines.

In sample E1-1, the nc ratio showed a high value of 90% or more. By making the film-forming temperature lower, it turned out that the nc ratio becomes higher. Also, in any of the samples, the sum of the nc ratio and the CAAC ratio was 100%.

(Example 2)

In this example, the film density evaluation result of In-Ga-Zn oxide and the result of thermal desorption spectroscopy (TDS) analysis are shown.

On the previously cleaned quartz substrate, an In-Ga-Zn oxide was formed by sputtering. As the target, a polycrystalline In-Ga-Zn oxide of In:Ga:Zn=1:1:1 (atomic ratio) was used. As the film forming conditions, the power supply was 100 W, argon and oxygen were used as film forming gases, and the flow rate was adjusted so that the flow rate of oxygen gas was 2% with respect to the total amount of flow rates of argon gas and oxygen gas. The pressure was set to 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. Table 4 shows film-forming conditions and film density. Samples B and D were subjected to heat treatment at 450°C after In-Ga-Zn oxide was formed by sputtering. The evaluation of the film density used XRR. As shown in Table 4, in Sample C, the density showed a high value of 6 [g/cm 3 ] or more.

Next, samples A to D were subjected to TDS analysis. The amount of outgassing having a molecular weight of 18 is shown in Figs. 54 (A) and (B). The degassing having a molecular weight of 18 is thought to be derived from H ₂ O. In Sample A, the emission amount was large, and in Sample B subjected to heat treatment, the emission amount was decreased. In Sample C having a high film density, it is considered that the amount of outgassing is small even if no heat treatment is performed, and the amount of moisture contained in the film is small.

Next, with respect to Samples A to D, the change in the crystal size (crystal size) by electron beam irradiation was evaluated. The crystal size was calculated by observing the cross section using TEM. Fig. 55 shows the result of evaluating the relationship between the cumulative irradiation amount and the crystal size by performing electron beam irradiation using TEM. In sample A, the tendency of crystal|crystallization to become large every time electron beam irradiation was performed was shown. Here, the crystal size before electron beam irradiation may be, for example, a value in which the cumulative irradiation amount is 0 [e ^- /nm 2 ] in the approximate line shown in FIG. 55 . In sample B subjected to heat treatment, the change in crystal size was small. Further, in Samples C and D with high film densities, there was no significant change in crystal size in the range of the cumulative irradiation amount of electron beams up to 4.2×10 ⁸ [e ⁻ /nm 2 ].

(Example 3)

In this example, the stability of the oxide semiconductor film was evaluated. The preparation methods of Sample 1, Sample 2, and Sample 3 are shown below.

First, an In-Ga-Zn oxide having a thickness of 100 nm is formed on a quartz substrate by RF sputtering. As the target, polycrystalline In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) was used. As for the film-forming gas, 2 sccm of oxygen gas and 98 sccm of argon gas were used. In addition, the electric power was set to 100W. In addition, the substrate temperature at the time of film-forming was made into room temperature. Here, for Sample 1, the film-forming pressure was 0.4 Pa. In addition, in Sample 2, the film-forming pressure was 1.0 Pa.

In Sample 3, an In-Ga-Zn oxide having a thickness of 100 nm was formed on a quartz substrate by DC sputtering. As the target, In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) was used. As for the film-forming gas, 10 sccm of oxygen gas and 20 sccm of argon gas were used. In addition, the electric power was set to 200W. In addition, the substrate temperature at the time of film-forming was 300 degreeC. The film-forming pressure was 0.4 Pa.

Next, heat treatment was performed for 1 hour in an atmosphere containing oxygen and nitrogen. Heat treatment temperature was made into 5 conditions of 250 degreeC, 300 degreeC, 350 degreeC, 400 degreeC, and 450 degreeC. Thereafter, the film densities of Sample 1, Sample 2, and Sample 3 were measured, including conditions in which no heat treatment was performed. For the measurement of the film density, XRR by an X-ray diffraction apparatus D8 ADVANCE manufactured by Bruker-AXS was used. The result of sample 1 is shown in FIG. 58(A), the result of sample 2 is shown in FIG. 58(B), and the result of sample 3 is shown in FIG. 58(C). The horizontal axis represents the temperature of the heat treatment. The film density of Sample 1 was from 5.9 g/cm 3 to 6.1 g/cm 3 . The film density of Sample 2 ranged from 5.6 g/cm 3 to 5.8 g/cm 3 . The film density of Sample 3 ranged from 6.2 g/cm 3 to 6.4 g/cm 3 .

Next, Sample 1, Sample 2, and Sample 3 were etched using an aqueous solution in which phosphoric acid was diluted 100 times with pure water. And the etching rate was measured by measuring the thickness before and behind an etching. The result of sample 1 is shown in FIG. 59(A), the result of sample 2 is shown in FIG. 59(B), and the result of sample 3 is shown in FIG. 59(C). As for Sample 1 and Sample 2, it turned out that the etching rate becomes low, so that the temperature of heat processing is high. It turned out that the difference by the temperature of sample 3 was small. Moreover, it turned out that the sample 1 which has not heat-processed has the etching rate lower than the sample 2 which performed the heat treatment. Moreover, it turned out that the sample 3 which has not heat-processed has the etching rate lower than the sample 1 which performed the heat treatment.

Next, sample 1, sample 2, and sample 3 were subjected to TDS analysis, and the amount of outgassing (water) having a mass-to-charge ratio of 18 was measured. For the TDS analysis, a temperature rise and desorption analyzer TDS-1200 manufactured by Denshi Chemical Co., Ltd. was used. The result of sample 1 is shown in FIG. 60(A), the result of sample 2 is shown in FIG. 60(B), and the result of sample 3 is shown in FIG. 60(C). As for Sample 1, Sample 2, and Sample 3, it was found that the higher the heat treatment temperature, the smaller the amount of degassed with a mass charge ratio of 18 decreased. Moreover, it turned out that the amount of outgassing of the sample 1 which has not heat-processed compared with the sample 2 which performed the heat treatment decreased with a mass-to-charge ratio of 18. Moreover, it turned out that the amount of outgassing of the sample 3 which had not heat-processed compared with the sample 1 which performed the heat treatment decreased with a mass charge ratio of 18.

Next, the hydrogen concentrations of Sample 1 and Sample 2 were measured. The hydrogen concentration was measured by SIMS. For SIMS, IMS 7fR manufactured by CAMECA was used. The results of Sample 1 are shown in FIGS. 61A and 68A, and the results of Sample 2 are shown in FIGS. 61B and 68B. Here, in FIGS. 68A and 68B , the horizontal axis indicates the depth from the film surface, and the vertical axis indicates the hydrogen concentration. In addition, in FIGS. 61A and 61B, the average value of the hydrogen concentration from a depth of 10 nm to 60 nm is shown. In addition, in FIGS. 68(A) and 68(B), the In-Ga-Zn oxide film does not remain behind the region where the hydrogen concentration changes rapidly in the vicinity of 80 nm in depth, so that the quartz substrate may be measured There is this. In addition, in a region of less than 10 nm, there is a possibility that the surface state may be affected. Therefore, it is preferable that the hydrogen concentration of the In-Ga-Zn oxide film is expressed by, for example, an average value from a depth of 10 nm to 60 nm. In Sample 1 and Sample 2, it was found that the higher the heat treatment temperature, the lower the hydrogen concentration. Moreover, it turned out that the hydrogen concentration of Sample 1 which has not heat-processed is lower than Sample 2 which performed heat treatment.

Next, the change in crystal size of Sample 1, Sample 2, and Sample 3 due to heat treatment was measured by TEM. Incidentally, the crystal size is indicated by an average value of 20 to 45 points. For TEM, a Hitachi transmission electron microscope H-9000NAR was used. The result of sample 1 is shown in FIG. 62(A), the result of sample 2 is shown in FIG. 62(B), and the result of sample 3 is shown in FIG. 62(C). It was found that Sample 1 had a crystal size of about 1.4 nm regardless of the temperature of the heat treatment. Sample 2 had a crystal size of about 1.2 nm when not subjected to heat treatment (see Fig. 67), grew to about 1.3 nm by heat treatment at 250° C., and 1.6 nm by heat treatment at 300° C. grew to some degree. In addition, in the range of 300 degreeC to 450 degreeC, there was no change in crystal size. Also in Sample 3, the crystal size was 1.5 to 1.6 nm regardless of the temperature of the heat treatment.

Next, the change in crystal size of Sample 1, Sample 2, and Sample 3 due to electron beam irradiation was measured by TEM. The result of sample 1 is shown in FIG. 63(A), the result of sample 2 is shown in FIG. 63(B), and the result of sample 3 is shown in FIG. 63(C). In Sample 1 and Sample 3, regardless of the temperature of the heat treatment, there was hardly any change in crystal size even by electron beam irradiation. Sample 2 showed an increase in crystal size by electron beam irradiation. Moreover, this tendency was so remarkable that the temperature of heat processing was low.

When the change in the crystal size by heat treatment and the change in the crystal size by electron beam irradiation are observed, it can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When Sample 1, Sample 2, and Sample 3 are classified according to the above structure, Sample 1 becomes an nc-OS film, Sample 2 becomes an a-like OS film, and Sample 3 becomes a CAAC-OS.

As described above, the nc-OS film has a higher film density, a lower etching rate, less degassing of water, and a lower hydrogen concentration than the a-like OS film. In addition, the gap cannot be filled by the heat treatment after film formation. That is, it is important to use an oxide semiconductor film, which is an nc-OS film, for the transistor at the time of film formation.

(Example 4)

In this example, the local level of the nc-OS film was evaluated. Evaluation of the local level was performed by CPM (Constant photocurrent method) measurement.

For CPM measurement, the gate electrode (tungsten) on the glass substrate, the nc-OS film on the gate electrode, the gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film, and the nc-OS film are in contact. Prepare a sample having a pair of electrodes (a laminate formed in this order of tungsten, aluminum, and titanium) and an insulator (a laminate formed in this order of silicon oxynitride and silicon nitride) on the nc-OS film and on the pair of electrodes did. Incidentally, the nc-OS film was formed to a thickness of 35 nm by AC sputtering. As the target, In-Ga-Zn oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) was used. As for the film-forming gas, 10 volume% of oxygen gas and 90 volume% of argon gas were made into. In addition, the electric power was set to 2.5 kW. In addition, the substrate temperature at the time of film-forming was made into room temperature. In addition, the film-forming pressure was 0.6 Pa.

Next, it heat-processed with respect to the produced sample. The heat treatment was performed under a nitrogen atmosphere for 1 hour, and then further performed under an atmosphere containing oxygen and nitrogen for 1 hour.

In the CPM measurement, the amount of light irradiated to the sample surface between the terminals is adjusted so that the photocurrent value becomes constant while a voltage is applied between a pair of electrodes provided in contact with the nc-OS film, and an absorption coefficient is derived from the amount of light irradiated. Here, the absorption coefficient was derived for each wavelength. In CPM measurement, the absorption coefficient in energy (converted from wavelength) according to the density of local levels increases. By multiplying the increment of this absorption coefficient by a constant, the density of localized levels in the sample can be derived.

In addition, by removing the light absorption (Urbach tail) due to the band tail from the curve of the light absorption spectrum, the absorption coefficient α by the local level can be calculated from the following equation.

α=∫[(α(E)-α _u )/E]dE

Here, E denotes energy, α(E) denotes the absorption coefficient at each energy, and α _u denotes the absorption coefficient by the Urbach tail.

Also, the slope of the Urbach tail is called the Urbach energy. The lower the Urbach energy, the fewer defects, and the higher the order of the semiconductor film, the steeper the inclination of the tail (lower part) of the level at the band end of the valence band.

64 shows the results of fitting the absorption coefficient (dotted line) measured by the spectrophotometer and the absorption coefficient (solid line) measured by CPM in an energy range equal to or greater than the energy gap of the oxide semiconductor film. Fig. 64(A) shows the result of the sample subjected to heat treatment at 300°C after film formation, (B) is the result of the sample subjected to heat treatment at 400°C after film formation, and Fig. 64(C) is the film-forming result. The results of samples subjected to heat treatment at 450°C afterward are respectively shown. The Urbach energies obtained from the absorption coefficient measured by CPM were 72.65 meV, 69.45 meV, and 70.32 meV, respectively.

In addition, the background (thin dotted line) was subtracted from the absorption coefficient derived by CPM measurement in FIG. 64, and the integral value of the absorption coefficient was derived. The results are shown in FIG. 65 . The absorption coefficients by the local level were 6.27×10 ⁻¹ cm ⁻¹ , 4.19×10 ⁻¹ cm ⁻¹ and 2.29×10 ⁻¹ cm ⁻¹ , respectively. The relationship between the temperature of the heat treatment and the absorption coefficient is shown in FIG. 66 . From Fig. 66, it can be seen that the higher the temperature of the heat treatment, the smaller the absorption coefficient, so that the density of localized states also becomes smaller.

11 area
12 zones
Area 13
14 area
15 areas
16 zones
21 repair
22 repair
23 repair
50 boards
51 insulating film
100 transistors
101 semiconductor layer
101a insulator layer
101b semiconductor layer
101c insulator layer
102 gate insulating film
103 gate electrode
104a conductive layer
104b conductive layer
105 conductive layer
111 barrier
112 insulating film
113 insulating film
114 insulating film
116 insulating film
123 plug
124 wiring
130 transistors
131 semiconductor substrate
132 semiconductor layer
133a low resistance layer
133b low resistance layer
134 Gate Insulation Film
135 gate electrode
136 insulating film
137 insulating film
138 insulating film
139 plug
140 plug
143 conductive layer
150 capacitive element
151 conductive layer
152a conductive layer
152b conductive layer
160 transistors
164 plug
165 plug
166 wiring
171a low resistance layer
171b low resistance layer
176a area
176b area
181 element isolation layer
190 transistors
191 transistor
201 semiconductor layer
201a semiconductor layer
201b semiconductor layer
202 gate insulating film
202a gate insulating film
202b gate insulating film
203a gate electrode
203b electrode
204a conductive layer
204b conductive layer
214 insulating film
215 insulating film
216 insulating film
218 insulating film
251 conductive layer
281 hard mask
321 plug
322 plug
324 area
501 pixel circuit
502 pixels
504 drive circuit
504a gate driver
504b source driver
506 protection circuit
507 terminal part
550 transistors
552 transistor
554 transistor
560 capacitive element
562 capacitive element
570 liquid crystal element
572 light emitting element
610 electron gun room
612 Optics
614 sample room
616 Optics
618 camera
620 observation room
622 film room
624 electronic
632 Fluorescent Plate
700 indicator
701 board
702 pixel part
704 source driver circuitry
705 board
706 gate driver circuitry
708 FPC terminal
710 signal line
711 wiring
712 sealant
716 FPC
730 insulating film
732 sealing film
734 insulating film
736 colored film
738 light shield
750 transistors
752 transistor
760 connection electrode
764 insulating film
766 Insulation Film
768 insulating film
770 planarization insulating film
772 conductive layer
774 conductive layer
775 liquid crystal element
776 liquid crystal layer
778 structure
780 Anisotropic Conductive Layer
782 light emitting element
784 conductive layer
786 EL layer
788 conductive layer
790 capacitive element
790a capacitive element
790b capacitive element
800 RF tag
801 communicator
802 antenna
803 radio signal
804 antenna
805 rectifier circuit
806 constant voltage circuit
807 demodulation circuit
808 modulation circuit
809 logic circuit
810 memory circuit
811 ROM
901 housing
902 housing
903 display
904 display
905 microphone
906 speaker
907 operation keys
908 stylus
911 housing
912 housing
913 display
914 display
915 connection
916 operation keys
921 housing
922 display
923 keyboard
924 pointing device
931 housing
932 Refrigerator Door
933 Freezer Door
941 housing
942 housing
943 display
944 operation keys
945 lens
946 connection
951 body
952 wheel
953 instrument panel
954 light
2100 transistors
2200 transistors
4000 RF tags
5100 pellets
5100a pellets
5100b pellets
5101 ion
5120 board
5130 target
8000 display module
8001 top cover
8002 lower cover
8003 FPC
8004 touch panel
8005 FPC
8006 display panel
8007 back light
8008 light source
8009 frames
8010 printed board
8011 battery

Claims (3)

In a semiconductor device,
a first transistor comprising silicon in a first channel formation region;
a first insulating layer over the first channel forming region;
a first conductive layer over the first insulating layer, the first conductive layer functioning as a first electrode of a capacitor;
a second insulating layer over the first conductive layer;
a second conductive layer, a third conductive layer, and a fourth conductive layer over the second insulating layer;
a third insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer;
a layer comprising a second channel forming region of a second transistor over the third insulating layer, the second channel forming region comprising an oxide semiconductor;
a fifth conductive layer over the layer including the second channel forming region, the fifth conductive layer including a region functioning as one of a source electrode and a drain electrode of the second transistor;
a fourth insulating layer over the layer comprising the second channel forming region;
a sixth conductive layer over the fourth insulating layer;
a fifth insulating layer over the sixth conductive layer; and
a seventh conductive layer on the fifth insulating layer;
the fifth conductive layer is in contact with an upper surface of the layer including the second channel forming region;
the second conductive layer functions as a first gate electrode of the second transistor;
the sixth conductive layer functions as a second gate electrode of the second transistor;
the third conductive layer functions as a second electrode of the capacitor,
The third conductive layer and the fourth conductive layer overlap the first conductive layer,
and the second conductive layer, the third conductive layer, and the fourth conductive layer comprise the same material. In a semiconductor device,
a first transistor comprising silicon in a first channel formation region;
a first insulating layer over the first channel forming region;
a first conductive layer over the first insulating layer, the first conductive layer functioning as a first electrode of a capacitor;
a second insulating layer over the first conductive layer;
a second conductive layer, a third conductive layer, and a fourth conductive layer over the second insulating layer;
a third insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer;
a layer comprising a second channel forming region of a second transistor over the third insulating layer, the second channel forming region comprising an oxide semiconductor;
a fifth conductive layer over the layer including the second channel forming region, the fifth conductive layer including a region functioning as one of a source electrode and a drain electrode of the second transistor;
a fourth insulating layer over the layer comprising the second channel forming region;
a sixth conductive layer over the fourth insulating layer;
a fifth insulating layer over the sixth conductive layer; and
a seventh conductive layer on the fifth insulating layer;
the fifth conductive layer is in contact with an upper surface of the layer including the second channel forming region;
the fifth conductive layer is in contact with an upper surface of the first conductive layer through openings provided in the second insulating layer and the third insulating layer;
the second conductive layer functions as a first gate electrode of the second transistor;
the sixth conductive layer functions as a second gate electrode of the second transistor;
the third conductive layer functions as a second electrode of the capacitor,
The third conductive layer and the fourth conductive layer overlap the first conductive layer,
and the second conductive layer, the third conductive layer, and the fourth conductive layer are provided over the second insulating layer. In a semiconductor device,
a first transistor comprising silicon in a first channel formation region;
a first insulating layer over the first channel forming region;
a first conductive layer over the first insulating layer, the first conductive layer functioning as a first electrode of a capacitor;
a second insulating layer over the first conductive layer;
a second conductive layer, a third conductive layer, and a fourth conductive layer over the second insulating layer;
a third insulating layer over the second conductive layer, the third conductive layer, and the fourth conductive layer;
a layer comprising a second channel forming region of a second transistor over the third insulating layer, the second channel forming region comprising an oxide semiconductor;
a fifth conductive layer over the layer including the second channel forming region, the fifth conductive layer including a region functioning as one of a source electrode and a drain electrode of the second transistor;
a fourth insulating layer over the layer comprising the second channel forming region;
a sixth conductive layer over the fourth insulating layer;
a fifth insulating layer over the sixth conductive layer;
a seventh conductive layer over the fifth insulating layer;
a sixth insulating layer over the seventh conductive layer; and
an eighth conductive layer on the sixth insulating layer;
In the cross-sectional view, the eighth conductive layer overlaps the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer,
the fourth insulating layer extends beyond an end of the sixth conductive layer;
the fifth conductive layer is in contact with an upper surface of the layer including the second channel forming region;
the fifth conductive layer is in contact with an upper surface of the first conductive layer through openings provided in the second insulating layer and the third insulating layer;
In a cross-sectional view, the fifth conductive layer is provided between the third conductive layer and the fourth conductive layer,
the second conductive layer functions as a first gate electrode of the second transistor;
the sixth conductive layer functions as a second gate electrode of the second transistor;
the third conductive layer functions as a second electrode of the capacitor,
The third conductive layer and the fourth conductive layer overlap the first conductive layer,
and the second conductive layer, the third conductive layer, and the fourth conductive layer are provided in the same layer.

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