JP2024055906A - Semiconductor Device - Google Patents

Abstract

[Problem] To provide a semiconductor device with good electrical characteristics. [Solution] An oxide semiconductor film is provided with an oxide semiconductor film having ...

Description

Application for application of Article 30, Paragraph 2 of the Patent Law submitted. Presented at the 61st Spring Meeting of the Japan Society of Applied Physics held at Aoyama Gakuin University Sagamihara Campus on March 18, 2014 and March 19, 2014.

The present invention relates to an object, a method, or a manufacturing method, or to a process, a machine, a manufacture, or a composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. In addition, an arithmetic device, a memory device, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, and the like), and an electronic device may include a semiconductor device.

The physical properties of oxides containing indium and zinc are interesting and have been extensively studied (
Non-Patent Document 1 and Non-Patent Document 2). In Non-Patent Document 1, In _1-x Ga _1+x O ₃ (ZnO
) _m (x is a number satisfying -1≦x≦1, m is a natural number).
For example, when powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and sintered at 1350° C., the solid solution region of the homologous phase when m=1 is x
is said to be −0.33 to 0.08, and the solid solution region of the homologous phase when m = 2 is said to be x −0.68 to 0.32.

Also, a compound represented by _AB2O4 (A and B are metals) is known as a compound having a spinel type crystal structure. Non-Patent Document 1 shows an example of _InxZnyGazOw , in which _x , _y , and _z are in the _{vicinity of ZnGa2O4} , that is, x, y, and z are in the vicinity of (x, y
It is described that when the value of z is close to (z)=(0, 1, 2), a spinel type crystal structure is likely to be formed or to be mixed.

In addition, a technology for constructing a transistor using a semiconductor material has been attracting attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have been attracting attention as other materials.

For example, techniques for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor have been disclosed (see Patent Documents 1 and 2).

Furthermore, in recent years, with the trend toward higher performance, smaller size, and lighter weight of electronic devices, there has been an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are densely integrated.

JP 2007-123861 A JP 2007-96055 A

M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350°C", J. Solid State Chem. , 1991, Vol. 93, pp. 298-315 M. Nespolo, A. Sato, T. Osawa, and H. Ohashi, "Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. X-ray Diffraction Study of 20kb Single Crystal and 50kb Twin by Reticular Merohedry" Cryst. Res. Technol. , 2000 Vol. 35, pp151-165

One aspect of the present invention is to provide a semiconductor device with good electrical characteristics.

Another objective is to provide a highly reliable semiconductor device.

Another object of the present invention is to provide a good transistor with little variation in characteristics.Another object of the present invention is to provide a semiconductor device having a memory element with good retention characteristics.Another object of the present invention is to provide a semiconductor device suitable for miniaturization.Another object of the present invention is to provide a semiconductor device with a reduced circuit area.Another object of the present invention is to provide a semiconductor device having a novel structure.

Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and will not be described in detail without departing from the spirit and scope of the present invention.
Other issues can be extracted from the drawings, claims, etc.

One embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, in which the element M is at least one selected from aluminum, gallium, yttrium, and tin, and the atomic ratio of indium, the element M, and zinc is indium:the element M
In an equilibrium diagram satisfying the relationship x:y:z, where x, y, and z are the three elements of indium, element M, and zinc, the vertices are the first coordinate (x:y:z=8:14:7), the second coordinate (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), the fourth coordinate (x:y:z=51:149:300), and the fifth coordinate (x:y:z=46:288:460)
:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z=
a ratio of the number of atoms within a range obtained by connecting a first coordinate (x:y:z=1:0:0), an eighth coordinate (x:y:z=1:0:0), and the first coordinate with a line segment in this order, the range including the first to sixth coordinates but not including the seventh and eighth coordinates, and when a plurality of electron diffraction patterns are observed by irradiating a surface on which the oxide semiconductor film is to be formed with an electron beam having a half-width of a probe diameter of 1 nm while moving a position of the oxide semiconductor film relative to a position of the electron beam, the plurality of electron diffraction patterns include 50 or more electron diffraction patterns observed at different positions from each other, and a sum of a proportion of the 50 or more electron diffraction patterns having the first electron diffraction pattern and a proportion of the 2nd electron diffraction pattern is 100%,
The first electron diffraction pattern is of an oxide semiconductor film having an asymmetric observation point or a plurality of observation points arranged in a circular pattern, and the second electron diffraction pattern is of an oxide semiconductor film having observation points located at the vertices of a hexagon.

Alternatively, in one embodiment of the present invention, an oxide semiconductor film is provided with an oxide semiconductor film having an electron beam with a probe width of 1 nm, and the oxide semiconductor film is irradiated with the electron beam while moving a position of the oxide semiconductor film and a position of the electron beam relative to a surface on which the oxide semiconductor film is to be formed. In this case, the oxide semiconductor film has 50 or more electron diffraction patterns observed at different positions, the sum of a proportion of the 50 or more electron diffraction patterns having a first electron diffraction pattern and a proportion of the 50 or more electron diffraction patterns having a second electron diffraction pattern is 100%, and a proportion of the first electron diffraction pattern is 50% or more, the first electron diffraction pattern has observation points that are not symmetric or are arranged in a circular pattern, and the second electron diffraction pattern has observation points that are located at vertices of a hexagon.

Alternatively, one aspect of the present invention is a compound represented by the formula In:M(Al, Ga, Y, or Sn):Zn=x:y
In an equilibrium diagram having vertices at coordinates x:y:z=1:0:0, coordinates x:y:z=0:1:0, and coordinates x:y:z=0:0:1, a first coordinate (x:y:z=8:14:7) and a second coordinate (x:y:z=2:
4:3), the third coordinate (x:y:z=2:5:7), and the fourth coordinate (x:y:z=51
a fifth coordinate (x:y:z=46:288:833), a sixth coordinate (x:y:z=0:2:11), a seventh coordinate (x:y:z=0:0:1), an eighth coordinate (x:y:z=1:0:0), and the first coordinate are within a range obtained by connecting, in this order, the fifth coordinate (x:y:z=46:288:833), the sixth coordinate (x:y:z=0:2:11), the seventh coordinate (x:y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate with a line segment; a position of the oxide semiconductor film and a position of an electron beam having a half width of a probe diameter of 1 nm are moved relatively with respect to a surface on which the oxide semiconductor film is to be formed, to observe 50 or more electron diffraction patterns at different positions, and the 50 or more electron diffraction patterns are any one of an electron diffraction pattern having at least a plurality of spots arranged asymmetrically, an electron diffraction pattern having a plurality of spots arranged in a circular manner, and an electron diffraction pattern having spots arranged at vertices of a hexagon, and the range includes the first to sixth coordinates;
The oxide semiconductor film does not include the coordinates A and B.

In the above structure, the oxide semiconductor film contains indium, an element M, and zinc. The element M is at least one selected from aluminum, gallium, yttrium, and tin. The atomic ratio of indium, the element M, and zinc is indium:element M
In an equilibrium diagram satisfying the relationship x:y:z, where x, y, and z are the three elements of indium, element M, and zinc, the vertices are the first coordinate (x:y:z=8:14:7), the second coordinate (x:y:z=2:4:3), the third coordinate (x:y:z=2:5:7), the fourth coordinate (x:y:z=51:149:300), and the fifth coordinate (x:y:z=46:288:460)
:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x:y:z=
It is preferable that the ratio of the number of atoms falls within a range obtained by connecting the first coordinate (x:y:z=1:0:0), the eighth coordinate (x:y:z=1:0:0), and the first coordinate with a line segment in that order, and that the range includes the first coordinate to the sixth coordinate, but does not include the seventh coordinate and the eighth coordinate.

Another embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc. The oxide semiconductor film has a plurality of crystal parts which are randomly arranged, and the average longitudinal diameter of the plurality of crystal parts is greater than or equal to 1 nm and less than or equal to 3 nm.

Another embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, in which the element M is at least one selected from aluminum, gallium, yttrium, and tin, and the atomic ratio of indium, the element M, and zinc satisfies indium:element M:z=x:y:z, and x, y, and z are each a first coordinate (x:y:z=8:14:7) in an equilibrium phase diagram with the three elements of indium, the element M, and zinc as vertices.
, the second coordinates (x:y:z=2:4:3), and the third coordinates (x:y:z=2:5:7).
, the fourth coordinate (x:y:z=51:149:300), and the fifth coordinate (x:y:z=4
6:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x
the first coordinate (x:y:z=0:0:1), the eighth coordinate (x:y:z=1:0:0), and the eighth coordinate are connected in order by a line segment, the range includes the first to sixth coordinates but does not include the seventh and eighth coordinates, and the density of the oxide semiconductor film is 90% or more of the density of a single crystal having the same atomic ratio.

Another embodiment of the present invention is an oxide semiconductor film containing indium, an element M, and zinc, where the element M is at least one selected from aluminum, gallium, yttrium, and tin. The oxide semiconductor film has a plurality of crystal parts that are randomly arranged, the crystal parts do not have orientation, and the diameters of the crystal parts in the longitudinal direction are 1 nm to 3 nm.
The density of the oxide semiconductor film is 9 times that of a single crystal having the same atomic ratio.
0% or more.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, the oxide semiconductor film has a plurality of crystal parts that do not have orientation, the average longitudinal diameter of the plurality of crystal parts is 1 nm to 3 nm, and the density of the oxide semiconductor film is 5.7 g/ ^cm to 6.49 g/cm. In the above structure, the density of the oxide semiconductor film is preferably 90% or ^more of the density of a single crystal having the same atomic ratio.

Another embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc. The oxide semiconductor film has a plurality of crystal parts that are randomly arranged, the crystal parts do not have orientation, and an average diameter A [nm] of the crystal parts in the longitudinal direction is 1 nm or more and 3 nm or less.
nm or less, and the electron beam energy is 1×10 ⁷ [e ⁻ /nm ² ] or more and 4×10 ⁸ [
After irradiation to less than e ⁻ /nm ² , the average longitudinal diameter B [nm] of the crystal portion is A×
The oxide semiconductor film has a thickness greater than 0.7 and smaller than A×1.3.

In the above structure, the oxide semiconductor film is formed by a sputtering method. A target used in the sputtering method contains indium, the element M, and zinc. The atomic ratio of indium, the element M, and zinc contained in the target is indium:the element M:zinc=
It is preferable that the ratio of the number of atoms satisfies a:b:c, and a, b, and c are within a range obtained by connecting the first coordinate (a:b:c=8:14:7), the second coordinate (a:b:c=2:4:3), the third coordinate (a:b:c=1:2:5.1), the fourth coordinate (a:b:c=1:0:1.7), the fifth coordinate (a:b:c=8:0:1), the sixth coordinate (a:b:c=6:2:1), and the first coordinate in an equilibrium phase diagram with the three elements of indium, element M, and zinc as vertices, and that the range includes the first coordinate to the sixth coordinate.

Another embodiment of the present invention is a semiconductor device including any of the above oxide semiconductor films.
In the above structure, a first conductive layer, a first insulating film in contact with a top surface and a side surface of the first conductive layer, and a pair of electrodes in contact with a top surface of the oxide semiconductor film are included.
In the above structure, the oxide semiconductor film preferably has a region in contact with an upper surface of the insulating film. In the above structure, the oxide semiconductor film preferably has a first conductive layer, a first insulating film in contact with an upper surface and a side surface of the first conductive layer, a second insulating film in contact with an upper surface of the oxide semiconductor film, and a pair of electrodes in contact with an upper surface of the oxide semiconductor film and an upper surface and a side surface of the second insulating film, and the oxide semiconductor film preferably has a region in contact with an upper surface of the first insulating film. In the above structure, the oxide semiconductor film preferably has a second oxide film in contact with an upper surface of the oxide semiconductor film. In the above structure, the electron affinity of an oxide of the oxide semiconductor film is preferably larger than that of the second oxide film. In the above structure, the second oxide film contains indium, an element M, and zinc, and the element M
is an element selected from at least one of aluminum, gallium, yttrium, and tin, and the atomic ratio of indium, element M, and zinc contained in the second oxide film is expressed as indium:element M:zinc=x ₂ :y ₂ :z ₂ , and (x ₂ :y ₂ :z ₂ ) is the first coordinate (8:1) in an equilibrium phase diagram with the three elements of indium, element M, and zinc as vertices.
4:7), the second coordinate (2:4:3), the third coordinate (2:5:7), and the fourth coordinate (
51:149:300), the fifth coordinate (1:4:10), and the sixth coordinate (1:1:4)
It is preferable that the ratio of the number of atoms in a range obtained by connecting the first coordinate, the seventh coordinate (2:2:1), and the first coordinate in order with a line segment includes the first coordinate to the seventh coordinate.

Another embodiment of the present invention is a display device including any of the above semiconductor devices and a display element.

Another embodiment of the present invention is a module including any of the above semiconductor devices or any of the above display devices and an FPC.

Another embodiment of the present invention is an electronic device including any of the above semiconductor devices, the above display devices, or the above module, and a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a semiconductor device can have good electrical characteristics.
A highly reliable semiconductor device can be provided.

Furthermore, a transistor with little variation can be provided. Further, a semiconductor device having a memory element with good retention characteristics can be provided. Further, a semiconductor device suitable for miniaturization can be provided. Further, a semiconductor device with a reduced circuit area can be provided. Further, a semiconductor device having a novel structure can be provided. Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from descriptions in the specification, drawings, claims, etc., and may be easily understood from descriptions in the specification, drawings, claims, etc.
It is possible to extract effects other than these.

FIG. 1 illustrates an atomic ratio of an oxide film according to one embodiment of the present invention. FIG. 1 illustrates an atomic ratio of an oxide film according to one embodiment of the present invention. FIG. FIG. 1 illustrates an atomic ratio of an oxide film according to one embodiment of the present invention. FIG. 2 is a graph illustrating an atomic ratio of a target according to one embodiment of the present invention. FIG. 1A and 1B are diagrams showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. FIG. 13 shows the analysis results of nc-OS by an X-ray diffraction device. FIG. 1 shows an electron diffraction pattern of nc-OS. FIG _{. 1} is a diagram illustrating a crystal of InGaZnO4. FIG. 13 is a diagram showing a band structure of a part of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. 13A and 13B show Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. FIG. 13 shows a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. FIG. 13 shows a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. FIG. 13 shows a Cs-corrected high-resolution cross-sectional TEM image of nc-OS. FIG. 13 shows a Cs-corrected high-resolution cross-sectional TEM image of nc-OS. FIG. 1 shows pellet sizes and their frequencies observed in Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. 13A and 13B are graphs showing the relationship between the atomic ratio of a target and the atomic ratio of an oxide semiconductor film. 1A and 1B are a schematic diagram illustrating a film-formation model of nc-OS and a diagram showing a pellet. FIG. 1A and 1B are a block diagram and a circuit diagram illustrating a display device. FIG. 2 is a diagram of a display module according to an embodiment. 3 shows an example of the configuration of an RF tag according to the embodiment. 1A to 1C illustrate an example of a transistor. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 illustrates an example of a transistor according to one embodiment of the present invention. FIG. 1 is a top view illustrating one embodiment of a display device. FIG. 1 is a cross-sectional view showing one embodiment of a display device. FIG. 1 is a cross-sectional view showing one embodiment of a display device. FIG. FIG. 1 illustrates an example of a semiconductor device according to one embodiment of the present invention. 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A to 1C illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1 shows XRD evaluation results of an oxide semiconductor film according to one embodiment of the present invention. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. Electron diffraction pattern of an oxide semiconductor film. 1 shows the results of TDS analysis of an oxide semiconductor film. FIG. 1 shows changes in crystals caused by electron beam irradiation. 1 shows an example of how an RF tag is used according to an embodiment. 1 is an electronic device according to an embodiment. 13A to 13C show film densities of oxide semiconductor films. 13A to 13C show etching rates of oxide semiconductor films. 13A and 13B show amounts of released gases from oxide semiconductor films. 13A and 13B show hydrogen concentrations in oxide semiconductor films. 1A to 1C show crystal sizes of an oxide semiconductor film. 1A to 1C show crystal sizes of an oxide semiconductor film. 13A and 13B show CPM measurement results of an oxide semiconductor film. 13A and 13B show CPM measurement results of an oxide semiconductor film. 13A and 13B show CPM measurement results of an oxide semiconductor film. FIG. 1 shows a Cs-corrected high-resolution cross-sectional TEM image of an a-like OS. 13A and 13B show hydrogen concentrations in oxide semiconductor films.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be used.

In each figure described in this specification, the size, layer thickness, or area of each component is indicated by the following formula:
Illustrative figures may be exaggerated for clarity and are not necessarily to scale.

In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not limit the numbers.

In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of an angle of -5° or more and 5° or less is also included.
"Substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less. "Substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is referred to as a hexagonal crystal system.

A transistor is a type of semiconductor element and can perform a switching operation such as amplifying a current or voltage and controlling conduction or non-conduction. The transistor in this specification is an IGFET (Insulated Gate Field Effect Transistor).
transistors (TFTs) and thin film transistors (TFTs)
)including.

(Embodiment 1)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films.
The non-single-crystal oxide semiconductor film is a CAAC-OS (C Axis Aligned Cryogenic
The oxide semiconductor film includes a stalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

A single crystal can be formed in some cases by firing at a high temperature, for example, equal to or higher than about 1000° C. Thus, from an industrial viewpoint, it is preferable to use a non-single-crystal oxide semiconductor film, which can be formed at a lower temperature, because a semiconductor device can be manufactured at lower cost.

The number of grain boundaries in an oxide semiconductor film is preferably as small as possible. By reducing the number of grain boundaries, for example, carrier mobility can be increased. By manufacturing a transistor using an oxide semiconductor film with few grain boundaries, for example, a transistor with high field-effect mobility can be realized in some cases. As will be described in detail later, examples of a non-single-crystal oxide semiconductor film with few grain boundaries include an nc-OS film and a CAAC-OS film.

On the other hand, the oxide semiconductor film may have crystals with a spinel structure. When crystals with a spinel structure are mixed in a CAAC-OS film or an nc-OS film, a clear boundary (or grain boundary) may be formed. At the boundary, for example, carrier scattering may increase, and carrier mobility may decrease. In addition, the boundary is likely to become a path for impurities to move and is likely to capture impurities, so there is a concern that the impurity concentration in the oxide semiconductor film may increase.
When a conductive film is formed over an oxide semiconductor film, an element contained in the conductive film, such as a metal, may diffuse into the boundary between the spinel region and another region, so that the oxide semiconductor film preferably does not contain a spinel crystal structure or contains only a small amount of the spinel crystal structure.

Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When the oxide semiconductor contains indium, for example, the carrier mobility (electron mobility) is increased. In addition, the oxide semiconductor preferably contains an element M. The element M is preferably aluminum, gallium, or
The element M may be, for example, yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, the element M may be a combination of a plurality of the above elements. The element M is, for example, an element having a high bond energy with oxygen. For example, the element M is an element having a higher bond energy with oxygen than indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. In addition, the oxide semiconductor preferably contains zinc. The oxide semiconductor may be easily crystallized when it contains zinc. Here, an oxide containing indium, the element M, and zinc is referred to as In-M-Zn oxide.

[Atomic ratio]
The atomic ratio of the In-M-Zn oxide film which is the oxide semiconductor film of one embodiment of the present invention is In:
M:Zn=x:y:z. The preferred ranges of x, y and z will be described with reference to FIGS.

Here, the atomic ratio of each element will be described with reference to Fig. 3. Fig. 3 shows the atomic ratio of elements X, Y, and Z in an XYZ oxide film, where the atomic ratio of elements X, Y, and Z is x:y:z.
3A and 3B show the range of the atomic ratio. The atomic ratio of oxygen is not shown in FIG. 3. Also, FIG. 3 may be called an equilibrium diagram. In FIG. 3A and FIG. 3B, an equilateral triangle with vertices X, Y, and Z, and coordinate R (4:2:1) are shown as an example of coordinates. Here, each vertex represents the elements X, Y, and Z, respectively. The value of each term in the atomic ratio is higher the closer the coordinate is to each vertex, and lower the farther the coordinate is. Also, as shown in FIG. 3A, the value of each term in the atomic ratio is represented by the length of the perpendicular line from the coordinate to the opposite side of the vertex of the triangle. For example, in the case of element X, it is represented by the length of the perpendicular line 21 from the coordinate to the opposite side of vertex X, that is, side YZ. Therefore, the coordinate R shown in FIG. 3 represents that the atomic ratio of element X, element Y, and element Z is the ratio of the lengths of the perpendicular lines 21, 22, and 23, that is, x:y:z=4:2:1. Also, the point where the straight line passing through vertex X and coordinate R intersects with side YZ is defined as γ. In this case, if the ratio of the length of the line segment Yγ to the length of the line segment γZ is Yγ:γZ, then Yγ:γZ=(number of atoms of element Z):(number of atoms of element Y).

Also, as shown in Fig. 3(B), three straight lines are drawn that pass through coordinate R and are parallel to the three sides of the triangle. In this case, x, y, and z can be expressed as shown in Fig. 3(B) using the intersections of the three straight lines and the three sides.

In FIG. 6, the range in which x:y:z in the In-M-Zn oxide film satisfies the following formula is indicated by a dashed line.

x:y:z=(1-α):(1+α):m(-1≦α≦1)

Here, Figure 6 shows the cases where m = 1, 2, 3, 4, and 5.

As described in Non-Patent Document 1, In-M-Zn oxide is InMO ₃ (Zn
It is known that there exists a homologous phase (homologous series) represented by the element _M , GaO, where m is a natural number. Here, consider the case where the element M is Ga as an example. The region shown by the thick straight line in Fig. 6 is a composition that _is known to be capable of forming a single-phase solid solution region when, for example, powders of _In2O3 , _Ga2O3 , and _ZnO are mixed and sintered at 1350°C. The solid solution region is
It is known that the width increases as the value of m increases, that is, as the ratio of zinc increases.

The coordinates shown by square symbols in FIG. 6 indicate the following when, for example, powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and fired at 1350° C., as described in Non-Patent Document 1:
It is known that this composition is likely to have a spinel-type crystal structure mixed in. As shown in Fig _. 6, when the composition is close to _ZnGa2O4 , that is, when x, y, and z have values close to (x, y, z) = (0, 2, 1), a spinel-type crystal structure is likely to be formed or mixed in, as described in Non-Patent Document 1.

In the In-M-Zn oxide film that is the oxide semiconductor film of one embodiment of the present invention, the ratio of indium is preferably increased. In the In-M-Zn oxide film, the s orbitals of metal atoms mainly contribute to carrier conduction, and by increasing the content of indium, more s orbitals overlap, so that the carrier mobility is increased. By manufacturing a transistor using such a film for a channel region, for example, a transistor having high field-effect mobility can be realized. For example, x/y>0.5 is preferable,
More preferably, x/y≧0.75, and even more preferably, x/y≧1.
is preferred.

Therefore, x, y, and z preferably have the atomic ratio in the region 11 shown in FIG. 1, and more preferably have the atomic ratio in the region 12 shown in FIG. 2(A). Here, the region 11 is
The first coordinate K (x:y:z = 8:14:7) and the second coordinate R (x:y:z = 2:4:3
), the third coordinate L (x:y:z=2:5:7), and the fourth coordinate M (x:y:z=51:
Area 11 is within an area connecting, in order, coordinates N (x:y:z = 46:288:833), coordinate O (x:y:z = 0:2:11), coordinate P (x:y:z = 0:0:1), coordinate Q (x:y:z = 1:0:0), and coordinate K. Area 11 includes line segments connecting eight points. Area 11 excludes coordinates P and Q, and includes the other coordinates. Area 12 includes coordinates K (x:y:z = 46:288:833), coordinate O (x:y:z = 0:2:11), coordinate P (x:y:z = 0:0:1), coordinate Q (x:y:z = 1:0:0), and coordinate K.
(x:y:z=8:14:7), the second coordinate R (x:y:z=2:4:3), the third coordinate L (x:y:z=2:5:7), the fourth coordinate S (x:y:z=1:0:1), the fifth coordinate Q (x:y:z=1:0:0), and the first coordinate K are connected by line segments in that order. Note that area 12 includes line segments connecting five points. Area 12 excludes coordinate Q, and includes the other coordinates.

[Structure of oxide semiconductor film]
Next, the structure of the oxide semiconductor film will be described.

First, we will explain the CAAC-OS film.

The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts which are c-axis aligned.

Transmission Electron Microscope (TEM)
A composite analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of the CAAC-OS film can be observed using a TEM (transmission electron microscope). However, even in a high-resolution TEM image, clear boundaries between crystal parts, that is, grain boundaries, cannot be observed. Therefore, the CAAC-OS film is
It can be said that the decrease in electron mobility caused by the grain boundaries is unlikely to occur.

When a high-resolution TEM image of a cross section of a CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be seen that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape that reflects the unevenness of the surface (also referred to as the surface on which the CAAC-OS film is formed) or the top surface of the CAAC-OS film, and is arranged in parallel to the surface on which the CAAC-OS film is formed or the top surface.

On the other hand, when a high-resolution TEM image of a planar surface of a CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be seen that metal atoms are arranged in a triangular or hexagonal shape in the crystal parts, but no regularity is observed in the arrangement of metal atoms between different crystal parts.

Note that when electron diffraction is performed on the CAAC-OS film, spots (bright points) showing orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) is performed on a surface on which the CAAC-OS film is formed or on the top surface thereof using an electron beam with a diameter of 1 nm to 30 nm, spots are observed (see FIG. 7B ).

The high-resolution cross-sectional and planar TEM images show that the crystal parts of the CAAC-OS film have orientation.

Note that most of the crystal parts in the CAAC-OS film are sized to fit within a cube with one side less than 100 nm.
The size may be within a cube of less than 1 nm, less than 5 nm, or less than 3 nm. However, a plurality of crystal parts in the CAAC-OS film may be connected to form one large crystal region. For example, a crystal region of ²⁵⁰⁰ nm2 or more, ⁵ μm2 or more, or ¹⁰⁰⁰ μm2 or more may be observed in a high-resolution planar TEM image.

X-ray diffraction (XRD) of the CAAC-OS film
When the structure was analyzed using the device, for example, a CAAC-OS having InGaZnO ₄ crystals was found.
In an out-of-plane analysis of the film, a peak may appear at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO ₄ crystals, which confirms that the crystals of the CAAC-OS film have c-axis orientation and the c-axis faces in a direction approximately perpendicular to the surface on which the film is formed or the top surface.

On the other hand, in-plane X-ray irradiation is performed on the CAAC-OS film in a direction substantially perpendicular to the c-axis.
In the analysis by the AN method, a peak may appear when 2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of a single crystal oxide semiconductor film of InGaZnO ₄ , when 2θ is fixed at around 56° and analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface, six peaks attributed to a crystal plane equivalent to the (110) plane are observed. In contrast, in the case of a CAAC-OS film, when 2θ is fixed at around 56°, six peaks attributed to a crystal plane equivalent to the (110) plane are observed.
Even when φ is fixed at around 6° and scanned, no clear peak appears.

From the above, it can be seen that in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the film has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which the film is formed or the top surface. Therefore, each layer of metal atoms arranged in layers confirmed by the high-resolution TEM observation of the cross section described above is a plane parallel to the a-b plane of the crystal.

The crystalline parts are formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface on which the CAAC-OS film is formed or the top surface. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the surface on which the CAAC-OS film is formed or the top surface.

Furthermore, the distribution of c-axis oriented crystal parts in the CAAC-OS film does not have to be uniform. For example, when the crystal parts of the CAAC-OS film are formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the region near the top surface may have a higher proportion of c-axis oriented crystal parts than the region near the surface on which the film is formed. Furthermore, in a CAAC-OS film to which an impurity has been added, the region to which the impurity has been added may be altered, and a region with a different proportion of c-axis oriented crystal parts may be formed.

Note that the out-of-plane phase of the CAAC-OS film containing InGaZnO ₄ crystals
In the analysis by the method, in addition to the peak when 2θ is around 31°, a peak may also appear when 2θ is around 36°. The peak when 2θ is around 36° indicates that crystals without c-axis orientation are contained in part of the CAAC-OS film. It is preferable that the CAAC-OS film shows a peak when 2θ is around 31° and does not show a peak when 2θ is around 36°.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon that has stronger bonding strength with oxygen than metal elements constituting the oxide semiconductor film removes oxygen from the oxide semiconductor film, thereby disturbing the atomic arrangement of the oxide semiconductor film and causing a decrease in crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have a large atomic radius (or molecular radius), and therefore, when contained inside the oxide semiconductor film, they disturb the atomic arrangement of the oxide semiconductor film and cause a decrease in crystallinity. Note that the impurities contained in the oxide semiconductor film may become a carrier trap or a carrier generation source.

For example, oxygen vacancies in an oxide semiconductor film may become carrier traps or may capture hydrogen and become a carrier generation source. The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Specifically, the density is less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , further preferably less than 1×10 ¹⁰ /cm ³ .
The oxide semiconductor can have a carrier density of 10 ⁻⁹ /cm ³ or more.

Furthermore, in a transistor using a CAAC-OS film, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small.

Next, we will explain the polycrystalline oxide semiconductor film.

In the polycrystalline oxide semiconductor film, crystal grains can be confirmed in a high-resolution TEM image.
The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, 2 nm to 3 nm in a high-resolution TEM image.
In many cases, the grain size of the polycrystalline oxide semiconductor film is 00 nm or less, 3 nm to 100 nm, or 5 nm to 50 nm. In addition, in a high-resolution TEM image of the polycrystalline oxide semiconductor film, grain boundaries can be confirmed in some cases.

The polycrystalline oxide semiconductor film may have a plurality of crystal grains, and the crystal orientations of the plurality of crystal grains may differ from each _other .
In the analysis by the t-of-plane method, a peak at 2θ of approximately 31°, a peak at 2θ of approximately 36°, or other peaks may appear.

A polycrystalline oxide semiconductor film has high crystallinity and therefore has high electron mobility in some cases. Therefore, a transistor using the polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may segregate at crystal grain boundaries.
The grain boundaries of the polycrystalline oxide semiconductor film become defect states. Since the grain boundaries of the polycrystalline oxide semiconductor film may become carrier traps or carrier generation sources, a transistor using the polycrystalline oxide semiconductor film may have large fluctuations in electrical characteristics and low reliability.

Next, we will explain the microcrystalline oxide semiconductor film.

The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed in a high-resolution TEM image and a region where a clear crystal part cannot be confirmed. The crystal parts contained in the microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is referred to as n
c-OS (nanocrystalline oxide semiconductor)
In the nc-OS film, crystal grain boundaries may not be clearly identified in a high-resolution TEM image, for example.

The nc-OS film has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Furthermore, the nc-OS film has no regularity in crystal orientation between different crystal parts. Therefore, no orientation is observed in the entire film.
Therefore, the nc-OS film may be indistinguishable from an amorphous oxide semiconductor film depending on the analysis method.
When the structure is analyzed using the device, the out-of-plane analysis does not detect a peak near 31°, which indicates a crystal plane (see FIG. 8). When the nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than the crystal part (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the crystal part, a spot is observed. When the nc-OS film is subjected to nanobeam electron diffraction, a region with high brightness that draws a circle (ring-shaped) may be observed. When the nc-OS film is subjected to nanobeam electron diffraction, a plurality of spots may be observed within the ring-shaped region. For example, as shown in FIG. 9A, when the nc-OS film is subjected to nanobeam electron diffraction with a probe diameter of 30 nm, 20 nm, 10 nm, or 1 nm on a thickness of about 50 nm, a region with high brightness that draws a circle (ring-shaped) may be observed. It can also be seen that as the probe diameter is reduced, a ring-shaped region is formed from multiple spots.

For a more detailed structural analysis, the nc-OS film was sliced to a thickness of several nm (about 5 nm), and a transmission electron diffraction pattern was obtained using an electron beam with a probe diameter of 1 nm, resulting in a transmission electron diffraction pattern having spots showing crystallinity, as shown in FIG.

When nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions are sometimes observed.

The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film, and therefore has a lower density of defect states than an amorphous oxide semiconductor film.

In addition, the nc-OS film has no regularity in the crystal orientation between different crystal parts.
The nc-OS film has a higher density of defect states than the CAAC-OS film.
The S film might have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density might have high electron mobility. Therefore, a transistor using the nc-OS film might have high field-effect mobility.

The nc-OS film can be formed at a lower temperature than the CAAC-OS film.
In some cases, films can be formed even if they contain relatively large amounts of impurities.
In some cases, a c-OS film can be formed more easily than a CAAC-OS film.
A semiconductor device including a transistor using an OS film can be manufactured with high productivity in some cases.

In addition, the nc-OS film may have appropriate oxygen permeability. When the nc-OS film has appropriate oxygen permeability, for example, oxygen released from a film containing excess oxygen is likely to diffuse throughout the nc-OS film. Thus, oxygen vacancies may be easily reduced in the nc-OS film.

A semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) is called high-purity intrinsic or substantially high-purity intrinsic. A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a small number of carrier generation sources, and therefore the carrier density can be reduced. Therefore, a transistor using the oxide semiconductor film is unlikely to have electrical characteristics in which the threshold voltage is negative (also referred to as normally-on). In addition, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a small number of carrier traps. Therefore, a transistor using the oxide semiconductor film has small fluctuations in its electrical characteristics and is highly reliable. Note that charges trapped in carrier traps in the oxide semiconductor film take a long time to be released and may behave as if they are fixed charges. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

Next, we will explain the amorphous oxide semiconductor film.

An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and which does not have a crystal part, such as an oxide semiconductor film having an amorphous state like quartz.

In the amorphous oxide semiconductor film, no crystal parts can be seen in a high-resolution TEM image.

When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-
In the analysis by the plane method, no peak indicating a crystal plane is detected. In addition, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. In addition, when nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spots are observed, but a halo pattern is observed.

The amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration.
In addition, the amorphous oxide semiconductor film has a high density of defect states.

An oxide semiconductor film having a high impurity concentration and a high density of defect states has many carrier traps and carrier generation sources.

Therefore, the amorphous oxide semiconductor film may have a higher carrier density than an nc-OS film. Therefore, a transistor using an amorphous oxide semiconductor film is likely to have normally-on electrical characteristics. Thus, the amorphous oxide semiconductor film may be preferably used as a transistor required to have normally-on electrical characteristics. The amorphous oxide semiconductor film may have a high density of defect states and thus may have a large number of carrier traps. Therefore, a transistor using an amorphous oxide semiconductor film may have a higher carrier density than a transistor using a CAAC-OS film or an nc-OS film.
This results in a transistor with large fluctuations in electrical characteristics and low reliability.

Next, we will explain the single crystal oxide semiconductor film.

A single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, the carrier density can be reduced. Therefore, a transistor using a single crystal oxide semiconductor film rarely has normally-on electrical characteristics. Furthermore, since a single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, carrier traps may be reduced. Therefore, a transistor using a single crystal oxide semiconductor film has little change in electrical characteristics and is highly reliable.

Note that the oxide semiconductor film has a high density when the number of defects is small.
Higher crystallinity increases the density. Furthermore, an oxide semiconductor film has a higher density when the concentration of impurities such as hydrogen is low. A single-crystal oxide semiconductor film has a higher density than a CAAC-OS film. Furthermore, a CAAC-OS film has a higher density than a microcrystalline oxide semiconductor film. Furthermore, a polycrystalline oxide semiconductor film has a higher density than a microcrystalline oxide semiconductor film. Furthermore, a microcrystalline oxide semiconductor film has a higher density than an amorphous oxide semiconductor film.

Note that the oxide semiconductor film may have a structure that shows physical properties between an nc-OS film and an amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly called an amorphous-like oxide semiconductor (AIS).
The resulting film is called an a-like OS film.

In the a-like OS film, voids may be observed in a high-resolution TEM image. In addition, the high-resolution TEM image includes a region where a crystalline part can be clearly observed and a region where a crystalline part cannot be observed. In the a-like OS film, crystallization may occur due to a small amount of electron irradiation at the level observed by TEM, and growth of the crystalline part may be observed. On the other hand, in the case of a good quality nc-OS film, crystallization due to a small amount of electron irradiation at the level observed by TEM is hardly observed.

Note that the size of the crystal parts of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, an InGaZnO ₄ crystal has a layered structure, with two Ga-Zn-O layers between In-O layers. The unit lattice of an InGaZnO ₄ crystal has a structure in which a total of nine layers, including three In-O layers and six Ga-Zn-O layers, are layered in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is 0.29n from crystal structure analysis.
Therefore, by focusing on the lattice fringes in the high-resolution TEM image, it is possible to determine that in the area where the spacing between the lattice fringes is 0.28 nm or more and 0.30 nm or less, each lattice fringe is In.
This was considered to correspond to the a-b plane of a GaZnO ₄ crystal. The maximum length in the region where the lattice fringes were observed was taken as the size of the crystal part of the a-like OS film and the nc-OS film. Note that the size of the crystal part is selectively evaluated when it is 0.8 nm or more.

In addition, due to the voids, the a-like OS has a structure with a lower density than the nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition.

There may be cases where single crystals of the same composition do not exist. In such cases, the density corresponding to a single crystal of the desired composition can be estimated by combining single crystals of different compositions in any ratio. The density corresponding to a single crystal of the desired composition can be estimated by using a weighted average of the ratio of the single crystals of different compositions to be combined. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

[Nanobeam electron diffraction]
Next, nanobeam electron diffraction will be described.

When the oxide semiconductor film has a plurality of structures, the structures can be analyzed by nanobeam electron diffraction in some cases.

FIG. 7C shows an electron gun chamber 610, an optical system 612 below the electron gun chamber 610, and an optical system 613 below the electron gun chamber 610.
2, a sample chamber 614 below the sample chamber 614, an optical system 616 below the sample chamber 614, an observation chamber 620 below the optical system 616, a camera 618 installed in the observation chamber 620, and a film chamber 622 below the observation chamber 620. The camera 618 is installed facing the inside of the observation chamber 620. The film chamber 622 does not necessarily have to be provided.

7D shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 7C. In the transmission electron diffraction measurement device, electrons emitted from an electron gun installed in an electron gun chamber 610 are irradiated via an optical system 612 onto a material 628 placed in a sample chamber 614.
The electrons that have passed through are incident on a fluorescent screen 632 installed inside an observation chamber 620 via an optical system 616. On the fluorescent screen 632, a pattern appears according to the intensity of the incident electrons, making it possible to measure the transmission electron diffraction pattern.

The camera 618 is installed facing the fluorescent screen 632, and can photograph the pattern appearing on the fluorescent screen 632. The angle between the center of the lens of the camera 618 and the center of the fluorescent screen 632 and the upper surface of the fluorescent screen 632 is, for example, 15° to 80°, 30° to 75°, or 45° to 70°. The smaller the angle, the more distortion of the transmission electron diffraction pattern photographed by the camera 618. However, if the angle is known in advance, it is also possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 618 may be installed in the film chamber 622 in some cases. For example, the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with little distortion can be photographed from the back side of the fluorescent screen 632.

A holder for fixing a substance 628 as a sample is placed in the sample chamber 614 .
The holder has a structure that allows electrons passing through the material 628 to pass through. The holder may have a function of moving the material 628 in the X-axis, Y-axis, Z-axis, etc. The moving function of the holder may have a precision for moving within a range of, for example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less, 50 nm or more and 500 nm or less, 100 nm or more and 1 μm or less, etc. These ranges may be set to an optimal range depending on the structure of the material 628.

Next, a method for measuring the transmission electron diffraction pattern of a substance using the above-mentioned transmission electron diffraction measurement device will be described.

For example, by changing (scanning) the irradiation position of the electron 624, which is a nanobeam, on the material as shown in Fig. 7D, it is possible to confirm how the structure of the material changes. In this case, if the material 628 is a CAAC-OS film, a diffraction pattern such as that shown in Fig. 7B is observed. Alternatively, if the material 628 is an nc-OS film, a diffraction pattern such as that shown in Fig. 7A, for example, a diffraction pattern having a plurality of bright spots arranged in a circular pattern (a ring-shaped diffraction pattern accompanied by bright spots) is observed. The diffraction pattern shown in Fig. 7A has bright spots that are not arranged symmetrically (not symmetrical).

7B, in the diffraction pattern of the CAAC-OS film, for example, spots located at the vertices of a hexagon are observed. By scanning the irradiation position of the CAAC-OS film, it is found that the orientation of the hexagon is not uniform but rotates little by little. The angle of rotation has a certain range.

Alternatively, in the case of the diffraction pattern of the CAAC-OS film, the irradiation position is scanned to obtain
It can be seen that it rotates little by little around the c-axis. This can be said to be the rotation of the plane formed by the a-axis and b-axis, for example.

The substance 628 may have a region where a diffraction pattern similar to that of a CAAC-OS film is observed (hereinafter, referred to as a region having a CAAC structure) and a region where a diffraction pattern similar to that of an nc-OS film is observed (hereinafter, referred to as a region having an nc structure). Here, the ratio of the region where the diffraction pattern of the CAAC-OS film is observed in a certain range is referred to as the CAAC ratio (
Similarly, the ratio of a region where a diffraction pattern similar to that of the nc-OS film is observed can be expressed as an nc ratio (also referred to as an nc ratio).

A method for evaluating the CAAC ratio in a CAAC-OS film will be described below. Measurement points are randomly selected, a transmission electron diffraction pattern is obtained, and the ratio of the number of measurement points at which the diffraction pattern of the CAAC-OS film is observed to the number of all measurement points is calculated. Here, the number of measurement points is preferably 50 or more, and more preferably 100 or more.

As a method for randomly selecting measurement points, for example, the irradiation position may be scanned linearly and a diffraction pattern may be acquired at regular intervals.
This is preferable because it is possible to confirm the boundaries between the region having the structure and the other regions.
Similarly, the conversion rate can be calculated by randomly selecting measurement points and obtaining a transmission electron diffraction pattern.

By using such a measurement method, it may be possible to perform structural analysis of an oxide semiconductor film having a plurality of structures.

In the oxide semiconductor film of one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is 80%, for example.
It is preferable that the ratio is 90% or more and 100% or less, it is preferable that the ratio is 95% or more and 100% or less, it is preferable that the ratio is 98% or more and 100% or less, it is preferable that the ratio is 9
The ratio is preferably 9% or more and 100% or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film with fewer clear grain boundaries can be realized. By reducing the number of clear grain boundaries, for example, the carrier mobility of the oxide semiconductor film can be increased.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

The nc-OS film can be formed at a relatively low deposition temperature in some cases as compared with the CAAC-OS film. For example, the nc-OS film can be formed without heating the substrate in some cases. Therefore, a semiconductor device including a transistor using the nc-OS film can be manufactured with high productivity in some cases.

In addition, since the nc-OS film has a moderate oxygen permeability, oxygen can be easily diffused throughout the film, and oxygen vacancies can be easily reduced. Thus, an oxide semiconductor film with a low defect density can be realized. Thus, the characteristics of a semiconductor device including a transistor using the nc-OS film can be improved. Furthermore, reliability can be improved.

Here, the nc-OS film and the CAAC-OS film both have an atomic arrangement in which layers are stacked on top of each other. Such an atomic arrangement in which layers are stacked on top of each other can be observed using a TEM, for example.

Here, the nc-OS film and the CAAC film are subjected to spherical aberration correction (Spherical
Transmission electron microscopy (TEM) using the Aberration Corrector function
An image obtained by Transmission Electron Microscopy (TEM image) is observed. A composite analysis image of a bright-field image and a diffraction pattern obtained by TEM observation is called a high-resolution TEM image. A high-resolution TEM image using a spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image.
The images were obtained using, for example, an atomic resolution analytical electron microscope JEM-ARM20 manufactured by JEOL Ltd.
This can be done by, for example, 0F.

In the CAAC-OS and nc-OS, the size and orientation of the crystals are investigated by analyzing the Cs-corrected high-resolution cross-sectional TEM images in more detail. Hereinafter, the crystal parts of the nc-OS may be referred to as pellets. The size and orientation of the crystals are investigated by extracting pellets from an area of, for example, 20 nm square or more in the cross-sectional TEM images.

17A is a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS, and FIG 17B is a Cs-corrected high-resolution cross-sectional TEM image of nc-OS. Note that the left and right images were taken at the same location, and auxiliary lines indicating pellets are drawn in the right image.

18A is a cross-sectional TEM image of a CAAC-OS film formed by a DC sputtering method, and FIG 18B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a part of the CAAC-OS film.
In Fig. 18(B), the number of pellets is counted, and their sizes and orientations are plotted as a frequency distribution (see Fig. 22(A)). Here, the arrows in Fig. 18(A) indicate the direction perpendicular to the sample surface. The direction of the white lines in Fig. 18(B) indicates the orientation of the pellets, and the length of the white lines indicates the size of the pellets.

19A is a cross-sectional TEM image of a CAAC-OS film formed by an RF sputtering method, and FIG 19B is a Cs-corrected high-resolution cross-sectional TEM image of a part of the CAAC-OS film formed by an RF sputtering method.
In FIG. 19(B), the number of pellets is counted, and their sizes and orientations are plotted as a frequency distribution (see FIG. 22(B)).

FIG. 20A is a cross-sectional TEM image of an nc-OS film formed by a DC sputtering method.
FIG. 20B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a portion of the sample.
At 0(B), the number of pellets is counted and a frequency distribution is created for their sizes and orientations (see FIG. 22(C)).

FIG. 21A is a cross-sectional TEM image of an nc-OS film formed by an RF sputtering method.
FIG. 21B is an enlarged Cs-corrected high-resolution cross-sectional TEM image of a portion of the sample.
In FIG. 22(B), the number of pellets is counted and a frequency distribution is created for their sizes and orientations (see FIG. 22(D)).

The table below summarizes the results of Fig. 22. Here, the orientation of the pellet indicates the absolute value of the angle with respect to the sample surface.

The nc-OS preferably has pellets with a size of, for example, 0.5 nm to 3 nm, more preferably 1 nm to 3 nm.
It can be seen that the orientation of the pellets in the RF sputtering method is more oriented in a direction perpendicular to the sample surface than in the DC sputtering method. Here, the percentage of the nc-OS pellets whose orientation is 0° or more and less than 30° with respect to the sample surface is preferably, for example, 0% or more and 70% or less, the percentage of the nc-OS pellets whose orientation is 30° or more and less than 60° with respect to the sample surface is preferably, for example, 10% or more and 60% or less, and the percentage of the nc-OS pellets whose orientation is 60° or more and less than 90° with respect to the sample surface is preferably, for example, 0% or more and 60% or less. The nc-OS is a CAAC-OS.
It can be seen that the orientation of the pellets is random compared to that of the

An oxide semiconductor film having such pellets can be explained by, for example, the following film formation model.

[Film formation model]
A film formation model of the nc-OS will be described below.

FIG. 24 is a schematic diagram of the inside of a film formation chamber, illustrating how an nc-OS film is formed by sputtering.

The target 5130 is bonded onto the backing plate.
A plurality of magnets are disposed under the backing plate, which generates a magnetic field above the target 5130. A sputtering method that uses the magnetic field of the magnets to increase the film formation rate is called magnetron sputtering.

The target 5130 has a polycrystalline structure, and each crystal grain includes a cleavage plane.
The cleavage plane will be described in detail later.

The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d (
The target-substrate distance (also called the T-S distance) is set to 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less.
oxygen, argon, or a mixed gas containing 50% or more by volume of oxygen) and
The pressure is controlled to be 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage of a certain level or more to the target 5130, discharge begins and plasma is confirmed. Note that a high-density plasma region is formed by the magnetic field above the target 5130. In the high-density plasma region, the deposition gas is ionized to generate ions 5101. The ions 5101 are, for example, positive ions of oxygen (O ⁺ ) or positive ions of argon (Ar
⁺ ).

The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually collide with the target 5130. At this time, pellets 5100a and 5100b, which are flat or pellet-shaped sputtered particles, are peeled off from the cleavage surface and knocked out. Note that the pellets 5100a and 5100b may be distorted in structure due to the impact of the collision of the ions 5101.

The pellet 5100a is a flat or pellet-shaped sputter particle having a triangular, for example, equilateral triangular, plane. The pellet 5100b is a flat or pellet-shaped sputter particle having a hexagonal, for example, equilateral hexagonal, plane. The flat or pellet-shaped sputter particles such as the pellets 5100a and 5100b are collectively called pellets. The shape of the pellet plane is not limited to a triangle or hexagon, and may be, for example, a shape having two triangles.
For example, two equilateral triangles may join together to form a quadrilateral.

The thickness of the pellet is determined depending on the type of deposition gas, etc. It is preferable that the pellet has a uniform thickness. Also, it is preferable that the sputtered particles are in the form of a pellet with no thickness rather than in the form of a thick cube.

The pellets may pick up an electric charge as they pass through the plasma, resulting in negative or positive charging on the sides. The pellets may have oxygen atoms on their sides that may become negatively charged.

As shown in Fig. 24, for example, a pellet flies like a kite through the plasma, fluttering up to above the substrate 5120. Since the pellet is electrically charged, a repulsive force is generated when it approaches an area where other pellets are already deposited. Here, a magnetic field is generated on the upper surface of the substrate 5120 in a direction parallel to the upper surface of the substrate 5120. Also, since a potential difference is applied between the substrate 5120 and the target 5130, a magnetic field is generated from the substrate 5120 to the target 5130.
130. Therefore, the pellet receives a force (Lorentz force) on the upper surface of the substrate 5120 due to the action of the magnetic field and the current. In order to increase the force applied to the pellet, it is advisable to provide a region on the upper surface of the substrate 5120 where the magnetic field parallel to the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more. Alternatively, it is advisable to provide a region on the upper surface of the substrate 5120 where the magnetic field parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and more preferably 5 times or more of the magnetic field perpendicular to the upper surface of the substrate 5120.

According to the above model, it is considered that the pellets are deposited on the substrate 5120.
Therefore, unlike epitaxial growth, it is possible to form an nc-OS film even when the surface to be formed does not have a crystalline structure. For example, even if the top surface (surface to be formed) of the substrate 5120 has an amorphous structure, it is possible to form an nc-OS film.

Since the nc-OS film is formed by such a model, it is preferable that the sputtered particles have a pellet shape with no thickness.
The surface of the sputtered particles directed onto the substrate 5120 may not be uniform, making it impossible to achieve a uniform thickness or crystal orientation.

Furthermore, when the substrate 5120 is heated, resistance such as friction between the pellet and the substrate 5120 is smaller. As a result, the pellet glides over the upper surface of the substrate 5120. The pellet moves with its flat surface facing the substrate 5120. When the pellet reaches the side surface of another pellet 5100 that has already been deposited, the side surfaces are bonded to each other to obtain a CAAC-OS film.

When the substrate 5120 is not heated, resistance such as friction between the pellets and the substrate 5120 is large. As a result, it is difficult for the pellets to glide over the upper surface of the substrate 5120, and the pellets fall and accumulate irregularly to obtain an nc-OS.

CAAC-OS is formed by heating the substrate 5120, whereas nc-OS is formed by heating the substrate 51
It is possible to form a film without performing the heating step 20.

Also, as shown in FIG. 25, the atmosphere in the chamber is preferably kept at room temperature or higher by 500° C.
The chamber may be heated to 200° C. or less, more preferably 200° C. to 400° C. Lamps 5140 such as halogen lamps may be used to heat the atmosphere. Heating the atmosphere may, for example, heat pellets flying in the chamber, which may reduce defects. It may also increase the pellet size. Heating the atmosphere may also, for example, make it easier for moisture in the chamber to evaporate, thereby further increasing the degree of vacuum.

[Cleavage plane]
The cleavage plane of the target described in the film formation model of nc-OS will be described below.

First, the cleavage plane of the target will be described with reference to FIG.
10A shows the structure of a crystal of _InGaZnO4 when the c-axis is facing upward and _the crystal is observed from a direction parallel to the b-axis.
The structure of an InGaZnO ₄ crystal is shown when observed from a direction parallel to the axis.

The energy required for cleavage at each crystal plane of the InGaZnO ₄ crystal is calculated by first-principles calculation. The calculation uses a pseudopotential and a density functional program (CASTEP) using a plane wave basis. The pseudopotential is an ultra-soft type pseudopotential. The functional is GGA PBE. The cutoff energy is 400 eV.

The energy of the initial structure is derived after optimization of the structure including the cell size, while the energy of the structure after cleavage on each plane is derived after optimization of the atomic arrangement with the cell size fixed.

Based on the InGaZnO ₄ crystal structure shown in FIG. 10, a structure is fabricated by cleaving at any of the first, second, third, and fourth planes, and a structural optimization calculation is performed with the cell size fixed. Here, the first plane is the crystal plane between the Ga-Zn-O layer and the In-O layer, (
The second plane is a crystal plane between the Ga—Zn—O layers, and is parallel to the (001) plane (or the a-b plane) (see FIG. 10A).
The first plane is a crystal plane parallel to the (110) plane (see FIG. 10A). The second plane is a crystal plane parallel to the (110) plane (see FIG. 10B). The fourth plane is a crystal plane parallel to the (100) plane (or the bc plane) (see FIG. 10B).

Under the above conditions, the energy of the structure after cleavage is calculated on each plane. Next, the difference between the energy of the structure after cleavage and the energy of the structure in the initial state is divided by the area of the cleavage plane to calculate the cleavage energy, which is a measure of the ease of cleavage on each plane. Note that the energy of the structure is an energy that takes into account the kinetic energy of electrons and interactions between atoms, atoms and electrons, and electrons, for the atoms and electrons contained in the structure.

As a result of calculations, the cleavage energy of the first plane was found to be 2.60 J/m ² , the cleavage energy of the second plane was 0.68 J/m ² , the cleavage energy of the third plane was 2.18 J/m ² , and the cleavage energy of the fourth plane was 2.12 J/m ² (see table below).

This calculation shows that the cleavage energy at the second plane is the lowest in the crystal structure of InGaZnO ₄ shown in Figure 10. In other words, it is found that the plane (cleavage plane) that is easiest to cleave is between the Ga-Zn-O layer and the Ga-Zn-O layer. Therefore, in this specification, when the term "cleavage plane" is used, it refers to the second plane, which is the plane that is easiest to cleave.

Since the InGaZnO ₄ crystal shown in FIG. 10A has a cleavage plane on the second plane between the Ga-Zn-O layer and the Ga-Zn-O layer, it can be separated on a plane equivalent to the two second planes. Therefore, when ions or the like are bombarded against a target, it is considered that a wafer-shaped unit (we call this a pellet) cleaved on the plane with the lowest cleavage energy will fly out as the smallest unit. In that case, the InGaZnO ₄ pellet will have three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

In addition, since the cleavage energies of the third plane (a crystal plane parallel to the (110) plane) and the fourth plane (a crystal plane parallel to the (100) plane (or the bc plane)) are lower than those of the first plane (a crystal plane between the Ga-Zn-O layer and the In-O layer, and parallel to the (001) plane (or the ab plane)), it is suggested that the planar shape of the pellet is often triangular or hexagonal.

[Film density]
Next, the density of the In-M-Zn oxide film was evaluated.
= 1:1:1 polycrystalline In-Ga-Zn oxide was used, and nc-
The pressure was 0.4 Pa, the deposition temperature was room temperature, the power source was 100 W, and argon and oxygen were used as deposition gases, with the flow rates of argon at 98 sccm and oxygen at 2
The density of the obtained In-Ga-Zn oxide was 6.1 g/cm ^3. According to Non-Patent Document 2, the density of single crystal InGaZnO ₄ is 6.357 g/cm ³
In addition, as described in the JCPDS card, No. 00-038-1097, it is known that the density of single crystal In ₂ Ga ₂ ZnO ₇ is 6.494 g/cm ^3. Therefore, it is found that the obtained nc-OS film is an excellent film having a high density.

The density of the In-M-Zn oxide film, which is the oxide semiconductor film of one embodiment of the present invention, is, for example, preferably 85% or more, more preferably 90% or more, and further preferably 95% or more, of the density of a single crystal having approximately the same atomic ratio.

In the case where the element M is gallium, the density of the oxide semiconductor film of one embodiment of the present invention is
For example, 5.7 g/cm ³ or more and 6.49 g/cm ³ or less are preferable, 5.75 g/cm ³ or more and 6.49 g/cm ³ or less are preferable, 5.8 g/cm ³ or more and 6.33 g/cm ³ or less are more preferable, and 5.85 g/cm ³ or more and 6.33 g/cm ³ or less are even more preferable.

Here, "approximately the same atomic ratio" means that the difference between the atomic ratios is within 10%, for example.

Here, for example, the density of the single crystal is determined by the ratio of the number of atoms of two or more In-M-Zn
It may be estimated from the density of the oxide film. Here, the density of a single crystal having an atomic ratio of In:M:Zn=1:1:1 is defined as _D1 , and the density of a single crystal having an atomic ratio of In:M:Zn=2:2:1 is defined as _D2 .
The density of the Zn oxide film is expected to take a value between _D1 and _D2 . Therefore, for example, the average value of _D1 and _D2 may be calculated and referred to as the density of the single crystal, or either one of _D1 and _D2 , for example, the value closer to the atomic ratio, may be referred to. When calculating the average value using _D1 and _D2 , for example, 0.6× _D1 +0.4× _D2 may be used.
The density of a single crystal having n=A:B:C _{is Dα} , and the density of a single crystal having an atomic ratio of In:M:Zn=D:E:F is _Dβ . The density of a single crystal having an atomic ratio of In:M:Zn=X:Y:Z may be calculated, for example, as follows.

First, α is set so that (αA+βD):(αB+βE):(αC+βF)=X:Y:Z.
Next, the density of the single crystal _is calculated by using the calculated α and β.
+{β/(α+β)} _Dβ .

Next, we will explain an example of a method for producing an nc-OS film.

Common techniques for forming an oxide semiconductor film include, for example, a sputtering method, a chemical vapor deposition (CVD) method (including a metal-organic chemical vapor deposition (MOCVD) method, an atomic layer deposition (ALD) method, or a plasma enhanced chemical vapor deposition (PECVD) method), a vacuum evaporation method, or a pulsed laser deposition (PLD) method.

The nc-OS film is preferably formed by a sputtering method, and an In-M-Zn oxide can be used as a target for the sputtering method.

The target preferably contains polycrystalline In-M-Zn oxide. For example, when a target containing polycrystalline In-M-Zn oxide is used, the target has cleavage properties and may easily form an nc-OS film, which is more preferable.

Although it may be possible to prepare In-M-Zn oxide using a mixture of indium oxide, an oxide having element M, and zinc oxide as a target, it is preferable to use a target having polycrystalline In-M-Zn oxide.

The nc-OS film may be preferably formed at room temperature in some cases. For example, the nc-OS film may be preferably formed without heating the substrate in some cases. For example, the atmosphere in the chamber may be preferably heated to a temperature of from room temperature to 500° C., more preferably from 200° C. to 400° C.

[Atomic ratio]
Here, as the oxide semiconductor film of one embodiment of the present invention, for example, an In-M-Zn oxide film is preferably used.
Let n:M:Zn = x:y:z.

In the In-M-Zn oxide film which is the oxide semiconductor film of one embodiment of the present invention, for example, the proportion of indium is preferably increased.

The oxide semiconductor film preferably has fewer grain boundaries. Examples of non-single-crystal oxide semiconductor films with fewer grain boundaries include an nc-OS film and a CAAC-OS film. The oxide semiconductor film may include both an nc-OS film and a CAAC-OS film.

In addition, when nanobeam electron diffraction was performed on the oxide semiconductor film of one embodiment of the present invention,
The oxide semiconductor film according to one embodiment of the present invention may have a region where a diffraction pattern of the nc-OS film is observed and a region where a diffraction pattern of the CAAC-OS film is observed (CAAC structure).

The oxide semiconductor film of one embodiment of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, more preferably 50% or more, and more preferably 80% or more. In the oxide semiconductor film of one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, more preferably 90% or more and 100% or less, and more preferably 90% or more and ...
It is preferably 5% or more and 100% or less, more preferably 98% or more and 100% or less, and even more preferably 99% or more and 100% or less.

The oxide semiconductor film according to one embodiment of the present invention may be a stack of a plurality of films. The plurality of films may have different nc ratios and CAAC ratios. At least one of the plurality of stacked films preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, more preferably 50% or more, and more preferably 80% or more. The sum of the nc ratio and the CAAC ratio of at least one of the plurality of stacked films is preferably 80% or more, more preferably 90% or more and 100% or less, and even more preferably 95% or more and 100% or less.
It is preferable that the ratio is 98% or more and 100% or less, and it is preferable that the ratio is 99.00% or less.
It is more preferable that the ratio is 100% or more and 100% or less.

As shown in FIG. 6, In ₂ O ₃ , Ga ₂ O ₃ , and ZnO powders were mixed and 1350
Non-Patent Document 1 describes that when sintering is performed at 0.degree. C., the solid solubility region is widened by increasing the ratio of zinc. Here, by setting the atomic ratio of In-Ga-Zn oxide within a range in which the solid solubility region can be achieved, the CAAC ratio of the oxide semiconductor film of one embodiment of the present invention may be further increased. Thus, by reducing the ratio of zinc, the n-c ratio of the oxide semiconductor film of one embodiment of the present invention may be further increased. The atomic ratio of indium, element M, and zinc contained in the oxide semiconductor film is indium:element M:zinc=x:y:z. For example, the n-c ratio may be further increased by increasing the ratio of x+y to z, that is, (x+y)/z. Specifically, for example, (x+y)>z is preferable, and (x+
It is preferable that (x+y)≧1.5z, and it is preferable that (x+y)≧2z.

In addition, when crystals having a spinel structure are mixed with a CAAC-OS film or an nc-OS film,
A clear grain boundary or boundary portion may be formed, so it is preferable to move away from the atomic ratio that is more likely to form a spinel structure crystal.

Therefore, the In-M-Zn oxide film, which is the oxide semiconductor film of one embodiment of the present invention,
The atomic ratios x, y, and z of element M and zinc preferably have the atomic ratios in region 13 shown in FIG. 4A, and more preferably have the atomic ratios in region 14 shown in FIG. 4B. Here, region 13 is defined by first coordinates K (x:y:z=8:14:7) and second coordinates R
(x:y:z=2:4:3), the third coordinate V (x:y:z=1:2:3), the fourth coordinate S (x:y:z=1:0:1), the fifth coordinate T (x:y:z=8:0:1), and the sixth coordinate
The area 13 is within a region in which the coordinate U (x:y:z=6:2:1) of the first coordinate K and the first coordinate K are connected in order by line segments. The area 13 includes line segments connecting six points. The area 13 also includes all coordinates. The area 14 is within a region in which the first coordinate K (x:y:z=8:14:7), the second coordinate R (x:y:z=2:4:3), the third coordinate V (x:y:z=1:2:3), the fourth coordinate W (x:y:z=7:1:8), the fifth coordinate X (x:y:z=7:1:1), the sixth coordinate U (x:y:z=6:2:1), and the first coordinate K are connected in order by line segments. The area 14 includes line segments connecting six points. The area 14 also includes all coordinates.

In addition, when the oxide semiconductor film is formed by a sputtering method, the atomic ratio of the obtained film is
The atomic ratio of the target may deviate from that of the target. In particular, the ratio of zinc in the resulting film may be smaller than that of the target. Specifically, the ratio of zinc in the resulting film may be, for example, 40 atomic % or more and 90 atomic % or less of the ratio of zinc in the target.

Here, when forming a film of In--Ga--Zn oxide by a sputtering method, the relationship between the atomic ratio of the target used and the atomic ratio of the resulting film was examined.

The deposition conditions were argon and oxygen as deposition gases, and the oxygen flow ratio was 33%. Here, the oxygen flow ratio is an amount expressed as oxygen flow rate ÷ (oxygen flow rate + argon flow rate) × 100 [%]. The pressure was in the range of 0.4 Pa to 0.7 Pa, the substrate temperature was 200° C. to 300° C., and the power source was 0.5 kW (DC).

FIG. 23 shows the relationship between the ratio of the atomic ratio when focusing on two elements of the target and the residual rate of zinc. The numbers in the figure represent the atomic ratio of In:Ga:Zn of the target. Here, the residual rate of zinc will be explained. The value of the zinc term in the atomic ratio of the obtained film is divided by the sum of the values of the indium, gallium and zinc terms of the film, and the value is Zn(Film). In addition, the value of the zinc term in the atomic ratio of the target is divided by the sum of the values of the indium, gallium and zinc terms of the target, and the value is Zn(Target). Here, the residual rate of zinc is defined as a value represented by A=Zn(Film)÷Zn(Target)×100[%].

The atomic ratio of indium, gallium and zinc in the In-Ga-Zn oxide target used is represented as a:b:c.

FIG. 23A shows the ratio of zinc to gallium in the target (c/b) on the horizontal axis, and FIG.
3(B) shows the ratio of gallium to indium atoms in the target on the horizontal axis (b/a
23C shows the ratio of zinc to indium in the target (c/a) on the horizontal axis, and the zinc residual rate A on the vertical axis.

Here, from FIG. 23, it can be seen that the zinc residual rate of the film obtained by the sputtering method is approximately 5
It can be seen that the ratio is 0% or more and 90% or less. In addition, it can be said that indium and gallium do not change significantly from the atomic ratio of the target compared to zinc. In addition, when the ratio value (c/b) of zinc to gallium in the target is, for example, 1, the residual rate A of zinc is about 66%,
In the case of 2, it is about 74%, and in the case of 3, it is about 83%.

23A also shows that there is a good correlation between the ratio of zinc to gallium in the target (c/b) and the zinc residual rate. That is, the lower the zinc relative to gallium, the lower the residual rate.

In view of the above, in order to obtain the oxide semiconductor film in the region 13 shown in FIG. 4A by a sputtering method, the ratio of zinc in the target film is preferably 1.7 times or more, more preferably 1.5 times or more, relative to the ratio of zinc in the target film. Thus, the atomic ratio of indium, gallium, and zinc in the target is preferably the same as that of the region 15 shown in FIG. 5. Here, the region 15 is defined by a first coordinate K (a:b:c=8:14:7) and a second coordinate R (a
:b:c=2:4:3), a third coordinate Y (a:b:c=1:2:5.1), a fourth coordinate Z (a:b:c=1:0:1.7), and a fifth coordinate T (a:b:c=8:0:1),
The area 15 is formed by connecting the sixth coordinate U (a:b:c=6:2:1) and the first coordinate K in order with line segments. The area 15 includes the line segments connecting the six points. The area 15 includes all the coordinates.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 3)
In this embodiment, an example of a transistor including an oxide semiconductor film, which is one embodiment of the present invention, will be described.

[Transistor Example 1]
An example of a transistor including an oxide semiconductor film will be described with reference to FIGS.

FIG. 12A is a top view of the transistor 100. FIG.
12A shows a cross section taken along dashed line X-X' in FIG. 12B, and a cross section taken along dashed line Y-Y' in FIG. 12C. The transistor 100 shown in FIG. 12A includes a substrate 50, an insulating film 51 in contact with an upper surface of the substrate 50, an insulating film 114 in contact with an upper surface of the insulating film 51, a semiconductor layer 101 in contact with an upper surface of the insulating film 114, conductive layers 104a and 104b, a gate insulating film 102 provided on the semiconductor layer 101, and a gate electrode 103 overlapping with the semiconductor layer 101 with the gate insulating film 102 interposed therebetween.
In addition, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100. The transistor 100 may include a conductive layer 105. An insulating film does not necessarily have to be provided between the substrate 50 and the insulating film 114.

The semiconductor layer 101 may be formed as a single layer, or is more preferably formed as a stacked structure of a first layer, a second layer, and a third layer. The second layer is provided in contact with the first layer, and the third layer is provided in contact with the second layer. Here, in the transistor of one embodiment of the present invention, the first layer and the third layer have a region through which current does not easily flow as compared with the second layer. Thus, the first layer and the third layer may be referred to as an insulator layer. Thus, as in the example shown in FIG. 12, the semiconductor layer 101
It is preferable that the semiconductor layer 101b is formed of a laminated structure of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c. Also, the semiconductor layer 101b may have a structure that does not include any one of the insulator layer 101a and the insulator layer 101c. In the example shown in FIG.
a. The conductive layers 104a and 104b are in contact with the upper surface of the semiconductor layer 101b and are separated from each other in a region where they overlap with the semiconductor layer 101b. The insulator layer 101c is in contact with the upper surface of the semiconductor layer 101b. The gate insulating film 102 is in contact with the upper surface of the insulator layer 101c. The gate electrode 103 overlaps with the semiconductor layer 101b via the gate insulating film 102 and the insulator layer 101c.

In addition, an insulating film 112 and an insulating film 113 are provided to cover the transistor 100 .
The insulating films 112 and 113 will be described in detail in the embodiment described later.

The conductive layer 104a and the conductive layer 104b function as a source electrode or a drain electrode. A voltage lower or higher than that of the source electrode may be applied to the conductive layer 105 to shift the threshold voltage of the transistor in a positive or negative direction. By shifting the threshold voltage of the transistor in a positive direction, a normally-off transistor in which the transistor is in a non-conducting state (off state) even when the gate voltage is 0 V may be realized. Note that the voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to the conductive layer 105 is made variable, a circuit for controlling the voltage may be connected to the conductive layer 105. The conductive layer 105 may be connected to the gate electrode 103.

The upper surface of the insulating film 114 is polished by CMP (Chemical Mechanical Polishing).
It is preferable that the surface is planarized by a planarization process using a planarization method such as a fin-hanging method.

The insulating film 114 preferably contains an oxide. In particular, it preferably contains an oxide material from which some oxygen is released by heating. It is preferable to use an oxide containing more oxygen than the stoichiometric composition. An oxide film containing more oxygen than the stoichiometric composition loses some oxygen by heating. The oxygen released from the insulating film 114 is supplied to the semiconductor layer 101, which is an oxide semiconductor, and oxygen vacancies in the oxide semiconductor can be reduced. As a result, a change in the electrical characteristics of the transistor can be suppressed and reliability can be improved.

The oxide film containing more oxygen than the oxygen required for the stoichiometric composition has a desorption amount of oxygen of 1.0×10 ¹ or more in terms of oxygen atoms as measured by thermal desorption spectroscopy (TDS).
The oxide film has a surface density of 100° C. or higher and preferably ^3.0 ×10 ²⁰ atoms/cm ³ or ^higher .
The temperature range is preferably 00° C. or lower, or 100° C. or higher and 500° C. or lower.

For example, as such a material, it is preferable to use a material containing silicon oxide or silicon oxynitride. Alternatively, a metal oxide can be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, etc. can be used. Note that in this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

Alternatively, in order to make the insulating film 114 contain excess oxygen, oxygen may be introduced into the insulating film 114 to form a region containing excess oxygen. For example, oxygen (including at least oxygen radicals, oxygen atoms, or oxygen ions) is introduced into the insulating film 114 after film formation to form a region containing excess oxygen. Examples of a method for introducing oxygen include ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, and the like.

The semiconductor layer 101 includes an oxide semiconductor. An oxide semiconductor is preferably used as a semiconductor material having a wider band gap and a lower carrier density than silicon, because the current in the off state of the transistor can be reduced. In addition, when the semiconductor layer 101 includes an oxide semiconductor, fluctuations in electrical characteristics are suppressed, and a highly reliable transistor can be realized.

Here, for the semiconductor layer 101, for example, the oxide semiconductor described in Embodiment 1 or 2 can be used.

Note that in this specification and the like, when an oxide semiconductor layer is referred to as being substantially intrinsic, the carrier density of the oxide semiconductor layer is less than 1×10 ¹⁷ /cm ³ , less than 1×10 ¹⁵ /cm ³ , or less than 1×10 ¹³ /cm ^{3 .}
By highly purifying the oxide semiconductor layer to be intrinsic, the transistor can have stable electrical characteristics.

Here, a detailed description will be given of a case where a laminated film of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c is used as the semiconductor layer 101. The semiconductor layer 101b is preferably made of an oxide having a higher electron affinity than the insulator layer 101a and the insulator layer 101c. For example, the semiconductor layer 101b is made of an oxide having an electron affinity of 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV, higher than the insulator layer 101a and the insulator layer 101c. The electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

By using an oxide having a larger electron affinity than the insulator layers 101a and 101c as the semiconductor layer 101b, when an electric field is applied to the gate electrode,
Of the semiconductor layer 101b and the insulator layer 101c, a channel is formed in the semiconductor layer 101b, which has a larger electron affinity. Here, by forming a channel in the semiconductor layer 101b, for example, the channel formation region is separated from the interface with the gate insulating film 102, so that the influence of scattering at the interface with the gate insulating film can be reduced. Thus, the field effect mobility of the transistor can be increased. Here, as the semiconductor layer 101b and the insulator layer 101c share the same constituent elements as described later, almost no interface scattering occurs.

In addition, when a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or the like is used as the gate insulating film, silicon contained in the gate insulating film may be mixed into the oxide semiconductor film. When silicon is contained in the oxide semiconductor film, the crystallinity of the oxide semiconductor film may be reduced, and the carrier mobility may be reduced. Therefore, in order to reduce the impurity concentration, for example, the silicon concentration, of the semiconductor layer 101b in which the channel is formed, the semiconductor layer 10
It is preferable to provide an insulator layer 101c between the semiconductor layer 101b and the gate insulating film 114. For the same reason, it is preferable to provide an insulator layer 101a between the semiconductor layer 101b and the insulating film 114 in order to reduce the influence of impurity diffusion from the insulating film 114.

For example, an oxide semiconductor film containing indium, an element M, and zinc may be used as the semiconductor layer 101b. For example, the oxide semiconductor film described in Embodiment 1 or 2 is preferably used.

The semiconductor layer 101b is formed using, for example, an oxide having a large energy gap, for example, 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.7 eV, and more preferably 2.8 eV to 3.3 eV.

Next, the insulator layer 101a and the insulator layer 101c will be described.
The insulating layer 101a and the insulating layer 101c each contain at least one element other than oxygen that constitutes the semiconductor layer 101b,
Since the insulator layer 101a and the insulator layer 101c are composed of one or more elements other than oxygen that constitute the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b and the interface between the semiconductor layer 101b and the insulator layer 101c are preferably made of at least one of oxygen and at least one of oxygen.
At the interface with 01c, an interface state is unlikely to be formed.

The band structure is shown in FIG. 11. In FIG. 11,
vel), the conduction band minimum energy (denoted as Ec) and the valence band maximum energy (denoted as Ev) of each layer.

Here, there may be a mixed region of the insulator layer 101a and the semiconductor layer 101b between the insulator layer 101a and the semiconductor layer 101b.
In some cases, a mixed region of the semiconductor layer 101b and the insulator layer 101c may be present between the first and second layers 101a and 101b.
The mixed region has a low interface state density.
The stack of the insulating layer 101c and the insulating layer 101b has a band structure in which the energy changes continuously (also called a continuous junction) in the vicinity of the interface between the stack of the insulating layers 101c and 101b.

At this time, the electrons are not transferred to the insulator layer 101a and the insulator layer 101c but to the semiconductor layer 1
As described above, the electrons move mainly through the insulating layer 101a and the semiconductor layer 101b.
By reducing the interface state density at the interface between the semiconductor layer 101b and the insulator layer 101c, the movement of electrons in the semiconductor layer 101b is less hindered, and the on-current of the transistor can be increased.

11 shows a case where the Ec of the insulator layer 101a and the Ec of the insulator layer 101c are similar, but they may be different from each other. For example, the Ec of the insulator layer 101c may have a higher energy than that of the insulator layer 101a.

As shown in FIG. 12B, the side surface of the semiconductor layer 101b is covered with the conductive layer 104a and the conductive layer 104b.
12C, the electric field of the gate electrode 103 causes
The semiconductor layer 101b can be electrically surrounded (the structure of a transistor in which a semiconductor is electrically surrounded by the electric field of a conductor is called a surrounded channel (s-c
This is called an s-channel structure.) By providing the gate electrode 103 facing the upper surface and side surfaces of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the upper surface of the semiconductor layer 101b but also throughout (bulk) the semiconductor layer 101b. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current (on-current) during conduction can be increased.

Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since the transistors can be miniaturized, a semiconductor device having the transistors can be a highly integrated and highly dense semiconductor device. For example,
The transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less, and a channel width of preferably 40 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less. In particular, the smaller the channel width, the wider the region in which the channel is formed into the semiconductor layer 101b, and therefore the smaller the size, the higher the contribution to the on-current.

For example, In-M-Zn oxide can be used as the insulator layer 101a and the insulator layer 101c.

Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, for example, the insulating layer 101c may contain indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

More preferably, the insulator layer 101c contains gallium oxide.
When gallium oxide is contained in c, a lower off-current can be achieved in some cases.

The insulating layer 101a and the insulating layer 101c are preferably an nc-OS film or a CAAC-OS film.
By increasing the AC ratio, for example, defects can be reduced. Also, for example, regions having spinel type crystals can be reduced. Also, for example, carrier scattering can be reduced. Also, for example, a film with high impurity blocking ability can be obtained. Also, incorporation of impurities into the semiconductor layer 101b can be suppressed, and the impurity concentration of the semiconductor layer 101b can be reduced.

The n-c ratio of the insulator layer 101a and the insulator layer 101c is preferably, for example, 10% or more.
30% or more is preferable, 50% or more is preferable, 80% or more is preferable, 90% or more is preferable, and 95% or more is preferable.

Here, the insulating layer 101a, the semiconductor layer 101b, and the insulating layer 101c are In-M-Zn
Let us consider the case where the insulator layer 101a is an oxide. The atomic ratios of In, element M, and Zn contained in the insulator layer 101a are x _a , y _a , and _za . Similarly, the atomic ratios of In, element M, and Zn contained in the semiconductor layer 101b are
The atomic ratios of In, element M, and Zn in the insulator layer 101c are denoted by _xb , _yb , and _zb . Similarly, the atomic ratios of In, element M, and Zn in the insulator layer 101c are denoted by _xc , _yc, and _zc . Preferred values of each will be described below.

x _b , y _b and z _b are the regions 11, 12 and 13 shown in FIG. 1, FIG. 2(A) and FIG.
It is preferable that the range is any of the ranges 14 and 15.

It is preferable that the insulator layer 101a and the insulator layer 101c do not contain a spinel type crystal structure or contain only a small amount of the spinel type crystal structure. Therefore, _xa : _ya : _za and _xc : _yc : _zc are, for example, as shown in FIG.
It is preferable that the value of the electron affinity of the semiconductor layer 101b is within the range of the region 11 and is smaller than that of the semiconductor layer 101b.

In order to make the electron affinity of the semiconductor layer 101b greater than those of the insulator layers 101a and 101c, it is preferable to make the indium content of the semiconductor layer 101b greater than those of the insulator layers 101a and 101c, for example.

For example, _xb /(xb+ _yb + _zb )> _xa /( _xa + _ya + _{za )} , and _xb /(x
It is preferable that _xc /(xc+ _yc + _zc ) > _xc /( _xc + _yc + _zc ).

For example, preferably, x _a /(x _a +y _a )<0.5, and more preferably, x _a /(x
_a + _ya ) < 0.33, and more preferably _xa / ( _xa + _ya ) < 0.25. Also, preferably _xb / ( _xb + _yb ) ≥ 0.25, and more preferably _xb / (
xc/ _(xc + _yc )≧0.34. Also, preferably _xc /( _xc + _yc )<0.5, more preferably _xc /( _xc + _yc )<0.33, and even more preferably _xc /( _xc
+ _yc ) < 0.25.

Alternatively, _it is preferable that _xa , ya, _za , and _xc , _yc , _zc have the ratio of the number of atoms in the region 16 shown in Fig. 2(B). Here, the region 16 is a region having a first coordinate K (x:y:z=8:
14:7), the second coordinate R (x:y:z=2:4:3), and the third coordinate L (x:y:z
= 2:5:7), the fourth coordinate M (x:y:z = 51:149:300), the fifth coordinate B (x:y:z = 1:4:10), the sixth coordinate C (x:y:z = 1:1:4), and the seventh coordinate
The area 16 is an area formed by connecting the coordinate A (x:y:z=2:2:1) of the first coordinate with the first coordinate K by a line segment in order. Note that the area 16 includes all the coordinates.

In addition, when the transistor has an s-channel structure, a channel is formed in the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor can be. For example, the semiconductor layer 101b may have a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may decrease, for example, the semiconductor layer 101b may have a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less.

In order to increase the on-state current of the transistor, the smaller the thickness of the insulating layer 101c, the more preferable. For example, the thickness is less than 10 nm, preferably 5 nm or less, and more preferably 3 nm.
On the other hand, the insulator layer 101c is formed by transferring elements other than oxygen (hydrogen,
The insulating layer 10 has a function of blocking the intrusion of foreign matter such as silicon.
It is preferable that the insulating layer 101c has a certain thickness. For example, the insulating layer 101c may have a region having a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. In addition, the insulating layer 101c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the gate insulating film 102 and the like.

In order to increase reliability, it is preferable that the insulating layer 101a is thick and the insulating layer 101c is thin. For example, the insulating layer 101a is 10 nm or thicker, preferably 20 nm or thicker, and more preferably 40 nm or thicker.
The insulating layer 101a may have a region having a thickness of 0 nm or more, and more preferably 60 nm or more. By increasing the thickness of the insulating layer 101a, the insulating layer 101a may have a region having a thickness of 0 nm or more, and more preferably 60 nm or more.
It is possible to increase the distance from the interface with the semiconductor layer 101a to the semiconductor layer 101b in which the channel is formed.
However, since the productivity of the semiconductor device may decrease, for example, the insulating layer 1 having a region with a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less is not preferred.
It would be 01a.

When a large amount of hydrogen or moisture is contained in an oxide semiconductor film, a donor level due to hydrogen may be formed. The formation of the donor level may cause the threshold voltage of a transistor to shift in the negative direction. Therefore, it is preferable to perform a dehydration treatment (dehydrogenation treatment) after the formation of the oxide semiconductor film to remove hydrogen or moisture and highly purify the oxide semiconductor film so that impurities are not contained as much as possible.

Note that dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film may also reduce oxygen. Thus, after the dehydration treatment, oxygen vacancies in the oxide semiconductor film are preferably filled by supplying oxygen. In this specification and the like, supplying oxygen to the oxide semiconductor film may be referred to as oxygen-adding treatment. Alternatively, increasing the proportion of oxygen in the oxide semiconductor film to a proportion higher than that in the stoichiometric composition may be referred to as excessive oxygen treatment.

In this way, by removing hydrogen or moisture by the dehydration treatment and then supplementing the oxygen deficiency by the oxygen addition treatment, it is possible to obtain i-type (intrinsic) or a material that is very close to i-type, i.e., substantially i
Note that being substantially intrinsic means that the oxide semiconductor film contains very few carriers derived from donors (close to zero) and has a carrier density of 1×10 ¹⁷ /cm ³ or less, 1×10 ¹⁶ /cm ³ or less, 1×10 ¹⁵ /cm ³ or less, 1×10 ¹⁴ /cm ³ or less, or 1×10 ¹³ /cm ³ or less.

A transistor including an i-type or substantially i-type oxide semiconductor film can achieve an extremely excellent off-state current. For example, the off-state current of a transistor using an oxide semiconductor film can be 1×10 ⁻¹⁸ A or less, preferably 1×10 ⁻²¹ A or less, more preferably 1×10 ^{−24 A or less at room temperature (about 25° C.), or 1×10 −15} A or less, preferably 1×10 ⁻¹⁸ A or less, more preferably 1× ^{10 −21 A} or less at 85° C. Here, the off-state current refers to a drain current when the transistor is in an off state. In addition, the off-state of a transistor refers to a state in which the gate voltage is sufficiently lower than the threshold voltage in the case of an n-channel transistor. Specifically, when the gate voltage is 1 V or more, 2 V or more, or 3 V or more lower than the threshold voltage, the transistor is in an off state.

One of the conductive layer 104a and the conductive layer 104b functions as a source electrode and the other functions as a drain electrode.

The conductive layers 104a and 104b have a single-layer structure or a stacked-layer structure using a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as a main component. For example,
Examples of such a structure include a single layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a three-layer structure in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, and a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon.
A transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Aluminum oxide, hafnium oxide, gallium oxide, Ga-Zn based metal oxide, silicon nitride, or the like may be used, and the film may be provided as a laminated layer or a single layer.

Furthermore, the gate insulating film 102 may be made of a high-k material such as hafnium silicate (HfSiO _x ), hafnium silicate doped with nitrogen (HfSi _x O _y N _z ), hafnium aluminate doped with nitrogen (HfAl _x O _y N _z ), or yttrium oxide.

The gate insulating film 102 can be formed using an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide; or a mixed material of these.

Like the insulating film 114, the gate insulating film 102 is preferably an oxide insulating film containing more oxygen than the stoichiometric composition.

In addition, when a specific material is used for the gate insulating film, electrons can be captured in the gate insulating film under specific conditions, and the threshold voltage can be shifted in the positive direction. For example, a material with many electron capture levels, such as hafnium oxide, aluminum oxide, or tantalum oxide, is used for a part of the gate insulating film, such as a laminated film of silicon oxide and hafnium oxide, and the potential of the gate electrode is kept higher than the potential of the source electrode or drain electrode for one second or more, typically one minute or more, at a higher temperature (a temperature higher than the operating temperature or storage temperature of the semiconductor device, or 125° C. to 450° C., typically 150° C. to 300° C.). Electrons move from the semiconductor layer toward the gate electrode, and some of them are captured by the electron capture levels.

The gate electrode 103 can be formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-mentioned metals, or an alloy combining the above-mentioned metals. A metal selected from one or more of manganese and zirconium may also be used. A semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may also be used. The gate electrode 103 may have a single layer structure or a laminated structure of two or more layers. For example, there are a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, and a three-layer structure in which a titanium film is laminated on the titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed on the aluminum film. In addition, the aluminum may have a single layer structure,
Alternatively, an alloy film made of one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, or a nitride film may be used.

The gate electrode 103 may be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added. A stacked structure of the light-transmitting conductive material and the metal may also be used.

Between the gate electrode 103 and the gate insulating film 102, an In-Ga-Zn-based oxynitride semiconductor film, an In-Sn-based oxynitride semiconductor film, an In-Ga-based oxynitride semiconductor film, an In-Zn-based oxynitride semiconductor film, an Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (I
nN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, which is larger than the electron affinity of an oxide semiconductor. Therefore, the threshold voltage of a transistor using an oxide semiconductor can be shifted in the positive direction, and a switching element with so-called normally-off characteristics can be realized. For example, when an In-Ga-Zn-based oxynitride semiconductor film is used, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration at least higher than that of the semiconductor layer 101, specifically, an In-Ga-Zn-based oxynitride semiconductor film having a nitrogen concentration of 7 atomic % or more is used.

This concludes the explanation of transistor 100.

Note that the channel length is, for example, the length of a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or the length of a source (source region or source electrode) in a region where a channel is formed.
The channel length refers to the distance between the drain (drain region or drain electrode) and the gate of a transistor. Note that the channel length of a single transistor does not necessarily have the same value in all regions. That is, the channel length of a single transistor may not be determined to a single value. Therefore, in this specification, the channel length refers to any one value, maximum value, minimum value, or average value in the region where the channel is formed.

The channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed. Note that the channel width of one transistor does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) may differ from the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width). For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence of this may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

However, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from a design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in this specification, the apparent channel width, which is the length of the portion where the source and drain face each other in the region where the semiconductor and the gate electrode overlap in the top view of the transistor, is referred to as the "surrounded channel width (SCW)".
In this specification, when simply referred to as a channel width, it may refer to a surrounded channel width or an apparent channel width. In this specification, when simply referred to as a channel width, it may refer to an effective channel width.
The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by obtaining a cross-sectional TEM image or the like and analyzing the image.

In addition, when calculating the field effect mobility of a transistor, the current value per channel width, and the like, the calculation may be performed using the enclosed channel width. In that case, the calculated value may be different from the value calculated using the effective channel width.

[Transistor Example 2]
An example of a structure of a transistor including an oxide semiconductor film according to one embodiment of the present invention, which is different from that of FIG 12, will be described with reference to FIG 13. FIG 13A is a top view of a transistor 100 which is a semiconductor device according to one embodiment of the present invention, FIG 13B corresponds to a cross-sectional view of a cut surface taken along dashed line X1-X2 in FIG 13A, and FIG 13C corresponds to a cross-sectional view of a cut surface taken along dashed line Y1-Y2 in FIG 13A.

The transistor 100 includes a gate electrode 203a functioning as a gate electrode over a substrate 50, a gate insulating film 202 over the substrate 50 and the gate electrode 203a, a semiconductor layer 201 over the gate insulating film 202, and a conductive layer 204a and a conductive layer 204b functioning as a source electrode and a drain electrode electrically connected to the semiconductor layer 201.
More specifically, an insulating film 21 is formed on the conductive layer 204 a, the conductive layer 204 b and the semiconductor layer 201.
4. An insulating film 216 and an insulating film 218 are stacked in this order.

Next, we will explain the components included in the transistor of this embodiment.

For the gate electrode 203a which functions as the gate electrode of the transistor 100, the description of the gate electrode 103 can be referred to.

For the gate insulating film 202 that functions as the gate insulating film of the transistor 100, the description of the gate insulating film 102 may be referred to. Alternatively, the gate insulating film 202 may be a stacked film of two or more layers. For example, as shown in FIG. 13, the gate insulating film 202 may have a two-layer structure of a gate insulating film 202a and a gate insulating film 202b. In this case, for example, the lower layer, the gate insulating film 20
A film having a function as a blocking film that suppresses the permeation of oxygen may be used as 2a. As a film having a function as a blocking film, for example, the barrier film 111 described later may be referred to.

The oxide semiconductor film described in Embodiment 1 or 2 may be used as the semiconductor layer 201. The description of the semiconductor layer 101 may be referred to for the semiconductor layer 201. The semiconductor layer 201 may be a stacked film of two or more layers.

The insulating films 214, 216, and 218 function as protective insulating films for the transistor 100. The insulating film 214 also functions as a film for reducing damage to the semiconductor layer 201 when the insulating film 216 is formed.

It is more preferable that the insulating films 214 and 216 each have a region that contains oxygen in excess of the stoichiometric composition (oxygen excess region) like the insulating film 114 described above.

Furthermore, the insulating film 214 preferably has a small amount of defects, and typically, the spin density of a signal appearing at g=2.001 originating from silicon dangling bonds in an ESR measurement is preferably 3×10 ¹⁷ spins/cm ³ or less. If the insulating film 214 has a large defect density, oxygen bonds to the defects, and the amount of oxygen permeating through the insulating film 214 decreases.

In addition, in the insulating film 214, all of the oxygen that has entered the insulating film 214 from the outside is
Some oxygen does not move to the outside of the insulating film 214 and remains in the insulating film 214. In addition, oxygen may enter the insulating film 214 and move out of the insulating film 214, causing movement of oxygen in the insulating film 214. When an oxide insulating film that can transmit oxygen is formed as the insulating film 214, oxygen desorbed from the insulating film 216 provided over the insulating film 214 can be moved to the semiconductor layer 201 through the insulating film 214.

The insulating film 214 has an upper valence band energy (E _{v_os} ) of the oxide semiconductor film.
An oxide insulating film having a low density of nitrogen oxide levels between E v_os and the energy of the bottom of the conduction band (E _{c_os} ) can be used as the oxide insulating film having a low density of nitrogen oxide levels between E _{v_os} and E _{c_os} . A silicon oxynitride film that releases a small amount of nitrogen oxide, an aluminum oxynitride film that releases a small amount of nitrogen oxide, or the like can be used as the oxide insulating film having a low density of nitrogen oxide levels between E v_os and E c_os .

A silicon oxynitride film that releases a small amount of nitrogen oxide is a film that releases more ammonia molecules than nitrogen oxides in thermal desorption spectrometry, and typically releases ammonia molecules at a rate of 1×10 ¹⁸ molecules/cm ³ or more and 5×10 ¹⁹ molecules/cm ³ or less. The amount of ammonia molecules released is determined when the surface temperature of the film is 50° C. or more and 650° C. or less, preferably 5
The amount of release is determined by heat treatment at a temperature of 0° C. or higher and 550° C. or lower.

Nitrogen oxides (NO _x , where x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO ₂ or NO, form a level in the insulating film 214 or the like.
The level of nitrogen oxide is located within an energy gap of 1. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 214 and the semiconductor layer 201, the level may trap electrons on the insulating film 214 side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating film 214 and the semiconductor layer 201, shifting the threshold voltage of the transistor in the positive direction.

Nitrogen oxide reacts with ammonia and oxygen during heat treatment.
Nitrogen oxide contained in the insulating film 214 reacts with ammonia contained in the insulating film 216 during heat treatment, and thus the nitrogen oxide contained in the insulating film 214 is reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 214 and the semiconductor layer 201.

Note that the insulating film 214 has a function of protecting the back channel region of the semiconductor layer 201 by being in contact with the semiconductor layer 201 on the side opposite to the region where a channel is formed (hereinafter referred to as a back channel region).

By using an oxide insulating film having a low density of nitrogen oxide states between E _{v_os} and E _{c_os} as the insulating film 214, a shift in the threshold voltage of the transistor can be reduced, and fluctuations in the electrical characteristics of the transistor can be reduced.

In addition, the oxide insulating film having a low density of nitrogen oxide levels between E _{v_os} and E _{c_os} is S
The nitrogen concentration measured by IMS is 6×10 ²⁰ atoms/cm ³ or less.

Furthermore, it is preferable that the insulating film 216 has a small amount of defects. Typically, the spin density of a signal appearing at g=2.001 due to dangling bonds of silicon measured by ESR measurement is less than 1.5×10 ¹⁸ spins/cm ³ , and furthermore, less than 1×10 ¹⁸ spins/cm ^{3 .}
It is preferable that the insulating film 216 has a thickness smaller than that of the semiconductor layer 214.
Since it is far from 01, it is acceptable for the defect density to be higher than that of the insulating film 214.

The transistor 100 may have a structure shown in Figures 14 and 15. Here, the transistor 100 shown in Figure 13 is a channel-etched transistor, but the transistor 100 shown in Figures 14 and 15 is a channel-protective transistor.

14A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, FIG. 14B corresponds to a cross-sectional view of a cut surface taken along dashed line X1-X2 in FIG. 14A, and FIG. 14C corresponds to a cross-sectional view of a cut surface taken along dashed line Y1-Y2 in FIG. 14A. The transistor 100 shown in FIG. 14 includes a gate electrode 203a provided over a substrate 50, a gate insulating film 202 formed over the substrate 50 and the gate electrode 203a, a semiconductor layer 201 overlapping with the gate electrode 203a through the gate insulating film 202, an insulating film 214 over the gate insulating film 202 and the semiconductor layer 201, an insulating film 216 over the insulating film 214, and a semiconductor layer 201 in openings 141a and 141b of the insulating film 214 and the insulating film 216.
The transistor 1 has a pair of conductive layers 204a and 204b in contact with the transistor 1.
An insulating film 218 may be provided over the insulating film 216, more specifically, over the conductive layer 204a, the conductive layer 204b, and the insulating film 216.

15A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, FIG. 15B is a cross-sectional view taken along dashed line X1-X2 in FIG. 15A, and FIG. 15C is a cross-sectional view taken along dashed line Y1-Y2 in FIG. 15A. The transistor 100 in FIG. 15 is a semiconductor device of one embodiment of the present invention.
15. The shape of the insulating films 214 and 216 is different from that of the transistor 10 shown in FIG.
The insulating films 214 and 216 of 00 are provided in an island shape on the channel region of the semiconductor layer 101 .
The other configuration is similar to that of the transistor 100 shown in FIG. 14, and the same effects are obtained.

14 and 15, the semiconductor layer 201 is covered with the insulating films 214 and 216 when the pair of conductive layers 204a and 204b are formed, and therefore the semiconductor layer 201 is not damaged by etching to form the pair of conductive layers 204a and 204b. Furthermore, by using an oxide insulating film containing nitrogen and having a small amount of defects as the insulating films 214 and 216, a transistor with improved reliability can be manufactured in which fluctuations in electrical characteristics are suppressed.

16A is a top view of the transistor 100 which is a semiconductor device of one embodiment of the present invention, FIG. 16B is a cross-sectional view of the cut surface taken along dashed line X1-X2 in FIG. 16A, and FIG. 16C is a cross-sectional view of the cut surface taken along dashed line Y1-Y2 in FIG. 16A. In FIG. 16, the electrode 203b is disposed between the insulating film 214 and the insulating film 218.
16, the electrode 203b and the gate electrode 203a are connected through the openings 142c and 142d. However, the electrode 203b and the gate electrode 203a may not be connected.
When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the respective electrodes.

As shown in FIG. 16, in the channel width direction, the side surface of the semiconductor layer 201 and the electrode 203b
and the gate electrode 203 a and the electrode 203 b are opposed to each other, and further in the channel width direction, the gate electrode 203 a and the electrode 203 b surround the semiconductor layer 201 via the gate insulating film 202 and the insulating film 214, and the insulating film 216 and the insulating film 218. This allows the region in the semiconductor layer 201 where carriers flow to be distributed not only to the interfaces between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201, but also to the interfaces between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201 and the semiconductor layer 201.
Since carriers also flow inside the electrode 203b, the amount of carrier movement in the transistor 100 increases. As a result, the on-current of the transistor 100 increases and the field-effect mobility increases. In addition, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201 or the end portion including the side surface and the vicinity thereof, the generation of a parasitic channel in the side surface or end portion of the semiconductor layer 201 can be suppressed.

In addition, in FIG. 16, as an example of the semiconductor layer 201, a semiconductor layer 201b is formed on a semiconductor layer 201a.
Here, for example, the energy of the bottom end of the conduction band of the semiconductor layer 201b is closer to the vacuum level than that of the semiconductor layer 201a. Typically, the difference between the energy of the bottom end of the conduction band of the semiconductor layer 201b and the energy of the bottom end of the conduction band of the semiconductor layer 201a is 0.05 eV or less.
or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less,
That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more, 0.07 eV or less, or 0.5 eV or less, or 0.4 eV or less.
V or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.
5 eV or less, or 0.4 eV or less.

The semiconductor layer 201a may be referred to the semiconductor layer 101b described in Embodiment 3. For example, the preferable range of the atomic ratio of indium, the element M, and zinc contained in the semiconductor layer 101b may be referred to. In addition, the insulating layer 101b described in Embodiment 3 may be referred to as the semiconductor layer 201b.
For example, the preferable range of the atomic ratio of indium, the element M, and zinc in the insulator layer 101c may be referred to.

[Modifications of Transistors]
Modified examples of the transistor 100 are shown in FIGS. 30 to 33. For example, the transistor 100 may have a structure shown in FIG. 30. In FIG. 30, the shapes of the conductive layers 104a and 104b are different from those in FIG. 12. Note that FIG. 30B shows the same structure as FIG. 3, which passes through the dashed dotted line A-B in FIG. 30A.
0(A) and a cross section perpendicular to the plane shown.

The transistor 100 may also have a structure shown in FIG.
31, the conductive layer 104c is in contact with the upper surfaces of the conductive layers 104a and 104b.
31B shows a cross section of a plane passing through dashed dotted line A-B shown in FIG. 31A and perpendicular to FIG. 31A. With this structure, the insulating layer 101a, the semiconductor layer 101b, and the insulating layer 101c can be successively formed without being exposed to the air during film formation, thereby reducing interface defects.

The transistor 100 may have a structure shown in FIG. 32. Note that FIG. 32B shows a cross section taken along a dashed line AB in FIG. 32A and perpendicular to FIG. 32A.
12 in that the conductive layer 104a and the conductive layer 104b are not included.
As shown in FIG. 1C, the transistor 100 may have a low-resistance layer 171a and a low-resistance layer 171b. The low-resistance layer 171a and the low-resistance layer 171b preferably function as a source region or a drain region. The low-resistance layer 171a and the low-resistance layer 171b may be doped with impurities. Doping with impurities can reduce the resistance of the semiconductor layer 101. Examples of the doped impurities include argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium,
It is preferable to add one or more selected from zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. For example, the low resistance layers 171a and 171b are formed by doping the above-mentioned impurity elements in the semiconductor layer 101 at a concentration of 5×10 ¹⁹ atoms/cm ³ or more, preferably 1×10 ²⁰ atoms/cm 3 or more.
^m3 or more, more preferably 2× ¹⁰²⁰ atoms/cm3 or ^more , and even more preferably 5×
This is a region containing 10 ²⁰ atoms/cm ³ or more. Fig. 32D is an enlarged view of a region 324 in Fig. 32C.

In some cases, impurities, such as unnecessary hydrogen, can be trapped in such a low-resistance region. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region can be reduced, and the transistor 100 can have good characteristics.

The transistor 100 may also have a structure shown in FIG.
32. Note that FIG. 33B is the same as FIG. 33A.
33A and perpendicular to FIG. 33A.

In the structure shown in FIG. 30 to FIG. 33, the insulating layer 101 is in contact with the semiconductor layer 101b.
The configuration in which the insulating layer 101a and the insulating layer 101c are provided has been described.
A configuration may be adopted in which one or both of the elements 01c are not provided.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 4)
In this embodiment, an example of a display device including the transistor described in the above embodiment will be described below with reference to FIGS.

34 is a top view showing an example of a display device. A display device 700 shown in FIG. 34 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a sealant 712 arranged to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and
and a second substrate 705 provided to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are
The first substrate 701, the sealant 712, and the second substrate 705 are used for sealing.
Although not shown in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705 .

In addition, in the display device 700, a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and an FPC terminal portion 708 electrically connected to the gate driver circuit portion 706 are provided in a region different from the region surrounded by the sealant 712 on the first substrate 701.
(FPC: Flexible printed circuit) is provided.
An FPC 716 is connected to the FPC terminal portion 708 .
, a source driver circuit portion 704, and a gate driver circuit portion 706.
, and the FPC terminal portion 708 are connected to signal lines 710. Various signals and the like supplied from the FPC 716 are applied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the signal lines 710.

A plurality of gate driver circuit portions 706 may be provided in the display device 700. Although an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702 is shown as the display device 700, the display device 700 is not limited to this configuration. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit or a gate driver circuit or the like is formed (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701. Note that a method for connecting a separately formed driver circuit substrate is not particularly limited, and a COG (chip on glass) method, a wire bonding method, or the like may be used.

Further, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 each include a wiring portion or a plurality of transistors, and the semiconductor device of one embodiment of the present invention can be applied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706.

The display device 700 can have various elements, such as liquid crystal elements, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, and inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, and blue LEDs), etc.
etc.), transistors (transistors that emit light in response to electric current), electron emission elements, electronic ink, electrophoretic elements, grating light valves (GLV), plasma displays (P
DP), display elements using MEMS (microelectromechanical systems),
The display device has at least one of a digital micromirror device (DMD), a DMS (digital micro shutter), MIRASOL (registered trademark), an IMOD (interference modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, a display element using carbon nanotubes, and the like. In addition to these, the display device may have a display medium whose contrast, brightness, reflectance, transmittance, and the like change due to electrical or magnetic action. An example of a display device using an EL element is an EL display. An example of a display device using an electron emission element is a field emission display (FED) or an SED type flat panel display (SED: Surface-conduction E
Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays).
etc. An example of a display device using electronic ink or electrophoretic elements is electronic paper. When realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may function as a reflective electrode. For example, a part or all of the pixel electrodes may be made to have aluminum, silver, or the like. In this case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. This can further reduce power consumption.

The display method of the display device 700 may be a progressive method, an interlace method, or the like.
The number of colors is not limited to three, GB (R stands for red, G stands for green, and B stands for blue). For example, the pixel may be composed of four pixels, an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, as in a Pentile arrangement, one color element may be composed of two colors out of RGB, and two different colors may be selected depending on the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. may be added to RGB. Note that the size of the display area may differ for each dot of the color element. However, the disclosed invention is not limited to a color display device, and may also be applied to a monochrome display device.

In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light (
In order to make the display device display full color using a color filter, a colored layer (also called a color filter) may be used. The colored layer may be, for example, red (R), green (G), blue (B), etc.
, yellow (Y), etc. can be used in appropriate combination.
The color reproducibility can be improved compared to when a colored layer is not used. In this case, by arranging a region having a colored layer and a region not having a colored layer, the white light in the region not having a colored layer may be directly used for display. By arranging a region not having a colored layer in a part, the decrease in luminance due to the colored layer can be reduced during bright display, and power consumption may be reduced by about 20% to 30%. However, when a full-color display is performed using self-luminous elements such as organic EL elements or inorganic EL elements, R, G, B, Y, and white (W) may be emitted from elements having the respective luminous colors. By using self-luminous elements, power consumption may be further reduced compared to when a colored layer is used.

In this embodiment, a configuration using liquid crystal elements and EL elements as display elements will be described with reference to Fig. 35 and Fig. 36. Fig. 35 is a cross-sectional view taken along dashed line QR in Fig. 34, showing a configuration using liquid crystal elements as display elements. Fig. 36 is a cross-sectional view taken along dashed line QR in Fig. 34, showing a configuration using EL elements as display elements.

First, the common parts shown in FIG. 35 and FIG. 36 will be described, and then the different parts will be described below.

[Description of common parts of the display device]
35 and 36 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The lead wiring portion 711 includes a signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790 (capacitor 790a or capacitor 790b). The source driver circuit portion 704 includes a transistor 752.

The signal line 710 is formed in the same process as the conductive films that function as the source and drain electrodes of the transistors 750 and 752.
For example, a conductive film that functions as a gate electrode may be used as the signal line 710. When a material containing copper is used as the signal line 710, a signal delay caused by wiring resistance is small, and a large-screen display is possible.

The above-described transistors can be used as the transistor 750 and the transistor 752. Here, an example is shown in which the structure of the transistor 100 shown in FIG. 13 is used as the transistor 750 and the transistor 752, but other transistors shown above may be used.

16 may be used for the transistor 750 and the transistor 752. In this case, the electrode 203b can be formed in the same process as the conductive layer 772 or the conductive layer 784. By using the structure of the transistor 100 shown in FIG. 16, the transistor 750 and the transistor 752 can be formed in the same process as the conductive layer 772 or the conductive layer 784.
2, the on-state current can be increased, thereby increasing the circuit operation speed. In addition, the channel widths of the transistor 750 and the transistor 752 can be reduced in some cases, enabling circuit integration.

The transistor used in this embodiment has an oxide semiconductor film that is highly purified and in which formation of oxygen vacancies is suppressed. The transistor can have a low current value in an off state (off-state current value). Thus, the retention time of an electric signal such as an image signal can be extended, and the writing interval can be set long in a power-on state. Thus, the frequency of a refresh operation can be reduced, which leads to an effect of suppressing power consumption.

In addition, the transistor used in this embodiment can achieve relatively high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor capable of high speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. In other words, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driver circuit, the number of components of the semiconductor device can be reduced. Furthermore, by using a transistor capable of high speed driving in the pixel portion, a high-quality image can be provided.

The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive layer 780, and an FPC 71.
The connection electrode 760 is formed in the same process as the conductive films that function as the source and drain electrodes of the transistors 750 and 752.
The terminal of the PC 716 is electrically connected via an anisotropic conductive layer 780 .

Further, for example, a glass substrate can be used as the first substrate 701 and the second substrate 705. Further, a substrate having flexibility can be used as the first substrate 701 and the second substrate 705. For example, a plastic substrate can be used as the flexible substrate.

By using a flexible substrate, a flexible display device can be manufactured. The display device having flexibility can be attached to a curved surface or an irregular shape, and a wide variety of applications can be realized.

For example, by using a flexible substrate such as a plastic substrate, the display device can be made thinner and lighter. In addition, a display device using a flexible substrate such as a plastic substrate is less likely to break and has improved durability against impact when dropped, for example.

In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and
A colored film 736 functioning as a color filter, and an insulating film 734 in contact with a light-shielding film 738 and the colored film 736 are provided.

In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film.
The structure 778 is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structure 778.
36, a structure in which the structure 778 is provided on the second substrate 705 side is illustrated, but the present invention is not limited to this. For example, a structure in which the structure 778 is provided on the first substrate 701 side or a structure in which the structure 778 is provided on both the first substrate 701 and the second substrate 705 may be used.

35 and 36, on the transistor 750 and the transistor 752,
Insulating films 764, 766, and 768 are provided.

The insulating films 764, 766, and 768 are the same as the insulating film 214 shown in the above embodiment.
, 216, 218 can be formed using the same materials and manufacturing methods.

[Example of the configuration of a display device using a liquid crystal element as a display element]
35 includes a capacitor 790a. The capacitor 790a has a structure including a dielectric between a pair of electrodes. More specifically, an oxide semiconductor film having high conductivity formed through the same process as an oxide semiconductor film functioning as a semiconductor layer of the transistor 750 is used as one electrode of the capacitor 790a, and a conductive layer 772 electrically connected to the transistor 750 is used as the other electrode of the capacitor 790a. An insulating film 768 is used as the dielectric sandwiched between the pair of electrodes.

Here, an oxide semiconductor film with high conductivity which functions as one of a pair of electrodes of the capacitor 790a will be described below.

[Highly conductive oxide semiconductor film]
When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed, hydrogen enters the oxygen vacancy sites and a donor level is formed near the conduction band. As a result, the conductivity of the oxide semiconductor is increased.
The oxide semiconductor that has been made a conductor can be called an oxide conductor. In general, an oxide semiconductor has a large energy gap and therefore transmits visible light.
On the other hand, an oxide conductor is an oxide semiconductor having a donor level in the vicinity of the conduction band, and therefore is less affected by absorption due to the donor level and has the same degree of light transmission property for visible light as an oxide semiconductor.

Here, the temperature dependence of resistivity of a film formed of an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed of an oxide conductor (hereinafter referred to as an oxide conductor film (OC)) will be described.

The temperature dependence of resistivity in the oxide conductor film (OC) is smaller than that in the oxide semiconductor film (OS). Typically, the rate of change in resistivity of the oxide semiconductor film (OC) from 80 K to 290 K is less than ±20%.
The rate of change in resistivity at or below 50 K is less than ±10%. That is, it is presumed that the oxide conductor is a degenerate semiconductor, and the conduction band edge and the Fermi level coincide or nearly coincide.
For this reason, the oxide conductor film can be used as one electrode of the capacitor 790a. Here, the oxide conductor film can be formed by forming silicon nitride on an In-M-Zn oxide, for example.

The display device 700 shown in FIG. 35 includes a liquid crystal element 775.
The display device 700 includes a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776. The conductive layer 774 is provided on the second substrate 705 side and functions as a counter electrode.
The alignment state of the liquid crystal layer 776 changes depending on a voltage applied to the conductive layers 772 and 774, whereby light transmission or non-transmission is controlled, and an image can be displayed.

The conductive layer 772 is connected to a conductive film which functions as a source electrode and a drain electrode of the transistor 750.
That is, it functions as one electrode of the display element.

The conductive layer 772 can be formed using a light-transmitting conductive material, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added.

Although not shown in Fig. 35, an alignment film may be provided on each of the conductive layers 772 and 774 on the side in contact with the liquid crystal layer 776. Although not shown in Fig. 35, optical members (optical substrates) such as a polarizing member, a retardation member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Furthermore, a backlight, a sidelight, or the like may be used as a light source.

When a liquid crystal element is used as a display element, it is possible to use thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersion type liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on the conditions.

Furthermore, when the in-plane switching mode is adopted, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to an isotropic phase when the temperature of cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used in the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing liquid crystal exhibiting a blue phase and a chiral agent is:
The response speed is short, alignment treatment is unnecessary because of optical isotropy, and viewing angle dependency is small. In addition, since no alignment film is required, rubbing treatment is also unnecessary, so electrostatic damage caused by rubbing treatment can be prevented, and defects and damage to liquid crystal display devices during the manufacturing process can be reduced.

When a liquid crystal element is used as a display element, a TN (Twisted Nematic)
) mode, IPS (In-Plane-Switching) mode, FFS (Frequency Shift Switching) mode
ge Field Switching mode, ASM (Axially Symme
Tric aligned Micro-cell mode, OCB (Optical
Compensated Birefringence mode, FLC (Ferrole
Electric Liquid Crystal mode, AFLC (AntiFerr
A 3D electrochemical liquid crystal mode or the like can be used.

In addition, the liquid crystal display device may be a normally black type liquid crystal display device, for example, a transmissive type liquid crystal display device that employs a vertical alignment (VA) mode. There are several types of vertical alignment modes, for example, MVA (Multi-Domain Vertical Alignment
) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[Display device using light-emitting elements as display elements]
The display device 700 shown in Fig. 36 includes a capacitor 790b. The capacitor 790b has a structure having a dielectric between a pair of electrodes. More specifically, a conductive film formed in the same process as a conductive film functioning as a gate electrode of the transistor 750 is used as one electrode of the capacitor 790b, and a conductive film functioning as a source electrode or drain electrode of the transistor 750 is used as the other electrode of the capacitor 790b. In addition, an insulating film functioning as a gate insulating film of the transistor 750 is used as the dielectric sandwiched between the pair of electrodes.

In addition, in FIG. 36, a planarization insulating film 770 is provided on the insulating film 768.

The planarization insulating film 770 can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimideamide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films made of these materials.
A configuration in which 0 is not provided is also possible.

The display device 700 shown in FIG. 36 includes a light-emitting element 782. The light-emitting element 782 includes:
The display device 700 shown in FIG.
An image can be displayed by the EL layer 786 of the light-emitting element 782 emitting light.

The conductive layer 784 is connected to a conductive film which functions as a source electrode and a drain electrode of the transistor 750. The conductive layer 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. A conductive film which transmits visible light or a conductive film which reflects visible light can be used as the conductive layer 784. As the conductive film which transmits visible light, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film which reflects visible light, a material containing aluminum or silver is preferably used.

36, an insulating film 730 is provided over the planarization insulating film 770 and the conductive layer 784. The insulating film 730 covers part of the conductive layer 784. Note that the light-emitting element 782 has a top-emission structure. Therefore, the conductive layer 788 has a light-transmitting property, and the E
The light emitted by the L layer 786 passes through the top emission structure. Note that, in this embodiment, a top emission structure is illustrated, but the present invention is not limited to this. For example, the present invention can be applied to a bottom emission structure in which light is emitted to the conductive layer 784 side, or a dual emission structure in which light is emitted to both the conductive layer 784 and the conductive layer 788.

A colored film 736 is provided at a position overlapping the light-emitting element 782, and a light-shielding film 738 is provided at a position overlapping the insulating film 730, the lead-out wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732.
1 shows an example of the display device 700 in which the colored film 736 is provided, but the present invention is not limited to this example. For example, when the EL layer 786 is formed by coloring, the colored film 736 may not be provided.

The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

(Embodiment 5)
In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

The display device shown in FIG. 26A includes a region having pixels of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (
hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50
5 and a terminal portion 507. Note that the protection circuit 506 does not necessarily have to be provided.

It is preferable that a part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of components and terminals.
In the case where a part or the whole of the driver circuit portion 504 is not formed on the same substrate as the pixel portion 502, a part or the whole of the driver circuit portion 504 may be formed on a substrate using a COG or TAB (Tape Automated Bonding) method.
This can be implemented by

The pixel portion 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more), and the drive circuit portion 504 has drive circuits such as a circuit (hereinafter referred to as a gate driver 504a) for outputting a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as a source driver 504b) for supplying a signal (data signal) for driving the display element of the pixel.

The gate driver 504a includes a shift register and the like.
A signal for driving the shift register is input through the terminal portion 507, and the gate driver 504a outputs the signal. For example, a start pulse signal, a clock signal, and the like are input to the gate driver 504a, and the gate driver 504a outputs a pulse signal. The gate driver 504a has a function of controlling the potential of wirings to which scan signals are applied (hereinafter, referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided, and the scan lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this.
4a may also provide another signal.

The source driver 504b includes a shift register and the like.
In addition to a signal for driving the shift register, a signal (image signal) that is the source of a data signal is input via the terminal portion 507. The source driver 504b has a function of generating a data signal to be written to the pixel circuit 501 based on the image signal. The source driver 504b also has a function of controlling the output of a data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, and the like. The source driver 504b also has a function of controlling the potential of wirings (hereinafter referred to as data lines DL_1 to DL_Y) to which a data signal is applied. Alternatively, the source driver 504b has a function of being able to supply an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches.
The source driver 504b sequentially turns on a plurality of analog switches,
A signal obtained by time-sharing an image signal can be output as a data signal. The source driver 504b may be configured using a shift register or the like.

A pulse signal is input to each of the pixel circuits 501 via one of the scanning lines GL to which a scanning signal is applied, and a data signal is input via one of the data lines DL to which a data signal is applied. Furthermore, the writing and holding of the data signal in each of the pixel circuits 501 is controlled by a gate driver 504a. For example, the pixel circuit 501 in the mth row and nth column receives a pulse signal from the gate driver 504a via a scanning line GL_m (m is a natural number equal to or less than X), and writes a data line DL_n (
A data signal is input from the source driver 504b via the pixel 504c (n is a natural number equal to or smaller than Y).

The protection circuit 506 shown in FIG. 26A includes, for example, a gate driver 504a and a pixel circuit 5
01. Alternatively, the protective circuit 506 is connected to a scanning line GL which is a wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protective circuit 506 can be connected to a wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protective circuit 506 can be connected to a wiring between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 refers to a portion provided with terminals for inputting power, control signals, and image signals from an external circuit to the display device.

The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring.

As shown in FIG. 26A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504.
By providing the 6, ESD (Electro Static Discharge:
This can improve the resistance of the display device to overcurrent caused by electrostatic discharge or the like.
However, the configuration of the protection circuit 506 is not limited thereto, and for example, the protection circuit 506 may be connected to the gate driver 504a or the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

26A shows an example in which the driver circuit portion 504 is formed by the gate driver 504a and the source driver 504b, but is not limited to this configuration. For example, a configuration in which only the gate driver 504a is formed and a substrate (e.g., a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a source driver circuit is separately formed may be mounted.

In addition, the plurality of pixel circuits 501 shown in FIG. 26A can have a configuration shown in FIG. 26B, for example.

26B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. The transistor described in the above embodiment can be used as the transistor 550.

The potential of one of a pair of electrodes of the liquid crystal element 570 is set as appropriate according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the multiple pixel circuits 501. Also, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuits 501 in each row.

For example, the driving method of the display device including the liquid crystal element 570 includes the TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned Mode), and the like.
icro-cell mode, OCB (Optically Compensated)
Birefringence mode, FLC (Ferroelectric Liquid
id Crystal) mode, AFLC (AntiFerroelectric Li
quid Crystal) mode, MVA mode, PVA (Patterned Ve
(Artical Alignment) mode, IPS mode, FFS mode, or TBA mode
(Transverse Bend Alignment) mode, etc. may also be used.
In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carbide (ECB)).
Ally Controlled Birefringence mode, PDLC (P
Olmer Dispersed Liquid Crystal) mode, PNLC
(Polymer Network Liquid Crystal) mode, guest-host mode, etc. However, the present invention is not limited to these, and various liquid crystal elements and driving methods thereof may be used.

In the pixel circuit 501 in the mth row and the nth column, one of a source electrode or a drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570.
L_m. The transistor 550 has a function of controlling writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitor 560 is a wiring to which a potential is supplied (hereinafter, a potential supply line VL
) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Note that the value of the potential of the potential supply line VL is set as appropriate according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor that holds written data.

For example, in a display device having the pixel circuit 501 shown in FIG.
The pixel circuits 501 in each row are selected in sequence by a gate driver 504a shown in FIG.

The pixel circuit 501 to which the data has been written is put into a holding state by turning off the transistor 550. By performing this process row by row, an image can be displayed.

In addition, the plurality of pixel circuits 501 shown in FIG. 26A can have a configuration shown in FIG. 26C, for example.

26C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572.
The transistor described in any of the above embodiments can be used for either one or both of the above.

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is applied (hereinafter, referred to as a signal line DL_n).
The gate electrode of No. 2 is electrically connected to a wiring (hereinafter, referred to as a scanning line GL_m) to which a gate signal is applied.

The transistor 552 has a function of controlling writing of data signals by being turned on or off.

One of the pair of electrodes of the capacitor 562 is a wiring to which a potential is applied (hereinafter, a potential supply line VL
_a), and the other is electrically connected to the other of the source electrode and drain electrode of the transistor 552.

The capacitive element 562 functions as a storage capacitor that holds the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554 .

For example, an organic electroluminescence element (also referred to as an organic EL element) can be used as the light-emitting element 572. However, the light-emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may also be used.

Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other.

In a display device having the pixel circuit 501 of FIG. 26C, for example, the pixel circuits 501 of each row are sequentially selected by the gate driver 504a shown in FIG. 26A, and the transistors 552 are turned on to write data of a data signal.

The pixel circuit 501 in which data has been written is put into a holding state by turning off the transistor 552. Furthermore, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with a luminance corresponding to the amount of current flowing. By performing this process sequentially for each row, an image can be displayed.

The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

(Embodiment 6)
An example of a semiconductor device including an oxide semiconductor according to one embodiment of the present invention will be described below.

[Example of Semiconductor Device]
37A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG 37A includes a transistor 100, a transistor 130, a capacitor 150, a wiring WBL, a wiring RBL, a wiring WL, a wiring CL, a wiring BG, and a wiring SL.

One of the source and the drain of the transistor 130 is electrically connected to the wiring RBL.
The other electrode of the transistor 100 is electrically connected to a wiring SL, and the gate of the transistor 100 is electrically connected to one of the source and drain of the transistor 100 and one electrode of the capacitor 150. The other electrode of the transistor 100 is electrically connected to a wiring WBL, and the first gate of the transistor 100 is electrically connected to a wiring WL. The other electrode of the capacitor 150 is electrically connected to a wiring CL. The wiring BG is electrically connected to a second gate of the transistor 100.
30, one of the source and drain of the transistor 100, and the capacitor element 150
The node between the electrodes of one of the electrodes is called a node FN.

37A supplies a potential corresponding to the potential of the wiring WBL to the node FN when the transistor 100 is in a conductive state (on state). Also, the semiconductor device has a function of holding the potential of the node FN when the transistor 100 is in a non-conductive state (off state).
The semiconductor device shown in FIG. 37A functions as a memory cell of a memory device.
A memory device (memory cell array) can be formed by arranging the semiconductor device shown in (A) in a matrix.

In addition, a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to the node FN
In the case where a display element such as a pixel element is included, the semiconductor device in FIG. 37A can also function as a pixel of the display device.

The conductive state or non-conductive state of the transistor 100 can be selected by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with low off-state current as the transistor 100, the potential of the node FN in the non-conductive state can be held for a long period of time. Thus, the frequency of refreshing the semiconductor device can be reduced, and a semiconductor device with low power consumption can be realized. By using a transistor including an oxide semiconductor film as the transistor 100, for example, a transistor with low off-state current can be realized.

Note that a constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. By utilizing the fact that the transistor 130 is turned on or off due to the variation in the apparent threshold voltage, information on the potential held in the node FN can be read as data.

Note that the potential held at the node FN is maintained at 85° C. for 10 years (3.15×10 ⁸ seconds).
In order to retain the capacitance, the off-state current per 1 μm of the channel width of the transistor is preferably less than 4.3 yA (1 yA is 10 ⁻²⁴ A) per 1 fF of capacitance. At this time, the allowable fluctuation in the potential of the node FN is preferably within 0.5 V. Alternatively, the off-state current at 95° C. is preferably less than 1.5 yA.

In addition, by increasing the capacitance, the potential can be held at the node FN for a longer period of time, that is, the holding time can be increased.

In the semiconductor device illustrated in FIG. 37A, by utilizing the feature that the potential of the gate electrode of the transistor 130 can be held, data can be written, held, and read as follows.

First, the potential of the wiring WL is changed by the transistor 1.
00 is set to a potential at which the transistor 100 is turned on, thereby turning on the transistor 100.
The potential of the wiring WBL is applied to the gate electrode of the transistor 130 and the capacitor 150. That is, a predetermined charge is applied to the gate electrode of the transistor 130 (writing). Here, charges that give two different potential levels (hereinafter, Low-level charge, High-level charge,
Then, the potential of the wiring WL is set to
When the transistor 100 is turned off by setting the potential at which the transistor 100 is turned off, the charge applied to the gate electrode of the transistor 130 is held (retained).

Since the off-state current of the transistor 100 is extremely small, the charge in the gate electrode of the transistor 130 is held for a long time.

Next, reading of data will be described. When a predetermined potential (constant potential) is applied to the wiring RBL and an appropriate potential (read potential) is applied to the wiring CL, the wiring SL has a different potential depending on the amount of charge held in the gate electrode of the transistor 130. This is because, in general, if the transistor 130 is an n-channel type, the apparent threshold voltage V _{th_H} when a high-level charge is applied to the gate electrode of the transistor 130 is lower than the apparent threshold voltage V _{th_L} when a low-level charge is applied to the gate electrode of the transistor 130. Here, the apparent threshold voltage refers to the potential of the wiring CL required to turn the transistor 130 on. Therefore, when the potential of the wiring CL is V _t
By setting the potential _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the gate electrode of the transistor 130 can be determined. For example, when a high-level charge is applied in writing, if the potential of the wiring CL becomes _V0 (> _{Vth_H} ), the charge applied to the gate electrode of the transistor 130 can be determined.
The transistor 130 is in an "on state". When a low-level charge is applied, even if the potential of the wiring CL becomes V ₀ (<V _{th_L} ), the transistor 130 remains in an "off state". For this reason, the stored data can be read by determining the potential of the wiring SL. Note that in order to reduce the number of wirings, for example, the WBL and RBL shown in FIG. 37A may be brought into electrical conduction.

When memory cells are arranged in an array, it is necessary to read out only the information of a desired memory cell. When no information is to be read out, the potential at which the transistor 130 is in the "off state" regardless of the state of the gate electrode, that is, _{Vth_H}
Alternatively, a potential that turns on the transistor 130 regardless of the state of the gate electrode, that is, a potential larger than _{Vth_L} , may be applied to the wiring CL.

The semiconductor device shown in FIG. 37B differs from the semiconductor device shown in FIG. 37 mainly in that the transistor 130 is not provided.
In this case as well, the writing and holding of information is possible by the same operations as described above.

Next, reading of data will be described. When the transistor 100 is turned on, the wiring BL in a floating state and the capacitor 150 are brought into electrical conduction, and charge is redistributed between the wiring BL and the capacitor 150. As a result, the potential of the wiring BL changes. The change in the potential of the wiring BL is expressed as follows:
The potential varies depending on the potential of one electrode of the capacitor 150 (or the charge stored in the capacitor 150).

For example, the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, and the potential of the wiring B is
If the capacitance component of L is CB and the potential of the wiring BL before the charge is redistributed is VB0, then
The potential of the wiring BL after the charge is redistributed is (CB×VB0+C×V)/(CB+C). Therefore, in the state of the memory cell, the potential of one electrode of the capacitor 150 is V1
When the potential V1 is held, the wiring BL
It can be seen that the potential of the wiring BL (=(CB×VB0+C×V0)/(CB+C)) is higher than the potential of the wiring BL when the potential V0 is held (=(CB×VB0+C×V0)/(CB+C)).

Then, by comparing the potential of the wiring BL with a predetermined potential, data can be read.

The semiconductor device shown in FIG. 37A or FIG. 37B can also be used as a memory device for a CPU, for example.

Fig. 38 shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in Fig. 37A. Fig. 38 shows an example in which WBL and RBL are electrically connected to each other in order to reduce the number of wirings. Fig. 38B shows a cross section taken along the dashed line A-B in Fig. 38A and perpendicular to Fig. 38A. Fig. 38C shows a cross section taken along the dashed line C-D in Fig. 38A and perpendicular to Fig. 37A.
8(A) shows a cross section perpendicular to the plane shown in FIG.

The transistor 100 is preferably provided above the transistor 130. By stacking the transistor 100 and the transistor 130, for example, the circuit area can be reduced. As the transistor 100, for example, the transistor described in Embodiment 3 can be used. FIG 38 illustrates an example in which the transistor 100 illustrated in FIG 12 is used.

The transistor 130 is made of a first semiconductor material.
00 includes a second semiconductor material. Examples of semiconductors that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium, and arsenic, compound semiconductor materials containing silicon, germanium, gallium, arsenic, aluminum, and the like, organic semiconductor materials, and oxide semiconductor materials.

The first and second semiconductor materials may be the same material, but it is more preferable that they are different semiconductor materials. Here, single crystal silicon is used as the first semiconductor material,
The case where an oxide semiconductor is used as the second semiconductor material will be described.

[First Transistor]
The transistor 130 is provided on a semiconductor substrate 131 and includes a semiconductor layer 132 made of a part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and low resistance layers 133a and 133b functioning as a source region and a drain region.

The transistor 130 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used depending on the circuit configuration and driving method.

The region in which the channel of the semiconductor layer 132 is formed and the region in the vicinity thereof, the low resistance layer 133a and the low resistance layer 133b which become the source region or the drain region, and the like preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single crystal silicon.
e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide),
The transistor 130 may be formed of a material containing GaAlAs (gallium aluminum arsenide) or the like. A structure using silicon having a distorted crystal lattice may also be used. Alternatively, the transistor 130 may be formed as a high electron MOSFET (HEMT) by using GaAs and GaAlAs or the like.
It may also be referred to as a reliability transistor.

The transistor 130 may also have regions 176a and 176b that are lightly doped drain (LDD) regions.

The low resistance layers 133a and 133b contain, in addition to the semiconductor material applied to the semiconductor layer 132, an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron.

The gate electrode 135 is made of an element that provides n-type conductivity, such as phosphorus, or a p-type element, such as boron.
Conductive materials such as semiconductor materials, such as silicon, metal materials, alloy materials, or metal oxide materials that contain elements that impart electrical conductivity of that type can be used.

Here, a transistor 190 as shown in FIG. 29A and FIG. 29B may be used instead of the transistor 130. FIG. 29B shows a cross section of a surface perpendicular to FIG. 29A, passing through the dashed line E-F shown in FIG. 29A. In the transistor 190, a semiconductor layer 132 (a part of a semiconductor substrate) in which a channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along the side and upper surface of the semiconductor layer 132. An element isolation layer 181 is provided between the transistors. Such a transistor 190 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate. Note that an insulating film that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Here, a case where the convex portion is formed by processing a part of a semiconductor substrate is shown, but the convex portion may be formed by processing a silicon on insulator (SOI).
Alternatively, a semiconductor layer having a convex shape may be formed by processing a (n insulator) substrate.

An insulating film 136 , an insulating film 137 , and an insulating film 138 are stacked in this order to cover the transistor 130 .

The insulating film 136 is formed by insulating the low resistance layer 133 a and the low resistance layer 133
It functions as a protective film when activating the element added to b that imparts conductivity.
6 may not be provided if not necessary.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By performing heat treatment, dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137, and the reliability of the transistor 130 can be improved.

The insulating film 138 functions as a planarizing layer that planarizes steps caused by the transistor 130 provided thereunder. The top surface of the insulating film 138 may be planarized by a CMP method or the like.

In addition, the insulating film 136, the insulating film 137, and the insulating film 138 are formed with the low resistance layer 133a and the low resistance layer 1
A plug 140 electrically connected to the gate electrode 135 of the transistor 130 and the like may be embedded.

A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film 111 is a layer that has a function of suppressing the diffusion of water and hydrogen from a layer below the barrier film 111 to a layer above the barrier film 111. The barrier film 111 preferably has low oxygen permeability. Here, "water and hydrogen are less likely to diffuse" means that the barrier film 111 has low permeability to water and hydrogen compared to, for example, silicon oxide that is generally used as an insulating film. The barrier film 111 has low oxygen permeability compared to, for example, silicon oxide that is generally used as an insulating film.

Materials that can be used for the barrier film 111 include so-called h-type oxides such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba,Sr)TiO ₃ (BST).
An insulating film containing an igh-k material can be used as a single layer or a laminated layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, these insulating films may be subjected to nitriding treatment to form oxynitride films. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulating films. In particular, aluminum oxide is more preferable because it has excellent barrier properties against water and hydrogen.

The above-mentioned materials are also excellent in barrier properties against oxygen as well as hydrogen and water. Therefore, oxygen released when the insulating film 114 is heated can be prevented from diffusing to layers below the barrier film 111. As a result, oxygen released from the insulating film 114 and entering the transistor 100 can be prevented from diffusing to layers below the barrier film 111.
This can increase the amount of oxygen that can be supplied to the semiconductor layer.

Here, it is preferable to reduce hydrogen, water, and the like by, for example, heat treatment in layers below the barrier film 111. The heat treatment may be performed, for example, at 170° C. or higher in an inert gas atmosphere or a reduced pressure atmosphere.

In addition, in the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment can also serve as treatment for terminating dangling bonds of silicon with hydrogen (also called hydrogenation treatment).

A conductive layer 151, a conductive layer 152a, and a conductive layer 152b are provided so as to sandwich the barrier film 111, and form a capacitor 150. The conductive layer 151 is electrically connected to the conductive layer 104a of the transistor 100.

An insulating film 114 is provided to cover the barrier film 111, the conductive layer 152a, the conductive layer 152b, the conductive layer 105, etc. For the insulating film 114, see the description of the insulating film 114 in FIG.

[Second Transistor]
The transistor 100 is provided over the insulating film 114. In the example shown in FIG.

In addition, the transistor 100 illustrated in FIG. 38 has a conductive layer 1 functioning as a second gate electrode.
The conductive layer 105 may be formed simultaneously with the conductive layers 152a and 152b which form part of the capacitor 150. By forming these conductive layers simultaneously, for example, the process can be simplified.

In addition, an insulating film 112 , an insulating film 113 , and an insulating film 116 are provided to cover the transistor 100 .

The insulating film 112 is preferably made of a material through which water or hydrogen does not easily diffuse, like the barrier film 111. In particular, it is preferably made of a material through which oxygen does not easily permeate.

The insulating film 112 may have a stacked structure of two or more layers. In that case, for example, it is preferable that the insulating film 112 has a stacked structure of two layers, and a material from which water or hydrogen does not easily diffuse is used for the upper layer. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used for the lower layer. The insulating film provided in the lower layer may be an insulating film from which oxygen is released by heating, similar to the insulating film 114, and may have a structure in which oxygen is supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102.

Covering the semiconductor layer 101 with the insulating film 112 can suppress release of oxygen from the semiconductor layer 101 above the insulating film 112. Furthermore, oxygen desorbed from the insulating film 114 and the like can be confined below the insulating film 112, so that the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

Furthermore, the insulating film 112 can prevent water or hydrogen from entering the oxide semiconductor from the outside, thereby making it possible to provide a highly reliable transistor in which fluctuations in electrical characteristics are suppressed.

The insulating film 113 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and the film may be provided as a stacked layer or a single layer.

The insulating film 116 covering the transistor 100 functions as a planarization layer that covers the uneven shape of the underlying layer. The insulating film 113 may also function as a protective film when the insulating film 116 is formed. If the insulating film 113 is not required, it is not necessary to provide it. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used as the insulating film 116, and the insulating film 116 is provided as a stacked layer or a single layer.

A plug 321, a plug 322, and a plug 123 that are electrically connected to the conductive layer 104b are embedded in the insulating films 112, 113, and 116.

On the upper portion of the insulating film 116, wiring 124 and the like that are electrically connected to the plugs 322 are provided.

38 , an insulating film 137 containing the same material as the barrier film 111 may be provided on an insulating film 136 containing hydrogen. With such a structure, water or hydrogen remaining in the insulating film 136 containing hydrogen can be effectively prevented from diffusing upward.

Wires such as the wire 124 and the wire 166, conductive layers such as the conductive layer 143, the conductive layer 151, the conductive layer 152a, the conductive layer 152b, and the conductive layer 251, and plugs 123, 139, and 140,
For the plugs such as 40, plug 164, and plug 165, conductive materials such as metal materials, alloy materials, and metal oxide materials can be used. In particular, it is preferable to use a high-melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In addition, materials such as titanium nitride and titanium may be used in a laminated state with other materials.

[Example of manufacturing method]
Next, an example of a method for manufacturing the semiconductor device in FIG. 38 will be described with reference to FIGS.

First, a semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Alternatively, an SOI substrate may be used as the semiconductor substrate 131. The following describes a case where single crystal silicon is used as the semiconductor substrate 131.

Next, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer is formed by LOC.
OS (Local Oxidation of Silicon) method or STI (Sh
The insulating layer 12 may be formed by using a method such as a bypass trench isolation method or a mesa isolation method.

When forming a p-type transistor and an n-type transistor on the same substrate, the semiconductor substrate 1
An n-well or p-well may be formed in a part of the n-type semiconductor substrate 13.
An impurity element such as boron that imparts p-type conductivity to n-type transistor 1 may be added to form a p-well, and an n-type transistor and a p-type transistor may be formed on the same substrate.

Next, an insulating film that will become the gate insulating film 134 is formed on the semiconductor substrate 131. For example,
A silicon oxide film is formed by oxidizing the surface of the semiconductor substrate 131. Alternatively, after forming silicon oxide by thermal oxidation, a nitriding treatment is performed to nitride the surface of the silicon oxide film to form a stacked structure of a silicon oxide film and a silicon oxynitride film. Alternatively, a silicon oxide film, a silicon oxynitride film, a high dielectric constant material (also called a high-k material), such as tantalum oxide, hafnium oxide, hafnium oxide silicate, zirconium oxide,
Metal oxides such as aluminum oxide and titanium oxide, or rare earth oxides such as lanthanum oxide, etc. may also be used.

The insulating film is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, etc.
site) method (including thermal CVD method, MOCVD (Metal Organic CVD) method, PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo
crystalline beam epitaxy method, ALD (Atomic Layer Deposition)
Deposition method, or PLD (Pulsed Laser Deposition) method
Alternatively, the insulating layer 12 may be formed by deposition using a ion (ion) method or the like.

Subsequently, a conductive film that becomes the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, etc., or an alloy material or compound material mainly composed of these metals. Polycrystalline silicon to which an impurity such as phosphorus is added can also be used. A laminated structure of a metal nitride film and the above-mentioned metal film may also be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing a metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

The conductive film is formed by sputtering, vapor deposition, CVD (thermal CVD, MOCVD, PEC
In order to reduce damage caused by plasma, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

Next, a resist mask is formed over the conductive film by lithography or the like to remove unnecessary portions of the conductive film, and then the resist mask is removed to form the gate electrode 135.

Here, a method for processing the film to be processed will be described. As the processing method, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by photolithography or the like may be used. Alternatively, a dummy pattern may be formed by photolithography or the like, sidewalls may be formed on the dummy pattern, the dummy pattern may be removed, and the remaining sidewalls may be used as a resist mask to etch the film to be processed. In addition, in order to realize a high aspect ratio when etching the film to be processed,
It is preferable to use anisotropic dry etching. A hard mask made of an inorganic film or a metal film may also be used.

The light used to form the resist mask is, for example, i-line (wavelength 365 nm) or g-line (wavelength 43
The laser beam may be ultraviolet light, KrF laser light, ArF laser light, or a mixture of these.
Exposure may also be performed by immersion exposure technology. As light used for exposure, extreme ultraviolet light (EUV: extreme ultra-violet) or X-rays may also be used. Instead of light used for exposure, an electron beam may also be used. Extreme ultraviolet light, X-rays or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

Furthermore, before forming the resist film that will become the resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed, for example, by a spin coating method or the like, so as to cover the steps of the lower layer and flatten the surface, and the variation in thickness of the resist mask provided on the upper layer of the organic resin film can be reduced. Furthermore, particularly when fine processing is performed, it is preferable to use a material that functions as an anti-reflection film against the light used for exposure as the organic resin film. An example of an organic resin film having such a function is BARC (Bottom Anti-Reflection Coating).
The organic resin film may be removed simultaneously with the removal of the resist mask, or may be removed after the removal of the resist mask.

Hereinafter, for the description of processing using a resist mask, refer to, for example, the processing method described for the gate electrode 135. In addition, in this specification, the description of removing the resist after etching the processed film may be omitted in some cases.

After the gate electrode 135 is formed, a sidewall may be formed to cover the side surface of the gate electrode 135. The sidewall is formed by forming an insulating film having a thickness greater than that of the gate electrode 135, and then
This can be formed by performing anisotropic etching so that the insulating film remains only on the side surfaces of the gate electrode 135 .

39 shows an example in which the gate insulating film is not etched when the sidewalls are formed, but the insulating film that will become the gate insulating film 134 may be etched at the same time when the sidewalls are formed. In this case, the gate insulating film 134 is formed under the gate electrode 135 and the sidewalls.

Next, an element that imparts n-type conductivity, such as phosphorus, or an element that imparts p-type conductivity, such as boron, is added to a region of the semiconductor substrate 131 where the gate electrode 135 (and sidewalls) are not provided. A schematic cross-sectional view at this stage corresponds to FIG.

Next, after forming the insulating film 136, for example, heat treatment is performed to activate the element that provides conductivity. The heat treatment can be performed in an inert gas atmosphere such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere at a temperature of, for example, 400° C. or higher and lower than the distortion point of the substrate.

The insulating film 136 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and may be provided as a stacked layer or a single layer. The insulating film 136 can be formed by a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the covering property can be improved. In order to reduce damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.
The LD method is preferred.

At this stage, the transistor 130 is formed. Also, the third transistor 160 may be formed in a similar manner to the method for forming the transistor 130.

Next, insulating film 137 and insulating film 138 are formed.

The insulating film 137 may be made of silicon nitride (SiNOH) containing oxygen and hydrogen, in addition to the materials that can be used for the insulating film 136. The insulating film 138 may be made of TEOS (Tetra-Ethyl-Ortho-Silicon).
It is preferable to use silicon oxide having good step coverage, which is formed by reacting silane or the like with oxygen or nitrous oxide or the like.

The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method,
The insulating film can be formed by a method such as MOCVD, PECVD, etc., MBE, ALD, or PLD. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, since the covering property can be improved. In addition, in order to reduce damage caused by plasma, a thermal CVD method, MOCVD method, or ALD method is preferable.

Then, the upper surface of the insulating film 138 is planarized by CMP or the like. A planarizing film may be used as the insulating film 138. In that case, planarization by CMP or the like is not necessarily required.
The planarizing film can be formed by, for example, atmospheric pressure CVD or coating.
Examples of films that can be formed using the VD method include BPSG (Boron Phosphor
Examples of the film that can be formed by a coating method include hydrogen silsesquioxane (HSQ). After that, a heat treatment may be performed to terminate dangling bonds in the semiconductor layer 132 with hydrogen released from the insulating film 137.

Next, openings reaching the low resistance layers 133a, 133b, the gate electrode 135, and the like are formed in the insulating films 136, 137, and 138 (see FIG. 39B). Then, a conductive film is formed to fill the openings (see FIG. 39C).
The conductive film is planarized so that the upper surface of the conductive film is exposed, thereby forming plugs 139, 140, and the like (see FIG. 39D). The conductive film can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, and the like), an MBE method, an ALD method, a PLD method, or the like.

Subsequently, the insulating film 215 is formed over the insulating film 138. The insulating film 215 can be formed using a material and a method similar to those of the insulating film 136 and the like. After the insulating film 215 is formed, heat treatment may be performed.

The third heat treatment can be performed under the conditions exemplified in the description of the stacked structure above, for example, the conditions described in the first heat treatment.

Next, an opening is formed in the insulating film 215. After that, a conductive film is formed to fill the opening, and a planarization treatment is performed on the conductive film so that the top surface of the insulating film 215 is exposed, thereby forming a conductive layer 251, a conductive layer 143, a conductive layer 151, and the like (see FIG. 39E). When a conductive film is formed in an opening, for example, a material such as titanium nitride or titanium may be formed in the opening, and then another conductive material may be stacked thereon. For example, by using titanium nitride or titanium as a lower layer of a stacked film, adhesion to the opening can be improved.

Next, a barrier film 111 is formed and an opening is formed (see FIG. 40A). The barrier film 111 is formed by, for example, a sputtering method or a CVD method (thermal CVD method, MOCVD method, PECVD method, etc.).
The thin-film deposition can be performed by using a method such as MBE, ALD, or PLD.
In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, since it is possible to improve the covering property. In order to reduce damage caused by plasma, a thermal CVD method, a MOCVD method or an ALD method is preferable.

Next, a conductive film which is to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b is formed.
After that, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see FIG. 40B).

Next, the insulating film 114 is formed. The insulating film 114 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL method.
The insulating film can be formed by a method such as CVD, preferably a plasma CVD method, since it is possible to improve the covering property. In order to reduce damage caused by plasma, a thermal CVD method, a MOCVD method, or an ALD method is preferable.

In order to make the insulating film 114 contain excess oxygen, for example, the insulating film 114 is heated in an oxygen atmosphere.
Alternatively, oxygen may be introduced into the insulating film 114 after the film formation to form a region containing excess oxygen, or both of these methods may be combined.

For example, a region containing excess oxygen is formed by introducing oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) into the formed insulating film 114. Examples of a method for introducing oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment.

In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include:
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. may be used. In addition, in the oxygen introduction process, a rare gas may be added to the gas containing oxygen.
Hydrogen, etc. may be contained. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

After the insulating film 114 is formed, a planarization treatment using a CMP method or the like may be performed to improve the planarization of the upper surface thereof.

Next, a semiconductor film to be the insulator layer 101a and a semiconductor film to be the semiconductor layer 101b are formed in this order (see FIG. 40C). It is preferable that the semiconductor films are formed successively without being exposed to the air. The semiconductor to be the insulator layer 101a and the semiconductor to be the semiconductor layer 101b may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The semiconductors to be used for the insulator layer 101a and the semiconductor layer 101b are I
When forming an n-Ga-Zn oxide layer by MOCVD, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as source gas. The combination of source gases is not limited to the above, and triethylindium, or the like may be used instead of trimethylindium. Triethylgallium, or the like may be used instead of trimethylgallium. Diethylzinc, or the like may be used instead of dimethylzinc.

Here, oxygen may be introduced into the insulator layer 101a after the insulator layer 101a is formed. For example, oxygen (including at least any of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after the film formation to form a region containing excess oxygen. The oxygen introduction method may be an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like.

In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include:
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. may be used. In addition, in the oxygen introduction process, a rare gas may be added to the gas containing oxygen.
Hydrogen, etc. may be contained. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

After the insulating layer 101a and the semiconductor layer 101b are formed, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C., in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. The heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to compensate for desorbed oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the semiconductor film is formed, or may be performed after the semiconductor film is processed to form the island-shaped insulating layers 101a and 101b.
By the heat treatment, oxygen can be supplied to the semiconductor film from the insulating film 114 or the oxide film, so that oxygen vacancies in the semiconductor film can be reduced.

Then, using a resist mask, the island-shaped insulating layer 101a and the island-shaped semiconductor layer 101b are
(See FIG. 40D ). Note that when the semiconductor film is etched, a part of the insulating film 114 is etched, and the insulating film 114 in a region not covered with the insulator layer 101 a and the semiconductor layer 101 b may become thin. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 is not lost by the etching.

Depending on the etching conditions of the semiconductor film, the resist may disappear during the etching process, so a so-called hard mask made of a material having high etching resistance, for example, an inorganic film or a metal film, may be used. Here, an example in which a conductive film is used as the hard mask 281 is shown. FIG. 41A shows an example in which a semiconductor film is processed using the hard mask 281 to form the insulating layer 101a and the semiconductor layer 101b. Here, if a material that can be used as the conductive layer 104a and the conductive layer 104b is used for the hard mask 281, the conductive layer 104a and the conductive layer 104b can be formed by processing the hard mask 281. By using such a method, for example, the transistor 100 shown in FIG. 30 can be manufactured.

40D is formed, openings reaching the conductive layers 151, 251, and the like are provided in the insulating film 114 (see FIG. 41B). Then, conductive films to become the conductive layers 104a, 104b, and the like are formed so as to fill the openings provided in the insulating film 114.
The conductive film that becomes the conductive layer 104a, the conductive layer 104b, etc. can be formed by, for example, a sputtering method, a CVD method (
Thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD
In particular, the insulating film is preferably formed by a CVD method, preferably a plasma CVD method, since it can improve the coverage. In addition, in order to reduce damage caused by plasma, a thermal CVD method, an MOCVD method, or an ALD method is preferable.

Next, unnecessary portions of the conductive film to be the conductive layers 104a, 104b, and the like are removed by etching using a resist mask to form the conductive layers 104a, 104b, and the like (
41C). During etching of the conductive film, the semiconductor layer 101b and the insulating film 1
A part of the upper portion of the semiconductor layer 101b is etched, and the portion that does not overlap with the conductive layer 104a and the conductive layer 104b may be thinned.
It is preferable to form the insulating film thick in advance, taking into consideration the etching depth.

Next, an insulating layer 101c and a gate insulating film 102 are formed. After that, they are processed by etching using a resist mask (see FIG. 42A). Next, a conductive film that becomes the gate electrode 103 is formed and processed using a resist mask to form the gate electrode 103 (see FIG. 42B).

For the method of forming the insulator layer 101c, for example, the method of forming the insulator layer 101a may be referred to.

Alternatively, oxygen may be introduced into the insulating layer 101c after the insulating layer 101c is formed. For example, oxygen (including at least any one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating layer 101c after the film formation to form a region containing excess oxygen. Examples of a method for introducing oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment.

In the oxygen introduction process, a gas containing oxygen can be used. Examples of the gas containing oxygen include:
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide, etc. may be used. In addition, in the oxygen introduction process, a rare gas may be added to the gas containing oxygen.
Hydrogen, etc. may be contained. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

At this stage, transistor 100 is formed.

Next, the insulating film 112 is formed. The insulating film 112 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, a MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, or a PL method.
The insulating film can be formed by a method such as CVD, preferably a plasma CVD method, since it is possible to improve the covering property. In order to reduce damage caused by plasma, a thermal CVD method, a MOCVD method, or an ALD method is preferable.

Heat treatment may be performed after the insulating film 112 is formed. By the heat treatment, oxygen can be supplied from the insulating film 114 or the like to the semiconductor layer 101, and oxygen vacancies in the semiconductor layer 101 can be reduced.

The insulating film 112 may also have a laminated structure of two or more layers.

Next, the insulating film 113 is formed. The insulating film 113 is formed by, for example, a sputtering method or a CVD method.
method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or P
The layer can be formed by using the LD method or the like. In particular, the CVD method, preferably the plasma CVD method,
In order to reduce damage caused by plasma, the thermal CVD method, the MOCVD method, or the ALD method is preferable.

Next, the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulating layer 101c are
Openings are provided so as to reach the conductive layer 104a etc. Next, a conductive film is formed so as to fill the openings, and then unnecessary portions are removed using a resist mask to form plugs 321 and 322.

Next, the insulating film 116 is formed. The insulating film 116 is formed by, for example, a sputtering method or a CVD method.
method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method, or P
The insulating film 116 can be formed by an LD method or the like. When an organic insulating material such as an organic resin is used as the insulating film 116, the insulating film 116 may be formed by a coating method such as a spin coating method. After the insulating film 116 is formed, it is preferable to perform planarization treatment on the upper surface of the insulating film 116. The insulating film 116 may be formed by the material or the formation method shown in the insulating film 138.

Next, in the same manner as above, the plug 12 reaching the plug 322 is formed in the insulating film 116 .
Form 3rd class.

Subsequently, a conductive film is formed over the insulating film 116. After that, unnecessary portions of the conductive film are removed by etching using a resist mask in the same manner as above, so that the wiring 124 and the like can be formed.

By the above process, a semiconductor device according to one embodiment of the present invention can be manufactured.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Seventh embodiment)
In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to drawings.

[Circuit configuration example]
Various circuits can be configured by changing the connection configurations of transistors, wirings, and electrodes in the structure shown in the semiconductor device to which Embodiment 1 is applied. Below, examples of circuit configurations that can be realized using the semiconductor device of one embodiment of the present invention are described.

[CMOS Circuit]
The circuit diagram shown in FIG. 37C is a so-called CM in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected together.
The figure shows the structure of an OS circuit. In the figure, the symbol "OS" is added to the transistors to which the second semiconductor material is applied. Here, the CMOS circuit shown in this embodiment mode is a NMOS circuit.
AND circuit, NOR circuit, encoder, decoder, MUX (multiplanplife
The present invention can be used as a basic element of logic circuits such as a DRAM (Digital Array), a DEMUX (Demultiplexer), etc.

[Analog Switch]
37D shows a configuration in which the source and drain of the transistor 2100 and the source and drain of the transistor 2200 are connected to each other.
It can function as a so-called analog switch.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 8)
In this embodiment, a display module including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

A display module 8000 shown in FIG. 27 includes an upper cover 8001, a lower cover 8002, a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 801, and a display panel 8006 connected to an FPC 8005.
0, has a battery 8011.

The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate to match the sizes of the touch panel 8004 and the display panel 8006.

The touch panel 8004 can be a resistive or capacitive touch panel that is superimposed on the display panel 8006. It is also possible to provide a touch panel function to the opposing substrate (sealing substrate) of the display panel 8006.
It is also possible to provide an optical sensor in each pixel of the touch panel 006 to form an optical touch panel.

The backlight 8007 has a light source 8008. Although Fig. 27 illustrates a configuration in which the light source 8008 is disposed on the backlight 8007, the present invention is not limited to this. For example, the light source 8008 may be disposed at an end of the backlight 8007, and a light diffusion plate may be further used. When using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel, the backlight 8007 may not be provided.

The frame 8009 has a function of protecting the display panel 8006, as well as a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. The frame 8009 may also have a function as a heat sink.

The printed circuit board 8010 has a power supply circuit, and a signal processing circuit for outputting a video signal and a clock signal. A power supply for supplying power to the power supply circuit may be an external commercial power supply, or may be a power supply from a separately provided battery 8011. The battery 8011 can be omitted when a commercial power supply is used.

The display module 8000 may further include additional components such as a polarizing plate, a retardation plate, and a prism sheet.

The display module 8000 described in this embodiment mode may have flexibility. By having flexibility, the display module can be attached to a curved surface or an irregular shape, and a wide variety of applications can be realized.

The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

(Embodiment 9)
In this embodiment, a transistor or a memory device including the transistor or the memory device described in the above embodiment is used.
The F tag will be described with reference to FIG.

The RF tag in this embodiment has an internal memory circuit, stores necessary information in the memory circuit, and transmits and receives information to and from the outside using a non-contact means, for example, wireless communication. Because of these characteristics, the RF tag can be used in an individual authentication system that identifies an item by reading individual information of the item. However, extremely high reliability is required for use in these applications.

The configuration of an RF tag will be described with reference to Fig. 28. Fig. 28 is a block diagram showing an example of the configuration of an RF tag.

As shown in FIG. 28, an RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator, a reader/writer, or the like). The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, a demodulator circuit 807, a modulator circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a material capable of sufficiently suppressing a reverse current, for example, an oxide semiconductor, may be used for a transistor exhibiting a rectifying action included in the demodulator circuit 807. This can suppress a decrease in the rectifying action caused by the reverse current and prevent the output of the demodulator circuit from being saturated. That is, the output of the demodulator circuit with respect to the input of the demodulator circuit can be made closer to linear. Note that data transmission formats are roughly classified into three types: an electromagnetic coupling type in which a pair of coils are arranged opposite each other and communication is performed by mutual induction, an electromagnetic induction type in which communication is performed by an induced electromagnetic field, and a radio wave type in which communication is performed by using radio waves. The RF tag 800 shown in this embodiment can be used for any of these types.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from an antenna 802 connected to the communication device 801. The rectifier circuit 805 is a circuit for rectifying an input AC signal generated by receiving a radio signal at the antenna 804, for example, performing half-wave double voltage rectification, and smoothing the rectified signal by a capacitive element provided in the latter stage to generate an input potential. A limiter circuit may be provided on the input side or output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so that power above a certain level is not input to a circuit in the latter stage when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. The constant voltage circuit 806 may have an internal reset signal generation circuit. The reset signal generation circuit uses the rising edge of the stable power supply voltage to reset the logic circuit 8
09 is a circuit for generating a reset signal.

The demodulation circuit 807 is a circuit for demodulating the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit for holding input information, and includes a row decoder, a column decoder, a memory area, etc. The ROM 811 is a circuit for storing a unique number (ID) and the like, and for outputting the information according to processing.

The above circuits can be selected or removed as needed.

Here, the memory circuit described in the above embodiment can be used for the memory circuit 810. The memory circuit of one embodiment of the present invention can hold information even when power is cut off, and therefore can be suitably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention requires significantly less power (voltage) to write data than a conventional nonvolatile memory, and therefore can prevent a difference in maximum communication distance between reading and writing data. Furthermore, malfunction or erroneous writing caused by a power shortage when writing data can be suppressed.

Furthermore, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory and can therefore be applied to the ROM 811. In that case, it is preferable that a command for a manufacturer to write data to the ROM 811 is separately prepared so that the user cannot freely rewrite the data. By the manufacturer writing the unique number before shipping and then shipping the product, it is possible to assign the unique number only to the non-defective product to be shipped, instead of assigning the unique number to all the manufactured RF tags, and the unique numbers of the products after shipping are prevented from becoming discontinuous, which facilitates customer management for the products after shipping.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 10)
A semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, or an image playback device including a recording medium (typically, a DVD: Digital Versatile Disk)
Other examples of electronic devices that can use the semiconductor device according to one embodiment of the present invention include mobile phones, game consoles including portable ones, portable data terminals, e-books, video cameras,
Examples include cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combination machines, automated teller machines (ATMs), vending machines, etc. Specific examples of these electronic devices are shown in FIG.

FIG. 57A shows a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, an operation key 907, a stylus 90
57A includes the two display portions 903 and 904, the number of display portions included in the portable game machine is not limited to this.

FIG. 57B shows a portable data terminal, which includes a first housing 911, a second housing 912, a first display unit 913, a second display unit 914, a connection unit 915, an operation key 916, and the like.
3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by a connection unit 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection unit 915. The image on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 at the connection unit 915. In addition, a display device to which a function as a position input device is added may be used for at least one of the first display unit 913 and the second display unit 914. The function as the position input device can be added by providing a touch panel to the display device. Alternatively, the function as the position input device can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel unit of the display device.

FIG. 57C shows a notebook personal computer, which includes a housing 921, a display portion 922,
It has a keyboard 923, a pointing device 924, etc.

FIG. 57D shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, and a freezer door 933.
33 etc.

FIG. 57E shows a video camera, which includes a first housing 941, a second housing 942, and a display unit 943.
, operation keys 944, a lens 945, a connection portion 946, etc. The operation keys 944 and the lens 945 are provided on the first housing 941, and the display portion 943 is provided on the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946.
2.

FIG. 57(F) shows a standard automobile, which includes a body 951, wheels 952, a dashboard 953,
Light 954, etc.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

(Embodiment 11)
In this embodiment, an example of the use of an RF tag according to one embodiment of the present invention will be described with reference to Fig. 56. RF tags have a wide range of uses, including, for example, banknotes, coins, securities, bearer bonds, certificates (driver's licenses and resident cards, see Fig. 56A), packaging containers (wrapping paper and bottles, see Fig. 56C), recording media (DVDs and video tapes, see Fig. 56B), vehicles (bicycles, see Fig. 56D), personal belongings (bags and glasses), food,
Plants, animals, the human body, clothing, daily necessities, medical products including medicines and pharmaceuticals, or electronic devices (
The present invention can be used by being provided on articles such as liquid crystal display devices, EL display devices, television devices, or mobile phones, or on tags attached to each article (see FIG. 56(E) and FIG. 56(F)).

The RF tag 4000 according to one embodiment of the present invention can be attached to or embedded in a surface of a device.
The RF tag 4000 according to an embodiment of the present invention is fixed to an article. For example, if the article is a book, the RF tag 4000 is embedded in paper, and if the article is a package made of organic resin, the RF tag 4000 is embedded inside the organic resin and fixed to each article. Since the RF tag 4000 according to an embodiment of the present invention is small, thin, and lightweight, the RF tag 4000 does not impair the design of the article itself even after being fixed to the article. Furthermore, by providing the RF tag 4000 according to an embodiment of the present invention to paper money, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and by utilizing this authentication function, counterfeiting can be prevented. Furthermore, by attaching the RF tag according to an embodiment of the present invention to packaging containers, recording media, personal items, food, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved. Furthermore, even in vehicles, the security against theft can be improved by attaching the RF tag according to an embodiment of the present invention.

As described above, by using the RF tag according to one embodiment of the present invention for each of the applications described in this embodiment, the operating power including writing and reading of information can be reduced, and therefore the maximum communication distance can be increased. In addition, since the RF tag can hold information for an extremely long period even when the power is cut off, the RF tag can be suitably used for applications where writing and reading are not performed frequently.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes described in this specification.

In addition, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and/or with a figure (or a part thereof) described in one or more other embodiments to form even more figures.

In addition, it is possible to configure an embodiment of the invention that specifies the exclusion of any content that is not specified in the drawings or text of the specification. Alternatively, when a numerical range is described for a certain value, such as an upper limit and a lower limit, it is possible to specify an embodiment of the invention that excludes a part of the range by narrowing the range arbitrarily or by excluding one point in the range. In this way, it is possible to specify that, for example, the prior art does not fall within the technical scope of an embodiment of the present invention.

As a specific example, suppose a circuit diagram is described in which a first to fifth transistors are used in a certain circuit. In that case, it is possible to specify that the circuit does not have a sixth transistor as an invention. Or, it is possible to specify that the circuit does not have a capacitive element. Furthermore, it is possible to configure the invention by specifying that the circuit does not have a sixth transistor having a certain specific connection structure. Or, it is possible to configure the invention by specifying that the circuit does not have a capacitive element having a certain specific connection structure. For example, it is possible to specify that the invention does not have a sixth transistor whose gate is connected to the gate of the third transistor.
Alternatively, for example, the invention can be specified so as not to have a capacitive element whose first electrode is connected to the gate of the third transistor.

As another specific example, regarding the properties of a certain substance, for example, "a certain film is an insulating film"
In this case, for example, it is possible to specify one embodiment of the invention excluding the case where the insulating film is an organic insulating film. Or, for example, it is possible to specify one embodiment of the invention excluding the case where the insulating film is an inorganic insulating film. Or, for example, it is possible to specify one embodiment of the invention excluding the case where the film is a conductive film. Or, for example, it is possible to specify one embodiment of the invention excluding the case where the film is a semiconductor film.

As another specific example, suppose that a certain laminated structure is described as "a certain film is provided between film A and film B." In that case, for example, it is possible to specify the invention such that the film is a laminated film of four or more layers excepted. Or, for example, it is possible to specify the invention such that the invention is not a case where a conductive film is provided between film A and the film.

In this specification, it is possible to take a part of a figure or text describing one embodiment and configure one aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content of the part taken out of that figure or text is also disclosed as one aspect of the invention, and it is considered that it is possible to configure one aspect of the invention. And it can be said that one aspect of the invention is clear. Therefore, for example, in a figure or text that describes one or more active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc., it is considered that it is possible to take a part of that and configure one aspect of the invention. For example, when N pieces (N
It is possible to configure one embodiment of the invention by extracting M (M is an integer, M<N) circuit elements (transistors, capacitors, etc.) from a circuit diagram having M (M is an integer, M<N) circuit elements (transistors, capacitors, etc.). As another example, it is possible to configure one embodiment of the invention by extracting M (M is an integer, M<N) layers from a cross-sectional diagram having N (N is an integer) layers. As yet another example, it is possible to configure one embodiment of the invention by extracting M (M is an integer, M<N) elements from a flow chart having N (N is an integer) elements. As yet another example, it is possible to arbitrarily extract some elements from a sentence that states "A has B, C, D, E, or F" to make it into "A has B and E,""A has E and F," or "A has C, E, and F."
Or, it is possible to construct an aspect of the invention such as "A has B, C, D, and E."

In this specification, when at least one specific example is described in a figure or text described in a certain embodiment, a person skilled in the art can easily understand that a generic concept of the specific example can be derived. Therefore, when at least one specific example is described in a figure or text described in a certain embodiment, the generic concept of the specific example is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And, it can be said that one aspect of the invention is clear.

In this specification, at least the contents shown in the drawings (or even a part of the drawings)
is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if certain content is shown in a drawing, even if it is not described in text, the content is disclosed as one aspect of the invention and can constitute one aspect of the invention. Similarly, a drawing that is a part of a drawing is also disclosed as one aspect of the invention and can constitute one aspect of the invention. And,
One aspect of the invention is clear.

In this example, we will describe the evaluation results of an oxide semiconductor film, which is one embodiment of the present invention.

[Production method]
A silicon wafer was subjected to thermal oxidation to form a silicon oxide film of 100 nm. Then, an In-Ga-Zn oxide film of 100 nm was formed as an oxide semiconductor film by a sputtering method. The conditions of the sputtering method were as follows: a polycrystalline In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn=1:1:1, a power supply of 0.5 kW (DC), and a distance between the substrate and the target of 60 mm. Argon and oxygen were used as deposition gases, and
The flow rates of argon and oxygen were 30 sccm and 15 sccm, respectively.
The substrate temperature was set to 170° C. for sample E1-1 and 300° C. for sample F1-1.

Next, a heat treatment was performed under the conditions of 450° C. in a nitrogen atmosphere for 1 hour, and then, in the same treatment chamber, a heat treatment was performed under an oxygen atmosphere at 450° C. for 1 hour.

[XRD evaluation]
Next, the results of evaluation using an XRD device will be described. The XRD device is a multifunctional thin film material evaluation X-ray diffraction device D8 DISCOVER Hybrid (manufactured by Bruker AXS).
Each sample was evaluated using the method. FIG. 43 shows the analysis results by the out-of-plane method. FIG. 43A shows the results of sample E1-1, and FIG. 43B shows the results of sample F1-1. A peak was observed in the vicinity of 2θ=31° in each sample. The peak tended to be broad when the film was formed at 170° C., and sharper when the film was formed at 300° C. This peak is attributed to the (009) plane of the InGaZnO ₄ crystals, suggesting that increasing the film formation temperature increases the crystals of the oxide semiconductor film having c-axis orientation.

[Film density evaluation]
Next, the film density was measured. The film density was evaluated by XRR (X-ray reflectometry).
The obtained film density was 6.18 [g
/cm ³ ], and sample F1-1 had a density of 6.36 [g/cm ³ ]. Under all conditions, a dense and excellent film was obtained.

[Nanobeam electron diffraction]
Next, the samples E1-1 and F1-1 were analyzed by nanobeam electron diffraction. The electron diffraction was obtained using Hitachi High-Technologies'"HF-2000". The accelerating voltage was 200 kV.

The sample stage was moved little by little to scan the upper surface of each sample having an oxide semiconductor film, and a transmission electron diffraction pattern was obtained.
A nano-beam electron beam of 100 nm was used. The same measurements were performed at three points on each sample. In other words, a total of three scans, scan 1 to scan 3, were performed on each sample.

The diffraction pattern was observed while scanning at a speed of 5 nm/sec, and a video was obtained.
The diffraction patterns observed in the obtained movie were converted into still images every 0.5 seconds. The converted still images were analyzed and classified into three patterns: an nc-OS film pattern, a CAAC-OS film pattern, and a spinel crystal structure pattern. For samples E1-1 and F1-1, the number of images classified into each pattern in Scan 1 to Scan 3 is shown in Table 3. The results of Scan 1 of the electron diffraction pattern of sample E1-1 are shown in FIGS. 44 to 48, and the results of Scan 1 of sample F1-1 are shown in Table 3.
The results of scan 1 of -1 are shown in Figures 49 to 53. Among the electron diffraction results shown in Figures 44 to 48, patterns determined to be CAAC-OS film patterns are enclosed by dashed lines. Among the electron diffraction results shown in Figures 49 to 53, patterns determined to be nc-OS film patterns are enclosed by dashed lines.

In the sample E1-1, the n-c ratio was as high as 90% or more. It was found that the n-c ratio could be increased by lowering the film formation temperature.
The sum of the c ratio and the CAAC ratio was 100%.

In this example, the film density evaluation results and TDS (Thermal Distribution Spectral Analysis) of the In-Ga-Zn oxide are shown.
The results of thermal desorption spectroscopy (thermal desorption spectroscopy) analysis are shown below.

A film of In-Ga-Zn oxide was formed on a pre-cleaned quartz substrate by sputtering. The target was polycrystalline In-
The deposition conditions were as follows: power supply was 100 W, argon and oxygen were used as deposition gases, and the flow rate of oxygen gas was 2 times the total flow rate of argon gas and oxygen gas.
%. The pressure was 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. The film formation conditions and film density are shown in Table 4.
Sample D was formed by sputtering an In-Ga-Zn oxide film, and then heat-treated at 450° C. The film density was evaluated by XRR. As shown in Table 4, sample C showed a high density of 6 g/cm ³ or more.

Next, TDS analysis was performed on sample A to sample D.
54(A) and (B) show the amount of outgassing of sample 8. The outgassing of molecular weight 18 is considered to be derived from _H2O . The amount of outgassing was large in sample A, and decreased in sample B which was subjected to heat treatment. In sample C which has a high film density, the amount of outgassing was small even without heat treatment, and it is considered that the amount of moisture contained in the film is small.

Next, for sample A to sample D, the size of the crystals due to electron beam irradiation (
The change in the crystal size was evaluated. The cross section was observed using a TEM and the crystal size was calculated. Electron beam irradiation was performed using a TEM, and the results of evaluating the relationship between the cumulative dose and the crystal size are shown in FIG. 55. In sample A, the crystals tended to grow larger with each electron beam irradiation. Here, the crystal size before electron beam irradiation may be set to the value where the cumulative dose is 0 [e ^- /nm ² ] on the approximation line shown in FIG. 55, for example. In sample B, which was subjected to heat treatment, the change in the crystal size was small. Also, in sample C and sample B, which have high film density,
In the case of D, no significant change in crystal size was observed up to a cumulative electron beam irradiation dose of 4.2×10 ⁸ [e ⁻ /nm ² ].

In this example, the stability of oxide semiconductor films was evaluated.
The method for producing the above is described below.

First, a 100 nm thick In-Ga-Z film was deposited on a quartz substrate by RF sputtering.
The target is a polycrystalline In-Ga-Zn oxide (In:Ga:Zn
n=1:1:1 [atomic ratio]) was used. The deposition gas was oxygen gas at 2 sccm and argon gas at 98 sccm. The power was 100 W. The substrate temperature during deposition was room temperature. Here, the deposition pressure for sample 1 was 0.4 Pa. The deposition pressure for sample 2 was 1.0 Pa.

In sample 3, a 100 nm thick In-Ga GaN film was deposited on a quartz substrate by DC sputtering.
The target is In—Ga—Zn oxide (In:Ga:Zn=
The deposition gas was oxygen gas at 10 sccm and argon gas at 20 sccm. The power was 200 W. The substrate temperature during deposition was 300° C. The deposition pressure was 0.4 Pa.

Next, a heat treatment was performed for 1 hour in an atmosphere containing oxygen and nitrogen.
The five conditions were 0° C., 300° C., 350° C., 400° C., and 450° C. Then, the film density of Sample 1, Sample 2, and Sample 3 was measured, including the condition where no heat treatment was performed. The film density was measured using an XRR diffractometer D8 ADVANCE manufactured by Bruker AXS.
The results for sample 1 are shown in FIG. 58(A), the results for sample 2 in FIG. 58(B), and the results for sample 3 in FIG. 58(C). The horizontal axis represents the temperature of the heat treatment. The film density of sample 1 was 5.9 g/cm.
The film density of sample ² ranged from 5.6 g/ ^cm3 to 5.8 g/ ^cm3 .
^The film density of sample 3 ranged from 6.2 g/ ^cm3 to 6.4 g/ ^cm3 .

Next, samples 1, 2 and 3 were etched using an aqueous solution of phosphoric acid diluted 100 times with pure water. The etching rates were then determined by measuring the thickness before and after etching. The results for sample 1 are shown in FIG. 59(A), those for sample 2 in FIG. 59(B) and those for sample 3 in FIG. 59(C). It was found that the higher the heat treatment temperature, the lower the etching rate for samples 1 and 2. It was found that the difference due to the heat treatment temperature was small for sample 3. Also, sample 1, which was not subjected to heat treatment, had a higher etching rate than sample 2, which was subjected to heat treatment.
It was also found that the etching rate of Sample 3, which was not subjected to heat treatment, was lower than that of Sample 1, which was subjected to heat treatment.

Next, Sample 1, Sample 2, and Sample 3 were subjected to TDS analysis to measure the amount of outgassed gas (water) with a mass-to-charge ratio of 18. The TDS analysis was performed using a thermal desorption analyzer TDS-12 manufactured by Electron Science Corporation.
The results of sample 1 are shown in FIG. 60(A), the results of sample 2 are shown in FIG. 60(B), and the results of sample 3 are shown in FIG.
The results are shown in Figure 60(C). It was found that for Sample 1, Sample 2, and Sample 3, the higher the temperature of the heat treatment, the smaller the amount of outgassing with a mass-to-charge ratio of 18 that was released. It was also found that Sample 1, which was not subjected to heat treatment, released a smaller amount of outgassing with a mass-to-charge ratio of 18 than Sample 2, which was subjected to heat treatment. It was also found that Sample 3, which was not subjected to heat treatment, released a smaller amount of outgassing with a mass-to-charge ratio of 18 than Sample 1, which was subjected to heat treatment.

Next, the hydrogen concentrations were measured for Sample 1 and Sample 2. The hydrogen concentrations were measured by SIMS.
For the SIMS, an IMS 7fR manufactured by CAMECA was used. The results for Sample 1 are shown in Fig. 61(A) and Fig. 68(A), and the results for Sample 2 are shown in Fig. 61(B) and Fig. 68(B).
In Figures 68(A) and 68(B), the horizontal axis indicates the depth from the film surface, and the vertical axis indicates the hydrogen concentration. Also, Figures 61(A) and 61(B) show the average hydrogen concentration from a depth of 10 nm to 60 nm. Also, in Figures 68(A) and 68(B), after the region where the hydrogen concentration changes suddenly in the vicinity of a depth of 80 nm, there is a possibility that the In-Ga-Zn oxide film does not remain and the quartz substrate is measured. Also, in the region less than 10 nm, there is a possibility that the surface condition may affect the hydrogen concentration. Therefore, the hydrogen concentration of the In-Ga-Zn oxide film is, for example, at a depth of 10
It is preferable to express the hydrogen concentration as an average value from 0.1 nm to 60 nm. It was found that the hydrogen concentration decreased with increasing heat treatment temperature for Samples 1 and 2. It was also found that the hydrogen concentration was lower in Sample 1, which was not subjected to heat treatment, than in Sample 2, which was subjected to heat treatment.

Next, the change in crystal size due to the heat treatment of Sample 1, Sample 2, and Sample 3 was measured by TEM. The crystal size is shown as an average value of 20 to 45 points. A Hitachi transmission electron microscope H-9000NAR was used for the TEM. The results of Sample 1 are shown in Figure 62(A) and the results of Sample 2 are shown in Figure 62(B).
The results for Sample 2 (B) and Sample 3 are shown in Figure 62 (C). It was found that the crystal size of Sample 1 was about 1.4 nm regardless of the heat treatment temperature. Sample 2 had a crystal size of about 1.2 nm when not heat treated (see Figure 67), but this grew to about 1.3 nm by heat treatment at 250°C, and further grew to about 1.6 nm by heat treatment at 300°C. No change in crystal size was observed in the range from 300°C to 450°C. Also, in Sample 3, the crystal size was 1.5 to 1.6 nm regardless of the heat treatment temperature.
Met.

Next, the change in crystal size due to electron beam irradiation in Samples 1, 2, and 3 was measured by TEM. The results for Sample 1 are shown in Figure 63(A), those for Sample 2 in Figure 63(B), and those for Sample 3 in Figure 63(C). Samples 1 and 3 showed almost no change in crystal size regardless of the heat treatment temperature, and even with electron beam irradiation. Sample 2 showed an increase in crystal size due to electron beam irradiation. This tendency was more pronounced the lower the heat treatment temperature.

When we look at the changes in crystal size due to heat treatment and electron beam irradiation,
It can be seen that Sample 1 and Sample 3 have higher stability than Sample 2. When Sample 1, Sample 2, and Sample 3 are classified according to the above-mentioned structures, Sample 1 is an nc-OS film, Sample 2 is an a-like OS film, and Sample 3 is a CAAC-OS film.

As described above, the nc-OS film has a higher film density, a lower etching rate, less water degassing, and a lower hydrogen concentration than the a-like OS film. Furthermore, these differences cannot be compensated for by heat treatment after the film formation. In other words, it is important to use an oxide semiconductor film, which is an nc-OS film, for the transistor during film formation.

In this example, the localized states of the nc-OS film were evaluated.
The measurement was performed using the stant photocurrent method.

For the CPM measurement, a gate electrode (tungsten) on a glass substrate and an nc-
an OS film, a gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film,
A sample was prepared that had a pair of electrodes (a stack of tungsten, aluminum, and titanium formed in this order) in contact with the nc-OS film, and an insulator (a stack of silicon oxynitride and silicon nitride formed in this order) over the nc-OS film and the pair of electrodes.
The film was formed to a thickness of 35 nm by AC sputtering.
The deposition gas was 10% by volume of oxygen gas and 90% by volume of argon gas.
The power was set to 0.5 kW. The substrate temperature during the film formation was set to room temperature. The film formation pressure was set to 0.6 Pa.

Next, the prepared sample was subjected to a heat treatment in a nitrogen atmosphere for one hour, and then in an atmosphere containing oxygen and nitrogen for another hour.

In the CPM measurement, a voltage is applied between a pair of electrodes provided in contact with the nc-OS film, and the amount of light irradiated onto the sample surface between the terminals is adjusted so that the photocurrent value is constant, and the absorption coefficient is derived from the amount of irradiated light. Here, the absorption coefficient is derived for each wavelength. In the CPM measurement, the absorption coefficient increases at the energy (converted from the wavelength) corresponding to the localized level density. The localized level density of the sample can be derived by multiplying this increase in the absorption coefficient by a constant.

In addition, by removing the optical absorption due to the band tail (Urbach tail) from the optical absorption spectrum curve, the absorption coefficient α due to the localized level can be calculated from the following formula.

α＝∫[(α(E) _-αu )/E]dE

Here, E is energy, α(E) is the absorption coefficient at each energy, and _αu is the absorption coefficient due to the Urbach tail.

The slope of the Urbach tail is called the Urbach energy. The lower the Urbach energy, the fewer defects there are and the steeper the slope of the tail of the level at the edge of the valence band is, which means that the semiconductor film is more ordered.

64 shows the results of fitting the absorption coefficient measured by a spectrophotometer (dotted line) and the absorption coefficient measured by CPM (solid line) in an energy range equal to or greater than the energy gap of the oxide semiconductor film. FIG. 64A shows the results of a sample that was subjected to heat treatment at 300° C. after film formation, FIG. 64B shows the results of a sample that was subjected to heat treatment at 400° C. after film formation, and FIG.
C) shows the results for samples that were heat-treated at 450° C. after film formation. The Urbach energies obtained from the absorption coefficients measured by CPM were 72.65 meV and 69
.45 meV and 70.32 meV.

In addition, the background (thin dotted line) was subtracted from the absorption coefficient derived by the CPM measurement in Fig. 64 to derive the integral value of the absorption coefficient. The results are shown in Fig. 65. The absorption coefficients due to the localized levels were 6.27 x 10 ^-1 cm ^-1 , 4.19 x 10 -1 cm -1 and 2.29 x 10 ^-1 cm ^-1 , respectively.
×10 ⁻¹ cm ⁻¹ . The relationship between the heat treatment temperature and the absorption coefficient is shown in FIG.
It can be seen that the higher the temperature of the heat treatment, the smaller the absorption coefficient becomes, and therefore the smaller the localized level density becomes.

11 Region 12 Region 13 Region 14 Region 15 Region 16 Region 21 Perpendicular line 22 Perpendicular line 23 Perpendicular line 50 Substrate 51 Insulating film 100 Transistor 101 Semiconductor layer 101a Insulating layer 101b Semiconductor layer 101c Insulating layer 102 Gate insulating film 103 Gate electrode 104a Conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 116 Insulating film 123 Plug 124 Wiring 130 Transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating film 137 Insulating film 138 Insulating film 139 Plug 140 Plug 143 Conductive layer 150 Capacitive element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 Transistor 164 Plug 165 Plug 166 Wiring 171a Low resistance layer 171b Low resistance layer 176a Region 176b Region 181 Element isolation layer 190 Transistor 191 Transistor 201 Semiconductor layer 201a Semiconductor layer 201b Semiconductor layer 202 Gate insulating film 202a Gate insulating film 202b Gate insulating film 203a Gate electrode 203b Electrode 204a Conductive layer 204b Conductive layer 214 Insulating film 215 Insulating film 216 Insulating film 218 Insulating film 251 Conductive layer 281 Hard mask 321 Plug 322 Plug 324 Region 501 Pixel circuit 502 Pixel portion 504 Driver circuit portion 504a Gate driver 504b Source driver 506 Protection circuit 507 Terminal portion 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitor element 570 Liquid crystal element 572 Light emitting element 610 Electron gun chamber 612 Optical system 614 Sample chamber 616 Optical system 618 Camera 620 Observation chamber 622 Film chamber 624 Electron 632 Fluorescent screen 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal line 711 Wiring section 712 Sealant 716 FPC
730 insulating film 732 sealing film 734 insulating film 736 colored film 738 light-shielding film 750 transistor 752 transistor 760 connection electrode 764 insulating film 766 insulating film 768 insulating film 770 planarization insulating film 772 conductive layer 774 conductive layer 775 liquid crystal element 776 liquid crystal layer 778 structure 780 anisotropic conductive layer 782 light-emitting element 784 conductive layer 786 EL layer 788 conductive layer 790 capacitance element 790a capacitance element 790b capacitance element 800 RF tag 801 communication device 802 antenna 803 radio signal 804 antenna 805 rectifier circuit 806 constant voltage circuit 807 demodulation circuit 808 modulation circuit 809 logic circuit 810 memory circuit 811 ROM
901 Housing 902 Housing 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Housing 912 Housing 913 Display section 914 Display section 915 Connection section 916 Operation key 921 Housing 922 Display section 923 Keyboard 924 Pointing device 931 Housing 932 Refrigerator door 933 Freezer door 941 Housing 942 Housing 943 Display section 944 Operation key 945 Lens 946 Connection section 951 Vehicle body 952 Wheels 953 Dashboard 954 Light 2100 Transistor 2200 Transistor 4000 RF tag 5100 Pellet 5100a Pellet 5100b Pellet 5101 Ion 5120 Substrate 5130 Target 8000 Display module 8001 Upper cover 8002 Lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 Display panel 8007 Backlight 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims (7)

a first layer having a first channel formation region of a first transistor;
a first insulating film having a region on the first layer;
a first conductive layer having a region on the first insulating film;
a second insulating film having a region on the first conductive layer;
a second conductive layer having a region in contact with an upper surface of the second insulating film;
a third conductive layer having a region in contact with an upper surface of the second insulating film;
a third insulating film having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer;
a second layer having a region on the second insulating film and having a second channel formation region of a second transistor;
a fourth conductive layer having an area in contact with an upper surface of the second layer;
a fifth conductive layer having an area in contact with an upper surface of the second layer;
a fourth insulating film having an area on the second layer;
a sixth conductive layer having a region on the third insulating film;
the first layer comprises silicon;
the second layer comprises indium, gallium, and zinc;
the fifth conductive layer is electrically connected to the first conductive layer;
the fourth conductive layer is electrically connected to a source region or a drain region of the first transistor;
the sixth conductive layer has a region overlapping with the second conductive layer via the second layer,
the second conductive layer has an area overlapping the first layer;
the second conductive layer has an area overlapping the second layer;
the third conductive layer has a region overlapping the first conductive layer via the second insulating film,
the third conductive layer has a region functioning as one electrode of a capacitor element,
the first conductive layer has a region that functions as the other electrode of the capacitor. a first layer having a first channel formation region of a first transistor;
a first insulating film having a region on the first layer;
a first conductive layer having a region on the first insulating film;
a second insulating film having a region on the first conductive layer;
a second conductive layer having a region in contact with an upper surface of the second insulating film;
a third conductive layer having a region in contact with an upper surface of the second insulating film;
a third insulating film having a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer;
a second layer having a region on the second insulating film and having a second channel formation region of a second transistor;
a fourth conductive layer having an area in contact with an upper surface of the second layer;
a fifth conductive layer having an area in contact with an upper surface of the second layer;
a fourth insulating film having an area on the second layer;
a sixth conductive layer having a region on the third insulating film;
the first layer comprises silicon;
the second layer comprises indium, gallium, and zinc;
the fifth conductive layer is electrically connected to the first conductive layer;
the fourth conductive layer is electrically connected to a source region or a drain region of the first transistor;
the sixth conductive layer has a region that functions as a first gate electrode of the second transistor,
the second conductive layer has a region that functions as a second gate electrode of the second transistor;
the second conductive layer has an area overlapping the first layer;
the second conductive layer has an area overlapping the second layer;
the third conductive layer has a region overlapping the first conductive layer via the second insulating film,
the third conductive layer has a region functioning as one electrode of a capacitor element,
the first conductive layer has a region that functions as the other electrode of the capacitor. In claim 1 or 2,
The sixth conductive layer is electrically connected to the second conductive layer. In any one of claims 1 to 3,
the second conductive layer has a region functioning as one of a source electrode and a drain electrode of the second transistor,
the third conductive layer has a region functioning as the other of the source electrode and the drain electrode of the second transistor. In any one of claims 1 to 4,
the second insulating film has a function as a barrier film,
The second insulating film comprises nitrogen and silicon. In any one of claims 1 to 5,
The third insulating film comprises oxygen and silicon. In any one of claims 1 to 6,
the second layer having a plurality of crystals;
the second layer comprises indium, gallium, and zinc;
the atomic ratio of indium to gallium and zinc in the second layer satisfies indium:element M:z=x:y:z;
In an equilibrium phase diagram with three elements of indium, gallium, and zinc as vertices, the x, y, and z have a ratio of the number of atoms within a range obtained by connecting a first coordinate (x:y:z=8:14:7), a second coordinate (x:y:z=2:4:3), a third coordinate (x:y:z=2:5:7), a fourth coordinate (x:y:z=51:149:300), a fifth coordinate (x:y:z=46:288:833), a sixth coordinate (x:y:z=0:2:11), a seventh coordinate (x:y:z=0:0:1), an eighth coordinate (x:y:z=1:0:0), and the first coordinate in this order with a line segment, and the range includes the first coordinate to the sixth coordinate, but does not include the seventh coordinate and the eighth coordinate;
A semiconductor device, wherein an electron diffraction pattern observed by irradiating an electron beam having a half-width of a probe diameter of 1 nm onto a surface on which the second layer is to be formed is a pattern in which the spots are not arranged symmetrically or a pattern in which the spots are arranged in a circular pattern.

Images