JP2023078135A - Semiconductor device - Google Patents

Abstract

To apply an excellent electric characteristic to a semiconductor device.SOLUTION: In an oxide semiconductor film, a plurality of electronic diffraction patterns is observed by irradiating an electronic beam while relatively moving a position of a film and a position of the electronic beam to a formed surface of the oxide semiconductor film by using the electronic beam of which a half value width of a probe diameter is 1nm, and the plurality of electronic diffraction patterns includes fifty or more electronic diffraction patterns observed at a different place each other. A sum of a rate having a first electronic diffraction pattern and a rate having a second electronic diffraction pattern of fifty or more electronic diffraction patterns is 100%, and the rate having the first electronic diffraction pattern is 50% or more. The first electronic diffraction pattern includes an observation point without a symmetric property and a plurality of observation points arranged so as to draw a circle. The second electronic diffraction pattern includes an observation point positioned at a top of a hexagon.SELECTED DRAWING: None

Description

Applied for application of Article 30, Paragraph 2 of the Patent Law Presented at the 61st JSAP Spring Meeting held at Aoyama Gakuin University Sagamihara Campus on March 18, 2014 and March 19, 2014

The present invention relates to an article, method or method of manufacture. Alternatively, the invention relates to a process, machine, manufacture or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, driving methods thereof, or manufacturing methods thereof.

Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are modes of a semiconductor device. Arithmetic devices, storage devices, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices may include semiconductor devices.

Physical properties of oxides containing indium and zinc are interesting and have been extensively studied (
Non-Patent Document 1, Non-Patent Document 2). In Non-Patent Document 1, In _1−x Ga _1+x O ₃ (ZnO
) _m (where x is a number that satisfies −1≦x≦1, and m is a natural number). In addition, the solid solution region of the homologous phase (solid solution r
ange) are mentioned. For example, when powders of In ₂ O ₃ , Ga ₂ O ₃ and ZnO are mixed and fired at 1350° C., the solid solution region of the homologous phase when m=1 is x
is described as −0.33 to 0.08, and the solid solution region of the homologous phase when m=2 is described as x being −0.68 to 0.32.

A compound represented by AB ₂ O ₄ (A and B are metals) is also known as a compound having a spinel crystal structure. In addition, Non-Patent _Document 1 shows an example of _InxZnyGazOw , where x, y and z _are compositions near _ZnGa2O4 , that is, x, y _and z _are (x, y
, z)=(0, 1, 2), it is described that a spinel type crystal structure is easily formed or mixed.

Also, a technique for forming a transistor using a semiconductor material has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, but oxide semiconductors are attracting attention as other materials.

For example, a technique for manufacturing a transistor using zinc oxide or an In--Ga--Zn-based oxide semiconductor as an oxide semiconductor has been disclosed (see Patent Documents 1 and 2).

In recent years, as electronic devices have become more sophisticated, smaller, and lighter, there has been a growing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are densely integrated.

Japanese Patent Application Laid-Open No. 2007-123861 JP 2007-96055 A

M. Nakamura, N.; Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350°C", J. Am. Solid State Chem. , 1991, Vol. 93, pp. 298-315 M. Nespolo, A.; Sato, T. Osawa, and H. Ohashi, "Synthesis, Crystal Structure and Charge Distribution of InGaZnO4. X-ray Diffraction Study of 20kb Single Crystal and 50kb Twin by Reticular Mer ohdry" Cryst. Res. Technol. , 2000 Vol. 35, pp 151-165

An object of one embodiment of the present invention is to impart favorable electrical characteristics to a semiconductor device.

Another object is to provide a highly reliable semiconductor device.

Another object is to provide a favorable transistor with little variation in characteristics. Another object is to provide a semiconductor device including a memory element with excellent retention characteristics. Another object is to provide a semiconductor device suitable for miniaturization. Another object is to provide a semiconductor device with a reduced circuit area. Another object is to provide a semiconductor device with a novel structure.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the statements in the specification, drawings, claims, etc.
Problems other than these can be extracted from the drawings, claims, and the like.

One embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, where the element M is at least one element selected from aluminum, gallium, yttrium, and tin. , indium, the element M, and the ratio of the number of atoms of zinc is: indium: element M
: Zinc = x: y: z, where x, y and z are the first coordinates (x: y: z = 8: 14 :7), a second coordinate (x:y:z=2:4:3), a third coordinate (x:y:z=2:5:7), and a fourth coordinate (x: y:z=51:149:300) and the fifth coordinate (x:y:z=46:288
: 833), the sixth coordinates (x:y:z=0:2:11), and the seventh coordinates (x:y:z=
0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate, and the ratio of the number of atoms in the range connecting the line segments in order is and the range includes the first to sixth coordinates, does not include the seventh and eighth coordinates, and uses an electron beam having a probe diameter half width of 1 nm to form an oxide semiconductor film. When a plurality of electron diffraction patterns are observed by irradiating an electron beam while relatively moving the position of the oxide semiconductor film and the position of the electron beam with respect to the formation surface of The pattern has 50 or more electron diffraction patterns observed at different locations, and the proportion of the 50 or more electron diffraction patterns having the first electron diffraction pattern and the second electron diffraction pattern. The sum of the percentages is 100% and the first
The electron diffraction pattern of has observation points that do not have symmetry or a plurality of observation points arranged to draw a circle, and the second electron diffraction pattern has observation points located at the vertices of the hexagon. It is an oxide semiconductor film having an oxide semiconductor film.

Alternatively, in one embodiment of the present invention, the position of the oxide semiconductor film and the position of the electron beam are positioned relative to the formation surface of the oxide semiconductor film using an electron beam whose probe diameter has a half width of 1 nm. When a plurality of electron diffraction patterns are observed by irradiating the electron beam while moving the electron beam, the plurality of electron diffraction patterns has 50 or more electron diffraction patterns observed at different locations, and 50 The sum of the ratio of having the first electron diffraction pattern and the ratio of having the second electron diffraction pattern among the 1 or more electron diffraction patterns is 100%, and the ratio of having the first electron diffraction pattern is 50%. As described above, the first electron diffraction pattern has observation points that do not have symmetry or a plurality of observation points arranged to draw a circle, and the second electron diffraction pattern has hexagonal vertices. This is an oxide semiconductor film having an observation point located at .

Alternatively, in one embodiment of the present invention, In:M(Al, Ga, Y, or Sn):Zn=x:y
:z atomic ratio, where coordinates x:y:z = 1:0:0, coordinates x:y:z = 0:1:0, and coordinates x:y : z = 0: 0: 1, in the equilibrium diagram with vertices, the first coordinate (x: y: z = 8: 14: 7) and the second coordinate (x: y: z = 2 :
4:3), the third coordinates (x:y:z=2:5:7) and the fourth coordinates (x:y:z=51
: 149:300), fifth coordinates (x:y:z=46:288:833), sixth coordinates (x:y:z=0:2:11), and seventh coordinates ( x: y: z = 0: 0: 1), the eighth coordinate (x: y: z = 1: 0: 0), and the first coordinate are connected in order with a line segment. , and by relatively moving the position of the oxide semiconductor film and the position of the electron beam having a half width of the probe diameter of 1 nm with respect to the surface on which the oxide semiconductor film is formed, 50 at different locations The above electron diffraction patterns were observed, and the 50 or more electron diffraction patterns were at least an electron diffraction pattern having a plurality of spots arranged asymmetrically and an electron diffraction pattern having a plurality of spots arranged to draw a circle. and an electron diffraction pattern having spots located at the vertices of the hexagon, wherein the range includes the first coordinate through the sixth coordinate, and the seventh
and the eighth coordinate are not included.

In the above structure, the oxide semiconductor film includes indium, element M, and zinc, element M is an element selected from at least one of aluminum, gallium, yttrium, and tin, and indium , the ratio of the number of atoms of element M and zinc is indium: element M
: Zinc = x: y: z, where x, y and z are the first coordinates (x: y: z = 8: 14 :7), a second coordinate (x:y:z=2:4:3), a third coordinate (x:y:z=2:5:7), and a fourth coordinate (x: y:z=51:149:300) and the fifth coordinate (x:y:z=46:288
: 833), the sixth coordinates (x:y:z=0:2:11), and the seventh coordinates (x:y:z=
0:0:1), the eighth coordinate (x:y:z=1:0:0), and the first coordinate are connected in order by a line segment. However, the range preferably includes the first to sixth coordinates and excludes the seventh and eighth coordinates.

Alternatively, one embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, wherein the oxide semiconductor film includes a plurality of randomly arranged crystal parts and a plurality of crystals. The oxide semiconductor film has an average diameter of 1 nm to 3 nm in the longitudinal direction of the portion.

Alternatively, one embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, wherein the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. and the atomic number ratio of indium, element M and zinc satisfies indium: element M: zinc = x: y: z, and x, y and z are the three elements of indium, element M and zinc as vertices In the equilibrium diagram, the first coordinate (x: y: z = 8: 14: 7)
, second coordinates (x:y:z=2:4:3), and third coordinates (x:y:z=2:5:7)
, fourth coordinates (x:y:z=51:149:300), and fifth coordinates (x:y:z=4
6:288:833), the sixth coordinate (x:y:z=0:2:11), and the seventh coordinate (x
: y:z=0:0:1), the eighth coordinates (x:y:z=1:0:0), and the atoms in the range connecting the first coordinates in order with a line segment the range includes the first coordinate to the sixth coordinate but does not include the seventh coordinate and the eighth coordinate; the density of the oxide semiconductor film is a single unit having the same atomic ratio; The oxide semiconductor film has a crystal density of 90% or more.

Alternatively, one embodiment of the present invention is an oxide semiconductor film including indium, an element M, and zinc, wherein the element M is an element selected from at least one of aluminum, gallium, yttrium, and tin. where the oxide semiconductor film has a plurality of randomly arranged crystal parts, the plurality of crystal parts has no orientation, and the diameter of the plurality of crystal parts in the longitudinal direction is 1 nm or more and 3 n
m or less, and the density of the oxide semiconductor film is 9 times the density of single crystals having the same atomic ratio.
The oxide semiconductor film is 0% or more.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, wherein the oxide semiconductor film includes a plurality of crystal parts, and the crystal parts have an orientation. , the average diameter of the plurality of crystal parts in the longitudinal direction is 1 nm or more and 3 nm or less, and the density of the oxide semiconductor film is 5.7 g/cm ³ or more and 6.49 g/cm ³ or less. It is a material semiconductor film. Further, in the above structure, the density of the oxide semiconductor film is preferably 90% or more of the density of the single crystal having the same atomic ratio.

Alternatively, one embodiment of the present invention is an oxide semiconductor film containing indium, gallium, and zinc, wherein the oxide semiconductor film includes a plurality of randomly arranged crystal parts. has no orientation, and the average A [nm] of the diameters in the longitudinal direction of the plurality of crystal parts is 1 nm or more.
nm or less, and the electron beam energy is 1×10 ⁷ [e ⁻ /nm ² ] or more and 4×10 ⁸ [
The average diameter B [nm] of the crystal part in the longitudinal direction after being irradiated to less than e ⁻ /nm ² ] is A×
The oxide semiconductor film is larger than 0.7 and smaller than A×1.3.

Further, in the above structure, the oxide semiconductor film is formed by a sputtering method, the target used in the sputtering method contains indium, the element M, and zinc, and the target contains atoms of indium, the element M, and zinc. The numerical ratio is indium: element M: zinc =
satisfies a:b:c, and a, b, and c are the first coordinates (a:b:c=8:14: 7), a second coordinate (a:b:c=2:4:3), a third coordinate (a:b:c=1:2:5.1), and a fourth coordinate (a :b:c=1:0:1.7), the fifth coordinate (a:b:c=8:0:1) and the sixth coordinate (a:b:c=6:2:1 ) and the first coordinate, and the ratio of the number of atoms in the range connecting the first coordinate with a line segment in order, and the range preferably includes the first coordinate to the sixth coordinate.

Alternatively, one embodiment of the present invention is a semiconductor device including the oxide semiconductor film described above.
Further, in the above structure, the oxide semiconductor includes a first conductive layer, a first insulating film in contact with the top surface and side surfaces of the first conductive layer, and a pair of electrodes in contact with the top surface of the oxide semiconductor film. The membrane is the first
preferably has a region in contact with the upper surface of the insulating film. Further, in the above structure, the first conductive layer, the first insulating film in contact with the top surface and the side surface of the first conductive layer, the second insulating film in contact with the top surface of the oxide semiconductor film, and the oxide semiconductor film. It is preferable that the oxide semiconductor film has a top surface and a pair of electrodes that are in contact with the top surface and the side surface of the second insulating film, and that the oxide semiconductor film has a region that is in contact with the top surface of the first insulating film. Further, the above structure preferably includes a second oxide film in contact with the top surface of the oxide semiconductor film. In the above structure, the electron affinity of the oxide in the oxide semiconductor film is preferably higher than the electron affinity of the oxide in the second oxide film. Further, in the above structure, the second oxide film includes indium, the element M, and zinc, and the element M
is an element selected from at least one of aluminum, gallium, yttrium, and tin, and the atomic ratio of indium, element M, and zinc in the second oxide film is indium: element M: zinc It is represented by x ₂ : y ₂ : z ₂ , and (x ₂ : y ₂ : z ₂ ) is the first coordinate (8: 1
4:7), a second coordinate (2:4:3), a third coordinate (2:5:7), and a fourth coordinate (
51:149:300), the fifth coordinate (1:4:10) and the sixth coordinate (1:1:4)
, the seventh coordinate (2:2:1), and the first coordinate are connected in order by a line segment, and the range is from the first coordinate to It preferably includes a seventh coordinate.

Alternatively, one embodiment of the present invention is a display device including the semiconductor device described above and a display element.

Alternatively, one embodiment of the present invention is a module including the semiconductor device or the display device described above, and an FPC.

Alternatively, one embodiment of the present invention is an electronic device including the above semiconductor device, the above display device, or the above module, a microphone, a speaker, or an operation key.

According to one embodiment of the present invention, a semiconductor device can have favorable electrical characteristics. again,
A highly reliable semiconductor device can be provided.

In addition, transistors with little variation can be provided. Further, a semiconductor device having a memory element with good retention characteristics can be provided. Also, a semiconductor device suitable for miniaturization can be provided. Also, a semiconductor device with a reduced circuit area can be provided. Further, a semiconductor device with a novel structure can be provided. Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Effects other than these are naturally apparent from the descriptions of the specification, drawings, claims, etc. From the descriptions of the specification, drawings, claims, etc.,
It is possible to extract effects other than these.

4A and 4B illustrate the atomic ratio of an oxide film according to one embodiment of the present invention; 4A and 4B illustrate the atomic ratio of an oxide film according to one embodiment of the present invention; The figure explaining an atomic number ratio. 4A and 4B illustrate the atomic ratio of an oxide film according to one embodiment of the present invention; FIG. 4 is a diagram illustrating an atomic ratio of a target according to one embodiment of the present invention; The figure explaining an atomic number ratio. 1A and 1B show a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; FIG. 4 is a diagram showing the analysis results of nc-OS by an X-ray diffraction apparatus; The figure which shows the electron diffraction pattern of nc-OS. FIG. 4 is a diagram for explaining a crystal of InGaZnO ₄ ; 4A and 4B illustrate band structures of part of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; FIG. 4 shows Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. FIG. 4 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS; FIG. 4 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS; FIG. 10 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of nc-OS; FIG. 10 is a diagram showing a Cs-corrected high-resolution cross-sectional TEM image of nc-OS; FIG. 3 is a diagram showing the pellet size and its frequency observed by Cs-corrected high-resolution cross-sectional TEM images of CAAC-OS and nc-OS. FIG. 11 shows the relationship between the atomic ratio of a target and the atomic ratio of an oxide semiconductor film; Schematic diagram for explaining a film formation model of an nc-OS, and a diagram showing a pellet. The schematic diagram explaining a film-forming apparatus. 4A and 4B are a block diagram and a circuit diagram illustrating a display device; FIG. 4 is a diagram of a display module according to an embodiment; 1 is a configuration example of an RF tag according to an embodiment; 4A and 4B illustrate an example of a transistor; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; 4A and 4B illustrate an example of a transistor according to one embodiment of the present invention; FIG. 10 is a top view illustrating one mode of a display device; 1A and 1B are cross-sectional views each illustrating one mode of a display device; 1A and 1B are cross-sectional views each illustrating one mode of a display device; A circuit diagram according to an embodiment. 1A and 1B illustrate an example of a semiconductor device according to one embodiment of the present invention; 4A and 4B illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention; 4A and 4B illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention; 4A and 4B illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention; 4A and 4B illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention; 4 shows XRD evaluation results of an oxide semiconductor film according to one embodiment of the present invention. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. Electron diffraction pattern of oxide semiconductor film. 4A and 4B are TDS analysis results of an oxide semiconductor film. The figure which shows the change of the crystal|crystallization by electron beam irradiation. An example of using the RF tag according to the embodiment. An electronic device according to an embodiment. 4A and 4B show film densities of oxide semiconductor films; 4A and 4B show etching rates of oxide semiconductor films; 4A and 4B show the amount of desorbed gas released from an oxide semiconductor film; 4A and 4B show hydrogen concentrations in oxide semiconductor films; 4A and 4B illustrate crystal sizes of oxide semiconductor films; 4A and 4B illustrate crystal sizes of oxide semiconductor films; 4A and 4B show CPM measurement results of an oxide semiconductor film; 4A and 4B show CPM measurement results of an oxide semiconductor film; 4A and 4B show CPM measurement results of an oxide semiconductor film; The figure which shows the Cs correction|amendment high resolution cross-sectional TEM image of a-like OS. 4A and 4B show hydrogen concentrations in oxide semiconductor films;

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the descriptions of the embodiments shown below.

In the configuration of the invention to be described below, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In each drawing described in this specification, the size, layer thickness, or region of each configuration is
May be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

Note that ordinal numbers such as “first” and “second” in this specification and the like are used to avoid confusion of constituent elements, and are not numerically limited.

In this specification, the term “parallel” refers to a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. again,"
"Substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Also, in this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

A transistor is a type of semiconductor element, and can achieve current or voltage amplification, switching operation for controlling conduction or non-conduction, and the like. A transistor in this specification is an IGFET (Insulated Gate Field Effect Trans
Itor) and thin film transistors (TFT: Thin Film Transistor
)including.

(Embodiment 1)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

Oxide semiconductor films are roughly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films.
The non-single-crystal oxide semiconductor film is CAAC-OS (C Axis Aligned Cry
(Stalline Oxide Semiconductor) film, polycrystalline oxide semiconductor film, microcrystalline oxide semiconductor film, amorphous oxide semiconductor film, and the like.

Single crystals may be formed by firing at high temperatures, for example, about 1000° C. or higher. Therefore, from an industrial point of view, a semiconductor device can be manufactured at a lower cost by using a non-single-crystal oxide semiconductor film that can be formed at a lower temperature, which is preferable.

The number of grain boundaries in the oxide semiconductor film is preferably as small as possible. By reducing grain boundaries, for example, carrier mobility can be increased. By manufacturing a transistor using an oxide semiconductor film with few grain boundaries, a transistor with high field-effect mobility can be realized in some cases. Although details will be described later, non-single-crystal oxide semiconductor films with few grain boundaries include, for example, an nc-OS film and a CAAC-OS film.

On the other hand, an oxide semiconductor film may have crystals with a spinel structure. When crystals with a spinel structure coexist in the CAAC-OS film and the nc-OS film, a distinct boundary (or grain boundary) may be formed. At the boundary, for example, carrier scattering may increase and carrier mobility may decrease. In addition, since the boundary is likely to serve as a migration path for impurities and tends to capture impurities, there is a concern that the impurity concentration of the oxide semiconductor film may increase. again,
When a conductive film is formed over an oxide semiconductor film, an element contained in the conductive film, such as a metal, might diffuse to the boundary between the spinel and another region. Therefore, it is more preferable that the oxide semiconductor film does not contain a spinel-type crystal structure or has a spinel-type crystal structure in a small amount.

Here, the oxide semiconductor is, for example, an oxide semiconductor containing indium. When the oxide semiconductor contains indium, for example, carrier mobility (electron mobility) increases. Further, the oxide semiconductor preferably contains the element M. Element M is preferably aluminum, gallium,
Yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. However, as the element M, there are cases where a plurality of the above elements may be combined. The element M is, for example, an element having high bonding energy with oxygen. For example, it is an element whose bonding energy with oxygen is higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Further, the oxide semiconductor preferably contains zinc. An oxide semiconductor containing zinc tends to crystallize in some cases. Here, an oxide containing indium, the element M, and zinc is referred to as an In--M--Zn oxide.

[Regarding atomic number ratio]
In the In—M—Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention, the ratio of the number of atoms of In:
M:Zn=x:y:z. Preferred ranges of x, y and z will be described with reference to FIGS. 1 and 2. FIG.

Here, the atomic number ratio of each element will be described with reference to FIG. FIG. 3 shows x, y, and z when the ratio of the number of atoms of the elements X, Y, and Z in the XYZ oxide film is x:y:z.
is a diagram showing the range of . Note that the atomic number ratio of oxygen is not shown in FIG. Also, FIG. 3 may be called an equilibrium diagram. FIGS. 3A and 3B show an equilateral triangle having vertices X, Y, and Z, and coordinates R (4:2:1) as an example of coordinates. Here each vertex represents an element X, Y and Z respectively. The value of each term in the atomic number ratio is higher when the coordinates are closer to each vertex and lower when the coordinates are further away. Also, as shown in FIG. 3A, the value of each term in the atomic number ratio is represented by the length of the perpendicular line from the coordinates to the opposite side of the vertex of the triangle. For example, element X is represented by the length of perpendicular 21 from the coordinates to the opposite side of vertex X, that is, side YZ. Therefore, the coordinate R shown in FIG. represents something. Also, let γ be the point where the straight line passing through the vertex X and the coordinate R intersects the side YZ. At this time, if the ratio of the length of the line segment Yγ and the length of the line segment γZ is Yγ:γZ, then Yγ:γZ=(number of atoms of element Z):(number of atoms of element Y).

Also, as shown in FIG. 3B, draw three straight lines that pass through the coordinate R and are parallel to the three sides of the triangle. At this time, x, y, and z can be expressed as shown in FIG. 3(B) using the intersections of the three straight lines and the three sides.

In FIG. 6, the dashed line indicates the range where x:y:z satisfies the following formula in the In--M--Zn oxide film.

x: y: z = (1-α): (1 + α): m (-1 ≤ α ≤ 1)

Here, FIG. 6 shows cases where m=1, 2, 3, 4, and 5. FIG.

As described in Non-Patent Document 1, in In-M-Zn oxide, InMO ₃ (Zn
O) It is known that a homologous phase (homologous series) represented by _m (m is a natural number) exists. Here, as an example, consider the case where the element M is Ga. The region indicated by the thick straight line in FIG. 6 can be a single-phase solid solution region when, for example, powders of In ₂ O ₃ , Ga ₂ O ₃ and ZnO are mixed and fired at 1350° C. is a known composition. The solid solution region is
It is known that as the value of m is increased, that is, as the proportion of zinc is increased, it becomes broader.

In _{addition ,} the coordinates _indicated by _square symbols in FIG. ,
It is known that the spinel type crystal structure is likely to be mixed in the composition. As shown in FIG. 6, the composition near ZnGa ₂ O ₄ , that is, when x, y and z have values close to (x, y, z)=(0, 2, 1), spinel crystals Non-Patent Document 1 describes that the structures are easily formed or mixed.

The In—M—Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, preferably has a high indium content. In the In—M—Zn oxide film, s orbitals of metal atoms mainly contribute to carrier conduction. Carrier mobility becomes higher. By manufacturing a transistor using such a film for a channel region, a transistor having high field-effect mobility, for example, can be realized. For example, preferably x/y>0.5,
x/y≧0.75 is more preferred, and x/y≧1 is even more preferred. Moreover, (x+y)≧z
is preferred.

Therefore, x, y, and z preferably have the ratio of the number of atoms in the region 11 shown in FIG. 1, and more preferably have the ratio of the number of atoms in the region 12 shown in FIG. 2(A). where region 11 is
A first coordinate K (x:y:z=8:14:7) and a second coordinate R (x:y:z=2:4:3)
), a third coordinate L (x:y:z=2:5:7), and a fourth coordinate M (x:y:z=51:
149:300), a fifth coordinate N (x:y:z=46:288:833), a sixth coordinate O (x:y:z=0:2:11), and a seventh coordinate P (x: y: z = 0: 0: 1), the eighth coordinate Q (x: y: z = 1: 0: 0), and the first coordinate K in order with a line segment It is within the connected area. Note that the region 11 includes line segments connecting the eight points. Also, the coordinates P and Q are excluded from the area 11, and the other coordinates are included in the area 11. FIG. Also, the region 12 is defined by the first coordinate K
(x: y: z = 8: 14: 7), a second coordinate R (x: y: z = 2: 4: 3), and a third coordinate L (x: y: z = 2: 5 :7), a fourth coordinate S (x:y:z=1:0:1), a fifth coordinate Q (x:y:z=1:0:0), and the first coordinate It is within the area where K and K are connected in order by line segments. Note that the area 12 includes a line segment connecting five points. Also, the coordinate Q is excluded from the region 12 and the other coordinates are included in the region 12 .

[Structure of oxide semiconductor film]
Next, the structure of the oxide semiconductor film is described.

First, the CAAC-OS film will be explained.

A CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Transmission electron microscope (TEM: Transmission Electron Micro
A plurality of crystal parts can be confirmed by observing a bright-field image of the CAAC-OS film and a combined analysis image of the diffraction pattern (also referred to as a high-resolution TEM image) using an oscopy. On the other hand, even with a high-resolution TEM image, a clear boundary between crystal parts, that is, a crystal grain boundary (also called a grain boundary) cannot be confirmed. Therefore, the CAAC-OS film is
It can be said that the decrease in electron mobility caused by the grain boundaries is less likely to occur.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting the unevenness of the surface on which the CAAC-OS film is formed (also referred to as the surface on which the CAAC-OS film is formed) or the upper surface, and is arranged in parallel with the surface on which the CAAC-OS film is formed or the upper surface. .

On the other hand, when a high-resolution TEM image of the plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

Note that when the CAAC-OS film is subjected to electron diffraction, spots (bright spots) indicating orientation are observed. For example, when the surface or top surface of the CAAC-OS film is subjected to electron diffraction using an electron beam of 1 nm or more and 30 nm or less (also referred to as nanobeam electron diffraction), spots are observed (FIG. 7B). reference.).

From the cross-sectional high-resolution TEM image and the planar high-resolution TEM image, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most of the crystal parts included in the CAAC-OS film have a size that fits within a cube with one side of less than 100 nm. Therefore, each side of the crystal part included in the CAAC-OS film is 10
A size that fits within a cube of less than nm, less than 5 nm, or less than 3 nm is also included. However, a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, a crystalline region of 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed in a planar high-resolution TEM image.

X-ray diffraction (XRD: X-Ray Diffraction) for the CAAC-OS film
Structural analysis using the apparatus revealed, for example, a CAAC-OS having InGaZnO ₄ crystals.
In the film analysis by the out-of-plane method, a peak may appear near the diffraction angle (2θ) of 31°. Since this peak is attributed to the (009) plane of the crystal of InGaZnO ₄ , the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or top surface. It can be confirmed that

On the other hand, the in-pl method in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis
In the analysis by the ane method, a peak may appear near 2θ of 56°. This peak is assigned to the (110) plane of the InGaZnO ₄ crystal. In the case of a single-crystal oxide semiconductor film of InGaZnO ₄ , 2θ is fixed around 56°, and analysis (φ scan) is performed while rotating the sample around the normal vector of the sample surface (φ axis). Six peaks attributed to crystal planes equivalent to the 110) plane are observed. On the other hand, in the case of the CAAC-OS film, 2θ is 5.
A clear peak does not appear even when φ scanning is performed with the angle fixed at around 6°.

From the above, in the CAAC-OS film, although the orientation of the a-axis and b-axis is irregular between different crystal parts, it has c-axis orientation and the c-axis is normal to the formation surface or the upper surface. It can be seen that the direction is parallel to the vector. Therefore, each layer of the metal atoms arranged in layers confirmed by the high-resolution TEM observation of the cross section is a plane parallel to the ab plane of the crystal.

Note that the crystal part is formed when the CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or top surface of the CAAC-OS film.

In addition, the distribution of c-axis oriented crystal parts may not be uniform in the CAAC-OS film. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the ratio of the c-axis oriented crystal parts in the area near the upper surface is higher than that in the area near the formation surface. can be higher. In addition, in the CAAC-OS film to which impurities are added, the regions to which the impurities are added may be degraded, and regions having different proportions of c-axis oriented crystal parts may be formed.

Note that the out-of-plane of the CAAC-OS film having InGaZnO ₄ crystals
In the analysis by the method, in addition to the peak near 31° 2θ, a peak may also appear near 36° 2θ. The peak near 36° of 2θ indicates that a portion of the CAAC-OS film contains crystals that do not have c-axis orientation. The CAAC-OS film preferably shows a peak near 31° in 2θ and does not show a peak near 36° in 2θ.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, an element such as silicon, which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor film, deprives the oxide semiconductor film of oxygen, thereby disturbing the atomic arrangement of the oxide semiconductor film and increasing the crystallinity. is a factor that lowers In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have large atomic radii (or molecular radii). is a factor that lowers Note that impurities contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

Further, for example, oxygen vacancies in the oxide semiconductor film may trap carriers or generate carriers by trapping hydrogen. A CAAC-OS film is an oxide semiconductor film with a low defect state density. Specifically, it is less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×
An oxide semiconductor with a carrier density of 10 ⁻⁹ /cm ³ or more can be used.

In addition, a transistor using a CAAC-OS film has little change in electrical characteristics due to irradiation with visible light or ultraviolet light.

Next, a polycrystalline oxide semiconductor film will be described.

Crystal grains can be found in a high-resolution TEM image of the polycrystalline oxide semiconductor film.
Crystal grains included in the polycrystalline oxide semiconductor film are, for example, 2 nm or more and 3 nm in a high-resolution TEM image.
The particle size is often 00 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less. In a high-resolution TEM image of the polycrystalline oxide semiconductor film, grain boundaries can be found in some cases.

A polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientation is different between the crystal grains in some cases. Further, when structural analysis is performed on the polycrystalline oxide semiconductor film using an XRD apparatus, the ou of the polycrystalline oxide semiconductor film having crystals of InGaZnO ₄ , for example, is found.
In the analysis by the t-of-plane method, a peak near 31° 2θ, a peak near 36° 2θ, or other peaks may appear.

A polycrystalline oxide semiconductor film has high crystallinity and thus may have high electron mobility. Therefore, a transistor including a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may segregate at grain boundaries. again,
A crystal grain boundary of the polycrystalline oxide semiconductor film becomes a defect level. In a polycrystalline oxide semiconductor film, grain boundaries may become a carrier trap or a carrier generation source; therefore, a transistor using a polycrystalline oxide semiconductor film has large fluctuations in electrical characteristics and is therefore unreliable. may become.

Next, a microcrystalline oxide semiconductor film is described.

In a high-resolution TEM image, a microcrystalline oxide semiconductor film has regions where crystal parts can be seen and regions where clear crystal parts cannot be seen. A crystal part included in a microcrystalline oxide semiconductor film often has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals with a size of 1 nm to 10 nm, or 1 nm to 3 nm, is
c-OS (nanocrystalline oxide semiconductor
) membrane. In addition, in the nc-OS film, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed.

The nc-OS film has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Further, in the nc-OS film, there is no regularity in crystal orientation between different crystal parts. Therefore, no orientation is observed in the entire film.
Therefore, the nc-OS film may be indistinguishable from the amorphous oxide semiconductor film depending on the analysis method. For example, for the nc-OS film, XRD using X-rays with a diameter larger than the crystal part
Structural analysis is performed using an apparatus, and in the out-of-plane analysis, a peak near 31° indicating a crystal plane is not detected (see FIG. 8). Further, when the nc-OS film is subjected to electron diffraction (also referred to as selected area electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part, a diffraction pattern like a halo pattern is observed. be done. On the other hand, when the nc-OS film is subjected to nanobeam electron diffraction using an electron beam with a probe diameter close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a circular (ring-like) region with high brightness may be observed. Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed within a ring-shaped region. For example, as shown in FIG. 9A, when nanobeam electron diffraction is performed with a probe diameter of 30 nm, 20 nm, 10 nm, or 1 nm for an nc-OS with a thickness of about 50 nm, a circle ( A region with high brightness is observed (like a ring). Further, it can be seen that a ring-shaped region is formed from a plurality of spots as the probe diameter is decreased.

For more detailed structural analysis, the nc-OS film is thinned to a thickness of several nanometers (about 5 nm), and a transmission electron diffraction pattern is obtained using an electron beam with a probe diameter of 1 nm. As a result, a transmission electron diffraction pattern having spots showing crystallinity shown in FIG. 9B was obtained.

Further, when nanobeam electron diffraction is performed on the nc-OS film, two ring-shaped regions may be observed.

The nc-OS film is an oxide semiconductor film with higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower defect level density than the amorphous oxide semiconductor film.

Further, in the nc-OS film, there is no regularity in crystal orientation between different crystal parts. for that reason,
The nc-OS film has a higher defect level density than the CAAC-OS film. Therefore, nc-O
The S film may have a higher carrier density than the CAAC-OS film. An oxide semiconductor film with high carrier density might have high electron mobility. Therefore, a transistor using an nc-OS film may have high field effect mobility.

The nc-OS film can be formed at a lower temperature than the CAAC-OS film. Also, nc-OS
In some cases, the film can be formed even when it is relatively doped. Therefore, n
A c-OS film may be easier to form than a CAAC-OS film. Therefore, nc-
A semiconductor device including a transistor including an OS film can be manufactured with high productivity in some cases.

In addition, the nc-OS film may have moderate oxygen permeability. When the film has moderate oxygen permeability, for example, oxygen released from the film containing excess oxygen easily diffuses throughout the nc-OS film. Therefore, oxygen vacancies can be easily reduced in the nc-OS film in some cases.

A low impurity concentration and a low defect level density (few oxygen vacancies) is called high-purity intrinsic or substantially high-purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film rarely has electrical characteristics such that the threshold voltage is negative (also referred to as normally-on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has little variation in electrical characteristics and is highly reliable. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave like a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states might have unstable electrical characteristics.

Next, an amorphous oxide semiconductor film will be described.

An amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and which does not have a crystal part. An example is an oxide semiconductor film having an amorphous state such as quartz.

A crystal part cannot be confirmed in a high-resolution TEM image of the amorphous oxide semiconductor film.

When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, out-of-
In the analysis by the plane method, no peaks indicating crystal planes are detected. In addition, a halo pattern is observed when the amorphous oxide semiconductor film is subjected to electron diffraction. Further, when the amorphous oxide semiconductor film is subjected to nanobeam electron diffraction, no spots are observed but a halo pattern is observed.

An amorphous oxide semiconductor film is an oxide semiconductor film containing impurities such as hydrogen at a high concentration.
An amorphous oxide semiconductor film is an oxide semiconductor film with a high density of defect states.

An oxide semiconductor film with a high impurity concentration and a high defect level density has many carrier traps and many carrier generation sources.

Therefore, the amorphous oxide semiconductor film may have a higher carrier density than the nc-OS film. Therefore, a transistor including an amorphous oxide semiconductor film tends to have normally-on electrical characteristics. Therefore, in some cases, it can be suitably used for a transistor that requires normally-on electrical characteristics. Since the amorphous oxide semiconductor film has a high density of defect states, the number of carrier traps may increase. Therefore, a transistor including an amorphous oxide semiconductor film has a lower cost than a transistor including a CAAC-OS film or an nc-OS film.
The transistor has a large variation in electric characteristics and a low reliability.

Next, a single crystal oxide semiconductor film is described.

A single crystal oxide semiconductor film is an oxide semiconductor film with a low impurity concentration and a low density of defect states (few oxygen vacancies). Therefore, carrier density can be lowered. Therefore, a transistor including a single crystal oxide semiconductor film rarely has normally-on electrical characteristics. Further, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, the number of carrier traps may be reduced. Therefore, a transistor including a single crystal oxide semiconductor film has little variation in electrical characteristics and is highly reliable.

Note that the oxide semiconductor film has a high density when there are few defects. Further, the oxide semiconductor film is
The higher the crystallinity, the higher the density. In addition, the oxide semiconductor film has a high density when the concentration of impurities such as hydrogen is low. A single-crystal oxide semiconductor film has a higher density than a CAAC-OS film. Further, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. A polycrystalline oxide semiconductor film has a higher density than a microcrystalline oxide semiconductor film. In addition, a microcrystalline oxide semiconductor film has a higher density than an amorphous oxide semiconductor film.

Note that the oxide semiconductor film may have a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor.
: a-like OS) film.

In the a-like OS film, voids may be observed in a high-resolution TEM image. In addition, in the high-resolution TEM image, there are regions where crystal parts can be clearly confirmed and regions where crystal parts cannot be confirmed. The a-like OS film may be crystallized by irradiation of a very small amount of electrons, which can be observed with a TEM, and the growth of a crystal part may be observed. On the other hand, if the nc-OS film is of good quality, almost no crystallization due to irradiation of a very small amount of electrons, which can be observed by TEM, is observed.

Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, an InGaZnO ₄ crystal has a layered structure, with two Ga--Zn--O layers between In--O layers. The unit cell of the crystal of InGaZnO ₄ has a structure in which nine In--O layers and six Ga--Zn--O layers are layered in the c-axis direction. Therefore, the spacing between these adjacent layers is approximately the same as the lattice spacing (also referred to as the d value) of the (009) plane, and the value is 0.29 n from crystal structure analysis.
m is required. Therefore, focusing on the lattice fringes in the high-resolution TEM image, each lattice fringe is In
It was assumed to correspond to the ab plane of the GaZnO ₄ crystal. The maximum length in the region where the lattice fringes are observed is taken as the size of the crystal part of the a-like OS film and the nc-OS film. In addition, the size of the crystal part is selectively evaluated when it is 0.8 nm or more.

In addition, since it has voids, the a-like OS has a lower density structure than the nc-OS and CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.

In some cases, single crystals having the same composition do not exist. In that case, by combining single crystals with different compositions at an arbitrary ratio, the density corresponding to a single crystal with a desired composition can be estimated. The density corresponding to a single crystal with a desired composition can be estimated using a weighted average of the ratio of single crystals with different compositions combined. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

[Nanobeam electron diffraction]
Next, nanobeam electron diffraction will be described.

When an oxide semiconductor film has multiple structures, structural analysis may be possible by using nanobeam electron diffraction.

FIG. 7C shows an electron gun chamber 610, an optical system 612 under the electron gun chamber 610, and an optical system 61
2, an optical system 616 below the sample room 614, an observation room 620 below the optical system 616, a camera 618 installed in the observation room 620, and a film room below the observation room 620. 622 and a transmission electron diffraction measurement apparatus. A camera 618 is installed facing the inside of the observation room 620 . Note that the film chamber 622 may not be provided.

Further, FIG. 7(D) shows the internal structure of the transmission electron diffraction measurement apparatus shown in FIG. 7(C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun installed in an electron gun chamber 610 are irradiated via an optical system 612 onto a substance 628 arranged in a sample chamber 614 . Substance 628
The electrons passing through enter the fluorescent screen 632 installed inside the observation room 620 via the optical system 616 . A transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of incident electrons on the fluorescent screen 632 .

The camera 618 is installed facing the fluorescent screen 632 and is capable of photographing the pattern appearing on the fluorescent screen 632 . The angle between the straight line passing through the center of the lens of the camera 618 and the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15° or more and 80° or less, 30° or more and 75° or less, or 45° or more and 70°. Below. The smaller the angle, the more distorted the transmission electron diffraction pattern captured by camera 618 . However, if the angle is known in advance, it is possible to correct the distortion of the obtained transmission electron diffraction pattern. Note that the camera 618 may be installed in the film chamber 622 in some cases. For example, camera 618 may be placed in film chamber 622 opposite the direction of incidence of electrons 624 . In this case, a less distorted transmission electron diffraction pattern can be photographed from the rear surface of the fluorescent screen 632 .

A holder for fixing a substance 628 as a sample is installed in the sample chamber 614 .
The holder is constructed to be transparent to electrons passing through material 628 . The holder may, for example, have the ability to move the substance 628 in the X-axis, Y-axis, Z-axis, and the like. The moving function of the holder only needs to have an accuracy of moving within a range of, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm. These ranges may be optimized depending on the structure of the substance 628 .

Next, a method for measuring a transmission electron diffraction pattern of a substance using the transmission electron diffraction measurement apparatus described above will be described.

For example, as shown in FIG. 7D, by changing (scanning) the irradiation position of electrons 624, which are nanobeams, on the substance, it is possible to confirm how the structure of the substance changes. At this time, if the substance 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 7B is observed. Alternatively, if the substance 628 is an nc-OS film, a diffraction pattern such as that shown in FIG. diffraction pattern) is observed. Also, the diffraction pattern shown in FIG. 7A has bright spots that are not symmetrically arranged (has no symmetry).

As shown in FIG. 7B, in the diffraction pattern of the CAAC-OS film, for example, spots located at the vertexes of hexagons are confirmed. In the CAAC-OS film, by scanning the irradiation position, the direction of the hexagons is not uniform, and it can be seen that they rotate little by little. Also, the angle of rotation has a certain width.

Alternatively, in the diffraction pattern of the CAAC-OS film, by scanning the irradiation position,
It can be seen that it rotates about the c-axis little by little. It can be said that the plane formed by, for example, the a-axis and the b-axis is rotating.

By the way, the substance 628 has a region where a diffraction pattern similar to that of the CAAC-OS film is observed (hereinafter referred to as a region having a CAAC structure) and a region where a diffraction pattern similar to that of the nc-OS film is observed (hereinafter referred to as an nc structure). ). Here, the CAAC ratio (
It is also called CAAC ratio. ). Similarly, the ratio of regions where a diffraction pattern similar to that of the nc-OS film is observed can be expressed as an nc ratio (also referred to as an nc conversion ratio).

A method for evaluating the CAAC ratio of the CAAC-OS film will be described below. Measurement points are selected at random, a transmission electron diffraction pattern is acquired, and the ratio of the number of measurement points where the diffraction pattern of the CAAC-OS film is observed to the total number of measurement points is calculated. Here, the number of measurement points is preferably 50 or more, more preferably 100 or more.

As a method of randomly selecting measurement points, for example, the irradiation position may be linearly scanned, and a diffraction pattern may be obtained at regular time intervals. CAAC by scanning the irradiation position
This is preferable because a boundary between a region having a structure and other regions can be confirmed. In addition, nc
Similarly, the conversion rate can be calculated by selecting measurement points at random and obtaining a transmission electron diffraction pattern.

By using such a measurement method, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.

In the oxide semiconductor film which is one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is 80%, for example.
It is preferably 90% or more, preferably 90% or more and 100% or less, preferably 95% or more and 100% or less, preferably 98% or more and 100% or less.
It is more preferably 9% or more and 100% or less. By increasing the sum of the nc ratio and the CAAC ratio, for example, an oxide semiconductor film with fewer distinct grain boundaries can be achieved. By reducing distinct grain boundaries, for example, carrier mobility of the oxide semiconductor film can be increased.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 2)
In this embodiment, an example of an oxide semiconductor film which is one embodiment of the present invention will be described.

The nc-OS film can sometimes be formed even at a relatively low film formation temperature compared to the CAAC-OS film. For example, it may be formed without heating the substrate. Therefore, a semiconductor device including a transistor including an nc-OS film can be manufactured with high productivity in some cases.

In addition, since the nc-OS film has moderate oxygen permeability, oxygen can easily diffuse throughout the film, and oxygen vacancies can be reduced more easily in some cases. Therefore, an oxide semiconductor film with a low defect density can be realized in some cases. Therefore, in some cases, the characteristics of a semiconductor device including a transistor using an nc-OS film can be improved. In addition, reliability can be improved in some cases.

Here, both the nc-OS film and the CAAC-OS film have atomic arrangements in which layers are stacked. Such a layered atomic arrangement can be observed using, for example, a TEM.

Here, for the nc-OS film and the CAAC film, spherical aberration correction (Spherical
Transmission electron microscopy (TEM:
An image (also referred to as a TEM image) obtained by Transmission Electron Microscopy is observed. A composite analysis image of a bright-field image and a diffraction pattern obtained by TEM observation is called a high-resolution TEM image. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. In addition, Cs-corrected high-resolution TEM
Acquisition of the image, for example, atomic resolution analysis electron microscope JEM-ARM20 manufactured by JEOL Ltd.
It can be done by 0F or the like.

In CAAC-OS and nc-OS, the crystal size and orientation will be investigated by analyzing Cs-corrected high-resolution cross-sectional TEM images in more detail. Hereinafter, the crystal part of the nc-OS may be called a pellet. The size and orientation of crystals are determined by extracting pellets of, for example, a range of 20 nm square or more in a cross-sectional TEM image, and examining their size and orientation.

FIG. 17A is a Cs-corrected high-resolution cross-sectional TEM image of CAAC-OS. FIG. 17B is a Cs-corrected high-resolution cross-sectional TEM image of nc-OS. The left and right figures are observations of the same place, and the right figure has an auxiliary line indicating the pellet.

FIG. 18A is a cross-sectional TEM image of CAAC-OS deposited by a DC sputtering method. Further, FIG. 18B is a Cs-corrected high-resolution cross-sectional TEM image in which a part thereof is enlarged.
In FIG. 18(B), the number of pellets was counted and their sizes and orientations were given a frequency distribution (see FIG. 22(A)). Here, the arrows shown in FIG. 18A indicate directions perpendicular to the sample surface. The direction of the white line shown in FIG. 18(B) indicates the direction of the pellet, and the length of the white line indicates the size of the pellet.

FIG. 19A is a cross-sectional TEM image of CAAC-OS deposited by an RF sputtering method. FIG. 19B is a partially enlarged Cs-corrected high-resolution cross-sectional TEM image.
In FIG. 19(B), the number of pellets was counted, and the size and orientation were made into a frequency distribution (see FIG. 22(B)).

FIG. 20A is a cross-sectional TEM image of an nc-OS deposited by a DC sputtering method.
FIG. 20B is a partially enlarged Cs-corrected high-resolution cross-sectional TEM image. Figure 2
At 0(B), the number of pellets was counted and their sizes and orientations were frequency-distributed (see FIG. 22(C)).

FIG. 21A is a cross-sectional TEM image of an nc-OS deposited by an RF sputtering method.
FIG. 21B is a partially enlarged Cs-corrected high-resolution cross-sectional TEM image. Figure 2
In 1(B), the number of pellets was counted and the size and orientation of the pellets were frequency-distributed (see FIG. 22(D)).

The table below summarizes the results of FIG. Here, the orientation of the pellet indicates the absolute value of the angle with respect to the sample plane.

The nc-OS preferably has pellets with a size of, for example, preferably 0.5 nm or more and 3 nm or less, more preferably 1 nm or more and 3 nm or less. Also, in nc-OS,
It can be seen that the orientation of the pellets in the RF sputtering method is more perpendicular to the sample surface than in the DC sputtering method. Here, the ratio of the nc-OS pellet orientation with respect to the sample surface of 0° or more and less than 30° is preferably 0% or more and 70% or less, and the ratio of 30° or more and less than 60° is, for example, 10. % or more and 60% or less, and the ratio of 60° or more and less than 90° is preferably 0% or more and 60% or less, for example. nc-OS stands for CAAC-OS
It can be seen that the orientation of the pellets is random compared to .

An oxide semiconductor film having such pellets can be described by, for example, the following deposition model.

[Deposition model]
A film formation model of the nc-OS will be described below.

FIG. 24 is a schematic diagram of the inside of the film forming chamber showing how the nc-OS is formed by the sputtering method.

A target 5130 is glued onto the backing plate. target 5130
And under the backing plate, a plurality of magnets are arranged. A magnetic field is generated on the target 5130 by the plurality of magnets. A sputtering method that uses the magnetic field of a magnet to increase the deposition rate is called a magnetron sputtering method.

Target 5130 has a polycrystalline structure, and any crystal grain includes a cleaved plane.
Details of the cleavage plane will be described later.

The substrate 5120 is arranged to face the target 5130, and the distance d (
It is also called target-substrate distance (TS distance). ) is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less. In the deposition chamber, most of the deposition gas (for example,
oxygen, argon, or a mixed gas containing 50% by volume or more of oxygen);
The pressure is controlled to 01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. Here, by applying a voltage above a certain level to the target 5130, discharge is started and plasma is confirmed. Note that the magnetic field above target 5130 forms a high-density plasma region. In the high-density plasma region, ions 5101 are generated by ionizing the deposition gas. The ions 5101 are, for example, positive ions of oxygen (O ⁺ ) and positive ions of argon (Ar
⁺ ) and so on.

The ions 5101 are accelerated toward the target 5130 by the electric field and eventually collide with the target 5130 . At this time, pellets 5100a and 5100b, which are flat plate-like or pellet-like sputtered particles, are peeled off from the cleaved surface and beaten out. Structural distortion may occur in the pellets 5100a and 5100b due to the impact of the ion 5101 collision.

The pellet 5100a is a plate-like or pellet-like sputtered particle having a triangular plane, for example, an equilateral triangular plane. The pellet 5100b is a plate-like or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane. Flat plate-like or pellet-like sputtered particles such as the pellets 5100a and 5100b are collectively referred to as pellets. The planar shape of the pellets is not limited to triangles and hexagons.
In some cases, the shape may be a combination of 1 or more and 6 or less. For example, it may be a quadrilateral formed by combining two equilateral triangles.

The thickness of the pellet is determined according to the type of film forming gas. It is preferable to make the thickness of the pellet uniform. Further, it is preferable that the sputtered particles are in the form of pellets with no thickness, rather than in the form of dice with thickness.

The pellets may become negatively or positively charged on the sides by receiving a charge as they pass through the plasma. The pellet has oxygen atoms on its sides, which can be negatively charged.

As shown in FIG. 24, for example, the pellet flies in the plasma like a kite and flutters up onto the substrate 5120 . Because the pellets carry an electric charge, a repulsive force is generated when approaching an area where other pellets are already deposited. Here, a magnetic field parallel to the upper surface of the substrate 5120 is generated on the upper surface of the substrate 5120 . In addition, since a potential difference is applied between the substrate 5120 and the target 5130, the voltage from the substrate 5120 to the target 5130 is increased.
Current is flowing towards 130 . Therefore, the pellet experiences a force (Lorentz force) on the upper surface of the substrate 5120 due to the action of the magnetic field and current. In order to increase the force applied to the pellet, the magnetic field parallel to the top surface of the substrate 5120 should be 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably 50 G or more. It is preferable to provide an area where Alternatively, on the upper surface of the substrate 5120, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than the magnetic field in the direction perpendicular to the upper surface of the substrate 5120, More preferably, a region that is five times or more should be provided.

It is considered that the pellets are deposited on the substrate 5120 according to the above model.
Therefore, unlike epitaxial growth, it can be seen that the nc-OS can be deposited even when the formation surface does not have a crystal structure. For example, the nc-OS can be deposited even if the structure of the top surface (formation surface) of the substrate 5120 is an amorphous structure.

Since the nc-OS is formed according to such a model, it is preferable that the sputtered particles are in the form of thin pellets. When the sputtered particles are thick and dice-shaped,
In some cases, the surface of the sputtered particles directed onto the substrate 5120 is not constant, and the thickness and crystal orientation cannot be made uniform.

Further, when the substrate 5120 is heated, the resistance such as friction between the pellet and the substrate 5120 is reduced. As a result, the pellet glides over the top surface of the substrate 5120 . Movement of the pellet occurs with the flat side of the pellet facing the substrate 5120 . After that, when the side surfaces of the already deposited pellet 5100 are reached, the side surfaces are joined together to obtain a CAAC-OS film.

When the substrate 5120 is not heated, there is more resistance, such as friction, between the pellet and the substrate 5120 . As a result, it is difficult for the pellets to glide over the upper surface of the substrate 5120, and the nc-OS can be obtained by accumulating irregularly.

The CAAC-OS heats the substrate 5120 to form a film, whereas the nc-OS heats the substrate 5120 to form a film.
It is possible to form a film without heating 20 .

Also, as shown in FIG. 25, for example, the atmosphere in the chamber is preferably 500°C above room temperature.
C. or less, more preferably 200.degree. C. or higher and 400.degree. C. or lower. A lamp 5140 such as a halogen lamp may be used for heating the atmosphere. Heating the atmosphere heats pellets flying in the chamber, for example, and can reduce defects. Also, the pellet size may increase. In addition, the heating of the atmosphere makes it easier for moisture in the chamber to evaporate, and the degree of vacuum can be further increased.

[Cleavage plane]
The cleavage plane of the target described in the nc-OS film formation model will be described below.

First, the cleavage plane of the target will be explained with reference to FIG. InGaZ in FIG.
The structure of the crystal of nO ₄ is shown. Note that FIG. 10A shows the structure of an InGaZnO ₄ crystal observed from a direction parallel to the b-axis with the c-axis directed upward. Moreover, FIG. 10(B) shows c
The structure of an InGaZnO ₄ crystal observed from the direction parallel to the axis is shown.

The energy required for cleavage on each crystal plane of the InGaZnO ₄ crystal is calculated by first-principles calculation. A density functional program (CASTEP) using a pseudopotential and a plane wave basis is used for the calculation. As the pseudopotential, an ultrasoft pseudopotential is used. Moreover, GGA PBE is used for the functional. Also, the cutoff energy is assumed to be 400 eV.

The energy of the structure in the initial state is derived after optimizing the structure including the cell size. Also, the energy of the structure after cleavage on each plane is derived after structural optimization of the atomic arrangement with the cell size fixed.

Based on the crystal structure of InGaZnO ₄ shown in FIG. 10, a structure was cleaved on any of the first, second, third, and fourth faces, and the cell size was fixed. Then, the structural optimization calculation is performed. Here, the first plane is a crystal plane between the Ga--Zn--O layer and the In--O layer, (
001) plane (or ab plane) (see FIG. 10A). The second plane is the crystal plane between the Ga--Zn--O layers and the (001) plane (or a
b plane) (see FIG. 10A). The third plane is a crystal plane parallel to the (110) plane (see FIG. 10B). The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (see FIG. 10B).

Under the above conditions, the energy of the structure after cleavage is calculated for each plane. Next, the difference between the energy of the structure after cleavage and the energy of the structure in the initial state is divided by the area of the cleavage plane to calculate the cleavage energy, which is a measure of the easiness of cleavage on each plane. The energy of the structure is the energy in consideration of the kinetic energy of electrons and interactions between atoms, between atoms and electrons, and between electrons, with respect to atoms and electrons included in the structure.

As a result of calculation, the cleavage energy of the first plane is 2.60 J/m ² , the cleavage energy of the second plane is 0.68 J/m 2 , the cleavage energy of the third plane is 2.18 J/m ² , and the cleavage energy of the third plane is 2.18 J/m ² . The cleavage energy of the plane of 4 was found to be 2.12 J/m ² (see table below).

According to this calculation, in the InGaZnO ₄ crystal structure shown in FIG. 10, the cleavage energy in the second plane is the lowest. That is, it can be seen that the interface between the Ga--Zn--O layers and the Ga--Zn--O layer is the most easily cleaved plane (cleavage plane). Therefore, in this specification, the term "cleavage plane" refers to the second plane, which is the most easily cleaved plane.

The crystal of InGaZnO ₄ shown in FIG. 10(A) is equivalent to two second planes because it has a cleavage plane on the second plane between the Ga—Zn—O layer and the Ga—Zn—O layer. can be separated in terms of Therefore, when the target is bombarded with ions or the like, wafer-like units cleaved on the plane with the lowest cleavage energy (we call them pellets) are thought to come out as the smallest units. In that case, the InGaZnO ₄ pellet has three layers of a Ga--Zn--O layer, an In--O layer and a Ga--Zn--O layer.

In addition, the third plane (a crystal plane that is a crystal plane between the Ga—Zn—O layer and the In—O layer and is parallel to the (001) plane (or ab plane)) is preferred over the first plane ( 110) plane) and the fourth plane (crystal plane parallel to the (100) plane (or bc plane)) have low cleavage energies, so the planar shape of the pellet is often triangular or hexagonal. is suggested.

[Film density]
Next, the density of the In--M--Zn oxide film was evaluated. In:Ga:Zn as a target
= 1:1:1 polycrystalline In-Ga-Zn oxide was used, and nc-
An OS was deposited. The pressure is 0.4 Pa, the film formation temperature is room temperature, the power supply is 100 W, and argon and oxygen are used as film formation gases.
sccm. The density of the obtained In--Ga--Zn oxide was 6.1 g/cm ³ . Here, according to Non-Patent Document 2, the density of single crystal InGaZnO ₄ is 6.357 g/cm ³
is. In addition, JCPDS card, No. 00-038-1097, the density of single crystal In ₂ Ga ₂ ZnO ₇ is known to be 6.494 g/cm ³ . Therefore, it is found that the obtained nc-OS film is an excellent film having a high density.

The density of the In-M-Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, is preferably 85% or more, more preferably 90% or more, of the density of a single crystal having approximately the same atomic ratio, for example. More preferably 95% or more.

Alternatively, when the element M is gallium, the density of the oxide semiconductor film of one embodiment of the present invention is
For example, 5.7 g/cm ³ or more and 6.49 g/cm ³ or less is preferable, 5.75 g/cm ³ or more and 6.49 g/cm ³ or less is preferable, and 5.8 g/cm ³ or more and 6.33 g/cm ³ or less is preferable. It is more preferably 5.85 g/cm ³ or more and 6.33 g/cm ³ or less.

Here, the substantially same atomic number ratio means that the difference between the atomic number ratios they have is within 10%, for example.

Here, for example, the density of a single crystal is two or more In-M-Zn having different atomic ratios.
It may be estimated from the density of the oxide film. Here, D ₁ is the density of a single crystal with an atomic ratio of In:M:Zn=1:1:1, and D is the density of a single crystal with an atomic ratio of In:M:Zn=2:2:1. ₂ . In-M- in which the atomic ratio of indium, element M and zinc is 1:1:0.8
The density of Zn oxide films is expected to take values between _D1 and _D2 . Therefore, as the density of the single crystal, for example, the average value of D ₁ and D ₂ may be calculated and referred to, or the value of either D ₁ or D ₂ , such as the closer atomic ratio, may be referred to. good. When calculating the average using D ₁ and D ₂ , for example, 0.6×D ₁ +0.4×D ₂ may be used. The atomic number ratio is In:M:Z
Let D _α be the density of a single crystal with n=A:B:C, and D _β be the density of a single crystal with an atomic ratio of In:M:Zn=D:E:F. The density of a single crystal with an atomic ratio of In:M:Zn=X:Y:Z may be calculated, for example, as follows.

First, (αA + βD): (αB + βE): (αC + βF) = X: Y: Z
and β. Next, using the obtained α and β, the density of the single crystal is {α / (α + β)} D _α
+{β/(α+β)}D _β may be calculated.

Next, an example of a method for manufacturing an nc-OS film is described.

General methods for forming an oxide semiconductor film include, for example, a sputtering method, a chemical vapor deposition (CVD) method (a metal organic chemical deposition (MOCVD) method, an atomic layer deposition (ALD) method, or a plasma chemical vapor deposition (ALD) method. vapor phase deposition (PECVD) method), vacuum deposition method or pulsed laser deposition (PLD) method.

The nc-OS film is preferably formed using a sputtering method. In--M--Zn oxide can be used as a target for the sputtering method.

Also, the target preferably comprises polycrystalline In--M--Zn oxide. For example, it is more preferable to use a target containing a polycrystalline In--M--Zn oxide because the target has cleavability and may facilitate formation of the nc-OS film.

In--M--Zn oxide may be produced using a mixture of indium oxide, an oxide having the element M, and zinc oxide as targets, but a target with polycrystalline In--M--Zn oxide is preferred. It is preferable to use

In addition, the nc-OS film can be formed at about room temperature in some cases, which is preferable. For example, it can be formed without heating the substrate in some cases, which is preferable. Further, for example, the atmosphere in the chamber may be heated to preferably room temperature or higher and 500° C. or lower, more preferably 200° C. or higher and 400° C. or lower.

[Regarding atomic number ratio]
Here, for example, an In--M--Zn oxide film is preferably used as the oxide semiconductor film which is one embodiment of the present invention. The atomic number ratio of In, M and Zn in the In-M-Zn oxide is defined as I
Let n:M:Zn=x:y:z.

An In--M--Zn oxide film, which is an oxide semiconductor film of one embodiment of the present invention, preferably has an increased proportion of indium, for example.

Further, the number of grain boundaries in the oxide semiconductor film is preferably as small as possible. Examples of non-single-crystal oxide semiconductor films with few grain boundaries include an nc-OS film and a CAAC-OS film. Further, the oxide semiconductor film may include both an nc-OS film and a CAAC-OS film.

Further, when the oxide semiconductor film of one embodiment of the present invention is subjected to nanobeam electron diffraction,
It preferably has a region (nc structure) where the diffraction pattern of the nc-OS film is observed. Further, the oxide semiconductor film which is one embodiment of the present invention includes a region where the diffraction pattern of the nc-OS film is observed and a region where the diffraction pattern of the CAAC-OS film is observed (CAAC structure). may

Further, the oxide semiconductor film which is one embodiment of the present invention preferably has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. Further, in the oxide semiconductor film which is one embodiment of the present invention, the sum of the nc ratio and the CAAC ratio is preferably 80% or more, preferably 90% or more and 100% or less.
It is preferably 5% or more and 100% or less, preferably 98% or more and 100% or less, and more preferably 99% or more and 100% or less.

A plurality of films may be stacked as the oxide semiconductor film which is one embodiment of the present invention. Also, the respective nc ratios and CAAC ratios of the plurality of films may be different. Moreover, it is preferable that at least one layer of the laminated films has a high nc ratio. For example, the nc ratio is preferably 30% or more, preferably 50% or more, and more preferably 80% or more. In addition, at least one of the laminated films preferably has a sum of the nc ratio and the CAAC ratio of 80% or more, preferably 90% or more and 100% or less, and 95% or more and 1
00% or less, preferably 98% or more and 100% or less, 99%
% or more and 100% or less.

As shown in FIG. 6, powders of In ₂ O ₃ , Ga ₂ O ₃ and ZnO are mixed and 1350
Non-Patent Document 1 describes that the solid solution region is widened by increasing the proportion of zinc in the case of firing at .degree. Here, the CAAC ratio of the oxide semiconductor film of one embodiment of the present invention may be increased by setting the atomic ratio of the In—Ga—Zn oxide to a range in which a solid solution region can be obtained. Therefore, by reducing the zinc ratio, the nc ratio of the oxide semiconductor film of one embodiment of the present invention can be increased in some cases. The atomic ratio of indium, element M, and zinc in the oxide semiconductor film is set to indium:element M:zinc=x:y:z. For example, increasing the ratio of x+y to z, ie, (x+y)/z, may result in a higher nc ratio. Specifically, for example, (x+y)>z is preferable, and (x+
y)≧1.5z, preferably (x+y)≧2z.

In addition, by mixing crystals with a spinel structure with the CAAC-OS film and the nc-OS film,
A distinct grain boundary or boundary may be formed. Therefore, it is preferable to keep away from the atomic number ratio that facilitates the formation of crystals with a spinel structure.

Therefore, In—M—Zn oxide film which is an oxide semiconductor film of one embodiment of the present invention contains In
, the atomic number ratios x, y and z of the element M and zinc preferably have the atomic number ratio in the region 13 shown in FIG. 4(A), and the atomic number ratio in the region 14 shown in FIG. It is more preferable to have Here, the area 13 has a first coordinate K (x:y:z=8:14:7) and a second coordinate R
(x: y: z = 2: 4: 3), a third coordinate V (x: y: z = 1: 2: 3), and a fourth coordinate S (x: y: z = 1: 0 : 1), fifth coordinates T (x:y:z=8:0:1), and sixth
and the first coordinate K are connected by line segments in order. Note that the region 13 includes line segments connecting the six points. Also, the area 13 contains all the coordinates. Also, the area 14 has a first coordinate K (x:y:z=8:14:7), a second coordinate R (x:y:z=2:4:3), and a third coordinate V (x: y: z = 1: 2: 3), a fourth coordinate W (x: y: z = 7: 1: 8), and a fifth coordinate X (x: y: z = 7: 1:1), the sixth coordinate U (x:y:z=6:2:1), and the first coordinate K are connected in order by line segments. Note that the region 14 includes line segments connecting the six points. Also, the area 14 contains all the coordinates.

Further, when an oxide semiconductor film is formed by a sputtering method, the atomic ratio of the obtained film is
It may deviate from the target atomic number ratio. Especially for zinc, the ratio of zinc in the resulting film may be smaller than the ratio of zinc in the target. Specifically, the ratio of zinc in the obtained film may be, for example, approximately 40 atomic % or more and 90 atomic % or less of the ratio of zinc in the target.

Here, when forming an In--Ga--Zn oxide film by a sputtering method, the relationship between the atomic ratio of the target used and the atomic ratio of the resulting film was investigated.

As film formation conditions, argon and oxygen were used as film formation gases, and the oxygen flow ratio was 33%. Here, the oxygen flow ratio is an amount represented by oxygen flow rate/(oxygen flow rate+argon flow rate)×100[%]. Further, the pressure was in the range of 0.4 Pa to 0.7 Pa, the substrate temperature was 200° C. to 300° C., and the power was 0.5 kW (DC).

FIG. 23 shows the relationship between the value of the atomic number ratio and the zinc residual ratio when focusing on two elements of the target. The numbers in the figure represent the atomic ratio of In:Ga:Zn in the target. Here, the zinc residual rate will be explained. A value obtained by dividing the value of the zinc term in the obtained atomic ratio of the film by the sum of the values of the terms of indium, gallium and zinc in the film is defined as Zn(Film). Zn(Target) is obtained by dividing the value of the zinc term in the atomic number ratio of the target by the sum of the values of the terms of indium, gallium, and zinc of the target. Here, the zinc residual rate is defined as a value represented by A=Zn(Film)÷Zn(Target)×100[%].

In addition, the atomic ratio of indium, gallium, and zinc in the In--Ga--Zn oxide target to be used is expressed as a:b:c.

In FIG. 23(A), the horizontal axis represents the ratio of zinc to gallium of the target (c/b), and the
In 3(B), the horizontal axis represents the ratio of gallium to indium in the target (b/a
), and the horizontal axis of FIG. 23(C) shows the ratio (c/a) of zinc to indium of the target. In addition, each vertical axis indicates the zinc residual ratio A.

Here, from FIG. 23, the zinc residual rate of the film obtained by the sputtering method is approximately 5%.
It can be seen that it is 0% or more and 90% or less. Also, it can be said that indium and gallium do not change greatly from the atomic number ratio of the target compared to zinc. Further, when the ratio of zinc to gallium in the target (c/b) is 1, for example, the zinc residual ratio A is about 66%,
In the case of 2, it is about 74%, and in the case of 3, it is about 83%.

Further, from FIG. 23A, it can be seen that there is a good correlation between the ratio of zinc to gallium in the target (c/b) and the zinc residual ratio. That is, the smaller the amount of zinc relative to the amount of gallium, the lower the residual rate.

In view of the above, in order to obtain the oxide semiconductor film in the region 13 illustrated in FIG. is preferably 1.7 times or more, more preferably 1.5 times or more. Therefore, the target indium, gallium and zinc preferably have the atomic ratio of region 15 shown in FIG. Here, the area 15 has a first coordinate K (a:b:c=8:14:7) and a second coordinate R (a
:b:c=2:4:3), the third coordinate Y (a:b:c=1:2:5.1), and the fourth coordinate Z (a:b:c=1:0 : 1.7), a fifth coordinate T (a:b:c=8:0:1),
It is within an area in which the sixth coordinate U (a:b:c=6:2:1) and the first coordinate K are connected in order by line segments. Note that the region 15 includes line segments connecting the six points. Area 15 contains all the coordinates.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 3)
In this embodiment, an example of a transistor including an oxide semiconductor film which is one embodiment of the present invention will be described.

[Transistor example 1]
An example of a transistor including an oxide semiconductor film is described with reference to FIGS.

FIG. 12A shows a top view of the transistor 100. FIG. Moreover, FIG. 12(B) is the
), and FIG. 12C shows a cross section along the dashed line YY'. 12 includes a substrate 50, an insulating film 51 in contact with the top surface of the substrate 50, an insulating film 114 in contact with the top surface of the insulating film 51, a semiconductor layer 101 in contact with the top surface of the insulating film 114, and a conductive layer 104a. and a conductive layer 104b, a gate insulating film 102 over the semiconductor layer 101, a gate electrode 103 overlapping with the semiconductor layer 101 with the gate insulating film 102 interposed therebetween,
have An insulating film 112 and an insulating film 113 are provided to cover the transistor 100 . Also, the transistor 100 may include a conductive layer 105 . Further, an insulating film may not be provided between the substrate 50 and the insulating film 114 .

The semiconductor layer 101 may be formed with a single layer, or preferably has a stacked-layer structure of first to third layers. A second layer is provided on and in contact with the first, and a third layer is provided on and in contact with the second layer. Here, in the transistor of one embodiment of the present invention, the first layer and the third layer each have a region through which current is less likely to flow than the second layer. Therefore, the first layer and the third layer may be called insulator layers. Therefore, as in the example shown in FIG. 12, the semiconductor layer 101
is preferably formed with a stacked structure of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c. Alternatively, a structure that does not include either the insulator layer 101a or the insulator layer 101c may be employed. In the example shown in FIG. 12, the semiconductor layer 101b is the insulator layer 101
touches the upper surface of a. The conductive layers 104a and 104b are in contact with the top surface of the semiconductor layer 101b and separated from each other in a region overlapping with the semiconductor layer 101b. Also, the insulator layer 101c is in contact with the upper surface of the semiconductor layer 101b. Also, the gate insulating film 102 is in contact with the upper surface of the insulator layer 101c. In addition, the gate electrode 103 overlaps the semiconductor layer 101b with the gate insulating film 102 and the insulator layer 101c interposed therebetween.

An insulating film 112 and an insulating film 113 are provided to cover the transistor 100 .
The insulating film 112 and the insulating film 113 will be described in detail in embodiments described later.

The conductive layers 104a and 104b function as source and drain electrodes. Alternatively, a voltage lower or higher than that of the source electrode may be applied to the conductive layer 105 to change the threshold voltage of the transistor in the positive or negative direction. By changing the threshold voltage of a transistor in the positive direction, a normally-off state, in which the transistor is in a non-conducting state (off state) even when the gate voltage is 0 V, can be realized in some cases. Note that the voltage applied to the conductive layer 105 may be variable or fixed. When the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage may be connected to the conductive layer 105 . Also, the conductive layer 105 may be connected to the gate electrode 103 .

The upper surface of the insulating film 114 is subjected to CMP (Chemical Mechanical Politics).
It is preferably planarized by a planarization treatment using a hing method or the like.

The insulating film 114 preferably contains oxide. In particular, it preferably contains an oxide material from which part of oxygen is released by heating. Preferably, an oxide containing more oxygen than the stoichiometric composition is used. Part of the oxygen is released from the oxide film that contains more oxygen than the stoichiometric composition by heating. Oxygen released from the insulating film 114 is supplied to the semiconductor layer 101 which is an oxide semiconductor, so that oxygen vacancies in the oxide semiconductor can be reduced. As a result, variation in electrical characteristics of the transistor can be suppressed and reliability can be improved.

An oxide film containing more oxygen than the stoichiometric composition is, for example, a thermal desorption spectroscopy (TDS analysis) in which the amount of oxygen desorbed in terms of oxygen atoms is 1.0×10 ¹
It is an oxide film having a density of ⁸ atoms/cm ³ or more, preferably 3.0×10 ²⁰ atoms/cm ³ or more. The surface temperature of the film during the TDS analysis is 100° C. or higher.
00° C. or lower, or a range of 100° C. or higher and 500° C. or lower is preferable.

For example, it is preferable to use a material containing silicon oxide or silicon oxynitride as such a material. Alternatively, metal oxides can also be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon oxynitride refers to a material whose composition contains more nitrogen than oxygen. indicates

In order to cause the insulating film 114 to contain excessive oxygen, oxygen may be introduced into the insulating film 114 to form a region containing excessive oxygen. For example, oxygen (including at least oxygen radicals, oxygen atoms, or oxygen ions) is introduced into the insulating film 114 after deposition to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

The semiconductor layer 101 contains an oxide semiconductor. A semiconductor material having a wider bandgap and a lower carrier density than silicon is preferably used as an oxide semiconductor because current in the off state of the transistor can be reduced. In addition, since the semiconductor layer 101 contains an oxide semiconductor, variation in electrical characteristics is suppressed, and a highly reliable transistor can be realized.

Here, for the semiconductor layer 101, the oxide semiconductor described in Embodiment 1 or 2 can be used, for example.

Note that the term “substantially intrinsic” in this specification and the like means that the carrier density of the oxide semiconductor layer is less than 1×10 ¹⁷ /cm ³ , less than 1×10 ¹⁵ /cm ³ , or 1×10 ¹³ /cm ^{3 .}
is less than By using a highly purified intrinsic oxide semiconductor layer, the transistor can have stable electrical characteristics.

Here, a case where a laminated film of an insulator layer 101a, a semiconductor layer 101b, and an insulator layer 101c is used as the semiconductor layer 101 will be described in detail. For the semiconductor layer 101b, an oxide having higher electron affinity than the insulator layers 101a and 101c is preferably used. For example, the semiconductor layer 101b has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.1 eV or less than those of the insulator layers 101a and 101c. A large oxide of 4 eV or less is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

By using an oxide having a higher electron affinity than the insulator layers 101a and 101c as the semiconductor layer 101b, when an electric field is applied to the gate electrode, the insulator layers 101a,
Of the semiconductor layer 101b and the insulator layer 101c, a channel is formed in the semiconductor layer 101b having a high electron affinity. Here, by forming a channel in the semiconductor layer 101b, for example, the channel forming region is separated from the interface with the gate insulating film 102, so that the influence of scattering at the interface with the gate insulating film can be reduced. Therefore, the field effect mobility of the transistor can be increased. As will be described later, the semiconductor layer 101b and the insulator layer 101c have the same constituent elements, so interface scattering hardly occurs.

Further, when a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, or the like is used for the gate insulating film, silicon contained in the gate insulating film might enter the oxide semiconductor film. When silicon is contained in the oxide semiconductor film, the crystallinity of the oxide semiconductor film may be lowered, the carrier mobility may be lowered, and the like. Therefore, in order to reduce the impurity concentration of the semiconductor layer 101b in which the channel is formed, for example, the silicon concentration, the semiconductor layer 10
An insulator layer 101c is preferably provided between 1b and the gate insulating film. For the same reason, it is preferable to provide the insulator layer 101a between the semiconductor layer 101b and the insulating film 114 in order to reduce the influence of impurity diffusion from the insulating film 114. FIG.

As the semiconductor layer 101b, an oxide semiconductor film containing indium, the element M, and zinc may be used, for example. For example, the oxide semiconductor film described in Embodiment 1 or 2 is preferably used.

For the semiconductor layer 101b, for example, an oxide with a large energy gap is used. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV to 4.2 eV, preferably 2.7 eV to 3.7 eV, more preferably 2.8 eV to 3.3 eV.

Next, the insulator layer 101a and the insulator layer 101c will be described. For example, insulator layer 1
01a and the insulator layer 101c contain at least one element other than oxygen constituting the semiconductor layer 101b;
Alternatively, it is an oxide composed of two or more kinds. Since the insulator layer 101a and the insulator layer 101c are composed of one or more or two or more elements other than oxygen that constitute the semiconductor layer 101b, the interface between the insulator layer 101a and the semiconductor layer 101b and the semiconductor layer 101b insulator layer 1
At the interface with 01c, an interface level is difficult to form.

FIG. 11 shows the band structure. FIG. 11 shows the vacuum level (vacuum le
Notated as vel. ), the energy at the bottom of the conduction band (represented by Ec) and the energy at the top of the valence band (represented by Ev) of each layer.

Here, there may be a mixed region of the insulator layer 101a and the semiconductor layer 101b between the insulator layer 101a and the semiconductor layer 101b. In addition, the semiconductor layer 101b and the insulator layer 101
c, there may be a mixed region of the semiconductor layer 101b and the insulator layer 101c.
The mixed region has a low interface state density. Therefore, the insulator layer 101a and the semiconductor layer 101b
and the insulator layer 101c has a band structure in which the energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface.

At this time, the electrons are not in the insulator layers 101a and 101c, but in the semiconductor layer 1
It mainly moves in 01b. As described above, insulator layer 101a and semiconductor layer 101b
By reducing the interface state density at the interface between the semiconductor layer 101b and the insulator layer 101c, the movement of electrons in the semiconductor layer 101b is less hindered, and the on-current of the transistor is reduced. can be raised.

In addition, although FIG. 11 shows the case where Ec of the insulating layer 101a and the insulating layer 101c are the same, they may be different. For example, Ec of the insulator layer 101c may have higher energy than that of the insulator layer 101a.

As shown in FIG. 12B, the side surface of the semiconductor layer 101b includes the conductive layer 104a and the conductive layer 1
04b. Further, as shown in FIG. 12C, the electric field of the gate electrode 103 causes
The semiconductor layer 101b can be electrically surrounded (the structure of a transistor in which the semiconductor is electrically surrounded by an electric field of a conductor is called a surrounded channel (sc
channel) structure. ). When the gate electrode 103 is provided to face the upper surface and side surfaces of the semiconductor layer 101b, a channel may be formed not only in the vicinity of the upper surface of the semiconductor layer 101b but also in the entire (bulk) of the semiconductor layer 101b. In the s-channel structure, a large current can flow between the source and the drain of the transistor, and the current (on-current) during conduction can be increased.

Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since a transistor can be miniaturized, a semiconductor device including the transistor can have a high degree of integration and high density. for example,
The transistor has a region with a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor has a channel width of preferably 40 nm or less, more preferably 30 nm or less, more preferably It has a region of 20 nm or less. In particular, the smaller the channel width, the wider the region where the channel is formed to the inside of the semiconductor layer 101b.

In--M--Zn oxide, for example, can be used for the insulator layers 101a and 101c.

Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Thus, for example, insulator layer 101c may include indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

Insulator layer 101c more preferably contains gallium oxide. insulator layer 101
When c contains gallium oxide, a lower off current can be achieved in some cases.

An nc-OS film or a CAAC-OS film is preferably used for the insulator layers 101a and 101c. Here, the nc ratio of the insulator layer 101a and the insulator layer 101c, the CA
A higher AC ratio can result in fewer defects, for example. In addition, for example, a region having spinel crystals can be reduced. Also, for example, carrier scattering can be reduced. Also, for example, a film having a high blocking ability against impurities can be used. In addition, it is possible to suppress the entry of impurities into the semiconductor layer 101b and reduce the impurity concentration of the semiconductor layer 101b.

The nc ratio of the insulator layer 101a and the insulator layer 101c is preferably 10% or more, for example.
30% or more is preferable, 50% or more is preferable, 80% or more is preferable, 90% or more is preferable, 95% or more is preferable.

Here, the insulator layer 101a, the semiconductor layer 101b, and the insulator layer 101c are made of In--M--Zn.
Consider the case of an oxide. Let x _a , ya, and _za be the atomic ratios of In, M, and _Zn in the insulator layer 101a. Similarly, In, elements M, and Zn included in the semiconductor layer 101b
Let x _b , y _b and z _b be the atomic number ratios of . Similarly, let _xc , _yc , and _zc be the atomic ratios of In, M, and Zn in the insulator layer 101c. Preferred values for each are described below.

x _b , y _b and z _b are regions 11, 12 and 13 shown in FIGS.
and region 14.

It is preferable that the insulator layer 101a and the insulator layer 101c have no or little spinel crystal structure. Thus, x _a : y _a : _za and x _c : y _c : z _c are for example
is within the range of the region 11 and the electron affinity is smaller than that of the semiconductor layer 101b.

Here, in order to make the electron affinity of the semiconductor layer 101b higher than those of the insulator layers 101a and 101c, for example, it is preferable that the indium content of the semiconductor layer 101b is higher than those of the insulator layers 101a and 101c. .

For example, _{xb /} ( _xb + _yb + _zb )> _xa /(xa+ _ya + _za ), and _xb /(x
_b + _yb + _zb )> _xc /( _xc + _yc + _zc ) is preferably satisfied.

For example, preferably x _a /(x _a +y _a )<0.5, more preferably x _a /(x
_a + y _a )<0.33, more preferably x _a /(x _a +y _a )<0.25. In addition, preferably x _b /(x _b +y _b )≧0.25, more preferably x _b /(
x _b +y _b )≧0.34. In addition, preferably x _c /(x _c +y _c )<0.5, more preferably x _c /(x _c +y _c )<0.33, still more preferably x _c /(x _c
+y _c )<0.25.

Alternatively, x _a , y _a , _za , and x _c , y _c , z _c preferably have the ratio of the number of atoms in region 16 shown in FIG. 2(B). Here the area 16 is defined by the first coordinates K (x:y:z=8:
14:7), a second coordinate R (x:y:z=2:4:3) and a third coordinate L (x:y:z
=2:5:7), the fourth coordinate M (x:y:z=51:149:300), the fifth coordinate B (x:y:z=1:4:10), and the 6 coordinates C (x:y:z=1:1:4) and the seventh
and the first coordinate K are connected by line segments in order. Note that the area 16 contains all the coordinates.

Note that when a transistor has an s-channel structure, a channel is formed over the entire semiconductor layer 101b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, the thicker the semiconductor layer 101b, the higher the on-current of the transistor. For example, the semiconductor layer 101b may have a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more. However, since the productivity of the semiconductor device may decrease, the semiconductor layer 101b may have a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less, for example.

In addition, the thickness of the insulator layer 101c is preferably as small as possible in order to increase the on-state current of the transistor. For example, less than 10 nm, preferably 5 nm or less, more preferably 3 nm
The insulator layer 101c having the following regions may be used. On the other hand, the insulator layer 101c supplies elements other than oxygen (hydrogen,
It has a function to block the entry of silicon, etc.). Therefore, insulator layer 10
1c preferably has a certain thickness. For example, the insulator layer 101c may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more. Insulator layer 101c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from gate insulating film 102 and the like.

In order to improve reliability, it is preferable that the insulator layer 101a is thick and the insulator layer 101c is thin. For example, 10 nm or more, preferably 20 nm or more, more preferably 4
The insulator layer 101a may have a region with a thickness of 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulator layer 101a, the adjacent insulator and the insulator layer 101a
The distance from the interface with a to the semiconductor layer 101b in which the channel is formed can be increased.
However, since the productivity of the semiconductor device may decrease, for example, the insulator layer 1 having a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less
01a.

When a large amount of hydrogen or moisture is contained in the oxide semiconductor film, a donor level due to hydrogen may be formed. The formation of the donor level may shift the threshold of the transistor in the negative direction. Therefore, dehydration treatment (dehydrogenation treatment) is preferably performed after the oxide semiconductor film is formed to remove hydrogen or moisture so that the oxide semiconductor film is highly purified so as to contain impurities as little as possible.

Note that the dehydration treatment (dehydrogenation treatment) on the oxide semiconductor film may also reduce oxygen at the same time. Therefore, after dehydration treatment, oxygen is preferably supplied to fill oxygen vacancies in the oxide semiconductor film. In this specification and the like, supplying oxygen to an oxide semiconductor film is sometimes referred to as oxygenation treatment. Alternatively, making the proportion of oxygen contained in the oxide semiconductor film higher than the stoichiometric composition may be referred to as peroxygenation treatment.

In this way, by removing hydrogen or moisture by dehydration treatment and by supplementing oxygen vacancies by oxygenation treatment, i-type (intrinsic) or substantially i-type
A type (intrinsic) oxide semiconductor film can be realized. Note that the term “substantially intrinsic” means that the number of donor-derived carriers in the oxide semiconductor film is extremely small (close to zero) and the carrier density is 1×10 ¹⁷ /cm ³ or less, 1×10 ¹⁶ /cm ³ or less, 1×10 ¹⁵ /cm ³ or less, 1×10 ¹⁴ /cm ³ or less, or 1×10 ¹³ /cm ³ or less.

A transistor including an i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current. For example, the off-state current of a transistor including an oxide semiconductor film is 1×10 ⁻¹⁸ A or less, preferably 1×10 ⁻²¹ A or less, more preferably 1×10 ⁻²⁴ A at room temperature (about 25° C.). or less, or 1×10 ⁻¹⁵ A or less at 85° C., preferably 1×10 ⁻¹⁸ A or less, more preferably 1×10 ⁻²¹ A or less. Here, off current refers to drain current when the transistor is in an off state. In addition, in the case of an n-channel transistor, the off state of the transistor means a state in which the gate voltage is sufficiently lower than the threshold. Specifically, when the gate voltage is 1 V or more, 2 V or more, or 3 V or more less than the threshold value, the transistor is turned off.

One of the conductive layers 104a and 104b functions as a source electrode and the other functions as a drain electrode.

The conductive layers 104a and 104b each have a single-layer structure or a stacked-layer structure of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these metals as a main component. used as for example,
A single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, and a copper film is laminated on a copper-magnesium-aluminum alloy film Two-layer structure, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and aluminum on the titanium film or titanium nitride film A three-layer structure in which a film or a copper film is laminated and a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or a copper film is laminated on the molybdenum film or the molybdenum nitride film. There is a three-layer structure in which a molybdenum film or a molybdenum nitride film is formed thereon.
Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

The gate insulating film 102 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn-based metal oxide, silicon nitride, or the like may be used, and a stacked layer or a single layer is provided.

As the gate insulating film 102, hafnium silicate ( _HfSiOx ) _, nitrogen-added _{hafnium silicate} (HfSixOyNz ₎ , nitrogen- _added hafnium aluminate (HfAlxOyNz ₎ , yttrium oxide A high-k material, such as, may be used.

As the gate insulating film 102, an oxide insulating film such as aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a mixture thereof.

As the gate insulating film 102, an oxide insulating film containing more oxygen than the stoichiometric composition is preferably used, similarly to the insulating film 114. FIG.

If a specific material is used for the gate insulating film, electrons can be trapped in the gate insulating film under specific conditions, and the threshold voltage can be shifted in the positive direction. For example, materials with many electron capture levels, such as hafnium oxide, aluminum oxide, and tantalum oxide, are used for part of the gate insulating film, such as a laminated film of silicon oxide and hafnium oxide, and the use of semiconductor devices at higher temperatures is possible. A state in which the potential of the gate electrode is higher than the potential of the source electrode or the drain electrode at a temperature higher than the storage temperature, or 125° C. or higher and 450° C. or lower, typically 150° C. or higher and 300° C. or lower By maintaining for 1 second or longer, typically 1 minute or longer, electrons move from the semiconductor layer toward the gate electrode, some of which are trapped in electron trap levels.

The gate electrode 103 is formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten, an alloy containing any of the above metals, or an alloy combining any of the above metals. can be done. Alternatively, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide such as nickel silicide may be used. Further, the gate electrode 103 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, and a two-layer structure in which a tungsten film is stacked over a titanium nitride film. a layer structure, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is laminated, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon, and the like. be. Also, for aluminum,
An alloy film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined, or a nitride film may be used.

The gate electrode 103 is formed of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a layered structure of the light-transmitting conductive material and the metal can be used.

Further, between the gate electrode 103 and the gate insulating film 102, an In--Ga--Zn-based oxynitride semiconductor film, an In--Sn-based oxynitride semiconductor film, an In--Ga-based oxynitride semiconductor film, and an In--Zn-based Oxynitride semiconductor films, Sn-based oxynitride semiconductor films, In-based oxynitride semiconductor films, metal nitride films (I
nN, ZnN, etc.) may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, which is higher than the electron affinity of an oxide semiconductor; A switching element with a so-called normally-off characteristic can be realized. For example, when using an In--Ga--Zn-based oxynitride semiconductor film, the In--Ga--Zn-based oxynitride semiconductor film is used with a nitrogen concentration higher than that of the semiconductor layer 101, specifically 7 atomic % or more.

The above is the description of the transistor 100 .

Note that the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion of the semiconductor where current flows when the transistor is on) overlaps with a gate electrode, or a region in which a channel is formed. , source (source region or source electrode)
and the drain (drain region or drain electrode). Note that channel lengths in one transistor do not always have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of the semiconductor where current flows when the transistor is on) overlaps with a gate electrode, or a region where a channel is formed, where the source and the drain face each other. It means the length of the part where Note that the channel width does not always have the same value in all regions of one transistor. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as the effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as the apparent channel width ) and may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may become larger than the apparent channel width shown in the top view of the transistor, and its effect cannot be ignored. For example, in a transistor having a fine three-dimensional structure, the proportion of the channel region formed on the side surface of the semiconductor may be greater than the proportion of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width if the shape of the semiconductor is not accurately known.

Therefore, in this specification, in a top view of a transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, is referred to as the "surrounding channel width (SCW : Surrounded Channel
Width)”. In addition, in this specification, simply referring to the channel width may refer to the enclosing channel width or the apparent channel width. Alternatively, in this specification, simply referring to the channel width may refer to the effective channel width.
The channel length, channel width, effective channel width, apparent channel width, enclosing channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. can.

Note that when the field-effect mobility of a transistor, the current value per channel width, and the like are calculated, they are sometimes calculated using the enclosed channel width. In that case, it may take a different value than when calculating using the effective channel width.

[Transistor example 2]
An example of a structure of a transistor including an oxide semiconductor film which is one embodiment of the present invention, which is different from that in FIG. 12, will be described with reference to FIGS. 13A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 13B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 13A. FIG. 13(C) corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 shown in FIG. 13(A).

In the transistor 100, the gate electrode 203a functioning as a gate electrode over the substrate 50, the gate insulating film 202 over the substrate 50 and the gate electrode 203a, the semiconductor layer 201 over the gate insulating film 202, and the semiconductor layer 201 are electrically connected. It has a conductive layer 204a and a conductive layer 204b functioning as a connected source electrode and a drain electrode. Moreover, the transistor 100
An insulating film 21 is formed on the conductive layer 204 a , the conductive layer 204 b and the semiconductor layer 201 , more specifically, on the conductive layer 204 a , the conductive layer 204 b and the semiconductor layer 201 .
4. An insulating film 216 and an insulating film 218 are laminated in order.

Next, components included in the transistor of this embodiment are described.

For the gate electrode 203a functioning as the gate electrode of the transistor 100, the description of the gate electrode 103 can be referred to.

For the gate insulating film 202 functioning as the gate insulating film of the transistor 100, the description of the gate insulating film 102 can be referred to. Alternatively, a laminated film having two or more layers may be used as the gate insulating film 202 . For example, as shown in FIG. 13, a two-layer structure of a gate insulating film 202a and a gate insulating film 202b may be employed. In that case, for example, the lower layer, here the gate insulating film 20
A film having a function as a blocking film that suppresses permeation of oxygen may be used for 2a. As a film functioning as a blocking film, for example, a barrier film 111 or the like, which will be described later, may be referred to.

As the semiconductor layer 201, the oxide semiconductor film described in Embodiment 1 or 2 may be used. For the semiconductor layer 201, the description of the semiconductor layer 101 may be referred to. Alternatively, the semiconductor layer 201 may be a laminated film of two or more layers.

The insulating films 214 , 216 , and 218 function as protective insulating films of the transistor 100 . The insulating film 214 also functions as a damage mitigation film to the semiconductor layer 201 when the insulating film 216 is formed.

The insulating film 214 and the insulating film 216 preferably have a region containing oxygen in excess of the stoichiometric composition (oxygen excess region), for example, like the insulating film 114 described above.

In addition ^, the insulating film 214 preferably has a small amount of defects. It is preferably ³ or less. If the density of defects included in the insulating film 214 is high, oxygen is bound to the defects, and the amount of oxygen permeation through the insulating film 214 is reduced.

In addition, in the insulating film 214 , all of the oxygen entering the insulating film 214 from the outside
Some oxygen remains in the insulating film 214 without moving to the outside of 4 . Further, when oxygen enters the insulating film 214 and oxygen contained in the insulating film 214 moves to the outside of the insulating film 214 , oxygen may move in the insulating film 214 . When an oxide insulating film which can transmit oxygen is formed as the insulating film 214 , oxygen released from the insulating film 216 provided over the insulating film 214 is transferred to the semiconductor layer 201 through the insulating film 214 . can be done.

In addition, the insulating film 214 has the energy (E _{v — os} ) at the upper end of the valence band of the oxide semiconductor film.
can be formed using an oxide insulating film in which the level density of nitrogen oxide is low between the energy (E _{c — os} ) at the bottom of the conduction band and the energy (E c — os ) at the bottom of the conduction band. As the oxide insulating film with a low level density of nitrogen oxides between _{Ev_os} and _{Ec_os} , a silicon oxynitride film which releases a small amount of nitrogen oxides, an aluminum oxynitride film which releases a small amount of nitrogen oxides, or the like can be used.

Note that a silicon oxynitride film that releases a small amount of nitrogen oxides is a film that releases a larger amount of ammonia molecules than nitrogen oxides in the temperature-programmed desorption spectrometry. The emission amount is 1×10 ¹⁸ pieces/cm ³ or more and 5×10 ¹⁹ pieces/cm ³ or less. The release amount of ammonia molecules is determined when the surface temperature of the film is 50° C. or more and 650° C. or less, preferably 5° C. or less.
It is the amount released by heat treatment at 0°C or higher and 550°C or lower.

Nitrogen oxides (NO _x , where x is greater than 0 and less than or equal to 2, preferably from 1 to 2), typically NO ₂ or NO, form levels in the insulating film 214 and the like. The level of the semiconductor layer 20
located within the energy gap of 1. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 214 and the semiconductor layer 201, the level may trap electrons on the insulating film 214 side. As a result, the trapped electrons remain near the interface between the insulating film 214 and the semiconductor layer 201, which shifts the threshold voltage of the transistor in the positive direction.

Nitrogen oxides also react with ammonia and oxygen during heat treatment. Insulating film 214
nitrogen oxides contained in the insulating film 214 react with ammonia contained in the insulating film 216 in the heat treatment, so nitrogen oxides contained in the insulating film 214 are reduced. Therefore, electrons are less likely to be trapped at the interface between the insulating film 214 and the semiconductor layer 201 .

Note that the insulating film 214 has a function of protecting the back channel region of the semiconductor layer 201 by being in contact with the semiconductor layer 201 on the opposite side of the region where the channel is formed (hereinafter referred to as the back channel region). have

By using an oxide insulating film in which the level density of nitrogen oxide is low between _{Ev_os} and _{Ec_os} as the insulating film 214, shift of the threshold voltage of the transistor can be reduced. Fluctuations in electrical properties can be reduced.

In addition, an oxide insulating film having a low level density of nitrogen oxides between _{Ev_os} and _{Ec_os} has S
A nitrogen concentration measured by IMS is 6×10 ²⁰ atoms/cm ³ or less.

In addition, the insulating film 216 preferably has a small amount of defects ^. less than 1×10 18 spins/cm ³ or even less than 1×10 ¹⁸ spins/cm ³
The following are preferable. Note that the insulating film 216 is closer to the semiconductor layer 2 than the insulating film 214 .
01, the defect density may be higher than that of the insulating film 214 .

Alternatively, the transistor 100 may have the structure shown in FIGS. Here, the transistor 100 illustrated in FIG. 13 is a channel-etched transistor, but the transistor 100 illustrated in FIGS. 14 and 15 is a channel-protected transistor.

14A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 14B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 14A. FIG. 14(C) corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 14(A). A transistor 100 illustrated in FIG. 14 includes a gate electrode 203a provided over a substrate 50, a gate insulating film 202 formed over the substrate 50 and the gate electrode 203a, and a semiconductor layer overlapping with the gate electrode 203a with the gate insulating film 202 interposed therebetween. Layer 201 , insulating film 214 on gate insulating film 202 and semiconductor layer 201 , insulating film 216 on insulating film 214 , insulating film 214 and semiconductor layer 20 in openings 141 a and 141 b of insulating film 216 .
It has a pair of conductive layers 204a and 204b which are in contact with each other. Also, the transistor 1
An insulating film 218 may be provided over 00, more specifically, over the conductive layers 204 a , 204 b , and the insulating film 216 .

15A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 15B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 15A. FIG. 15(C) corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 shown in FIG. 15(A). The transistor 100 shown in FIG. 15 corresponds to the transistor 10 shown in FIG.
0 and the insulating films 214 and 216 are different. Specifically, the transistor 1 shown in FIG.
00 insulating films 214 and 216 are provided in an island shape on the channel region of the semiconductor layer 101 .
Other configurations are similar to those of the transistor 100 shown in FIG. 14, and similar effects can be obtained.

14 and 15, the semiconductor layer 201 is covered with the insulating film 214 and the insulating film 216 when the pair of conductive layers 204a and 204b are formed. And the semiconductor layer 201 is not damaged by the etching for forming the conductive layer 204b. Further, when the insulating films 214 and 216 are oxide insulating films containing nitrogen and having a small number of defects, variation in electrical characteristics is suppressed, and a transistor with improved reliability can be manufactured. can.

Further, the transistor 100 may have an electrode 203b over the insulating film 218 as shown in FIG. 16A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention, and FIG. 16B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG. 16A. FIG. 16(C) corresponds to a cross-sectional view taken along the dashed-dotted line Y1-Y2 shown in FIG. 16(A). In FIG. 16, the electrode 203b is connected to the insulating film 214 and the insulating film 2
Although the structure in which the gate electrode 203a is connected to the gate electrode 203a through the opening 142c and the opening 142d provided in 16 is shown, a structure in which the electrode 203b and the gate electrode 203a are not connected may be employed.
When the electrode 203b and the gate electrode 203a are not connected, different potentials can be applied to the respective electrodes.

As shown in FIG. 16, in the channel width direction, the side surface of the semiconductor layer 201 and the electrode 203b
In addition, in the channel width direction, the gate electrode 203a and the electrode 203b surround the semiconductor layer 201 via the gate insulating film 202 and the insulating film 214, and the insulating film 216 and the insulating film 218. Carriers flow in the semiconductor layer 201 not only at the interface between the gate insulating film 202 and the insulating film 214 and the semiconductor layer 201, but also at the interface between the semiconductor layer 201 and the semiconductor layer 201.
1 also flows, the amount of carrier movement in the transistor 100 increases. As a result, the ON current of the transistor 100 increases and the field effect mobility increases. In addition, since the electric field of the electrode 203b affects the side surface of the semiconductor layer 201 or the edge including the side surface and its vicinity, the occurrence of parasitic channels at the side surface or the edge of the semiconductor layer 201 can be suppressed.

Further, in FIG. 16, as an example of the semiconductor layer 201, a semiconductor layer 201b is formed on the semiconductor layer 201a.
shows a configuration for stacking Here, for example, in the semiconductor layer 201b, the energy at the bottom of the conduction band is closer to the vacuum level than the semiconductor layer 201a. The difference from the lower end energy is 0.05 eV
0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less,
It is 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the semiconductor layer 201b and the electron affinity of the semiconductor layer 201a is 0.05 eV or more and 0.07 eV.
V or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.
5 eV or less, or 0.4 eV or less.

The semiconductor layer 101b described in Embodiment 3 may be referred to as the semiconductor layer 201a. For example, the preferred range of the atomic ratio of indium, the element M, and zinc in the semiconductor layer 101b may be referred to. Further, the insulator layer 1 described in Embodiment 3 is used as the semiconductor layer 201b.
01c. For example, a preferred range of atomic ratios of indium, the element M, and zinc in the insulator layer 101c may be referred to.

[Transistor modification]
Modifications of the transistor 100 are shown in FIGS. 30 to 33. FIG. For example, the transistor 100 may have the structure shown in FIG. FIG. 30 differs from FIG. 12 in the shapes of the conductive layers 104a and 104b. Note that FIG. 30(B) passes through the dashed dotted line AB shown in FIG. 30(A),
A cross-section of a plane perpendicular to 0(A) is shown.

Alternatively, the transistor 100 may have the structure shown in FIG. In FIG. 12, insulator layer 101
c touches the upper surfaces of the conductive layers 104a and 104b, whereas in FIG.
04a and the lower surfaces of the conductive layer 104b. Note that FIG. 31(B) shows a cross section of a plane perpendicular to FIG. 31(A) through the dashed-dotted line AB shown in FIG. 31(A). With such a structure, the films forming the insulating layer 101a, the semiconductor layer 101b, and the insulating layer 101c can be formed continuously without being exposed to the atmosphere. , the respective interface defects can be reduced.

Alternatively, the transistor 100 may have the structure shown in FIG. Note that FIG. 32(B) shows a cross section of a plane perpendicular to FIG. 32(A) through the dashed-dotted line AB shown in FIG. 32(A). Figure 32
is different from FIG. 12 in that it does not have the conductive layer 104a and the conductive layer 104b. Figure 32
As shown in (C), the transistor 100 may include a low-resistance layer 171a and a low-resistance layer 171b. The low-resistance layers 171a and 171b preferably function as source and drain regions. Impurities may be added to the low-resistance layers 171a and 171b. By adding impurities, the resistance of the semiconductor layer 101 can be lowered. Impurities to be added include, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium,
It is preferable to add one or more selected from zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum and tungsten. In the low-resistance layers 171a and 171b, for example, the above impurity element is added to the semiconductor layer 101 at a concentration of 5×10 ¹⁹ atoms/cm ³ or more, preferably 1×10 ²⁰ atoms/cm.
m ³ or more, more preferably 2×10 ²⁰ atoms/cm ³ or more, more preferably 5×
It is a region containing 10 ²⁰ atoms/cm ³ or more. FIG. 32(D) is an enlarged view of region 324 in FIG. 32(C).

In some cases, impurities such as unnecessary hydrogen can be trapped in such a low-resistance region. By trapping unnecessary hydrogen in the low-resistance layer, the hydrogen concentration in the channel region can be lowered, and favorable characteristics of the transistor 100 can be obtained.

Alternatively, the transistor 100 may have the structure shown in FIG. FIG. 33 shows the insulator layer 101
c and the shape of the gate insulating film 102 are different from those in FIG. Note that FIG. 33(B) is the same as FIG.
33A is a cross section of a plane perpendicular to FIG.

In addition, in the structures shown in FIGS. 30 to 33, the insulator layer 101 is in contact with the semiconductor layer 101b.
a and the insulator layer 101c have been described, but the insulator layer 101a or the insulator layer 1
01c or both may be omitted.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 4)
In this embodiment, an example of a display device including the transistors described in the above embodiments will be described below with reference to FIGS.

FIG. 34 is a top view showing an example of a display device. A display device 700 shown in FIG. 34 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, the pixel portion 702, a source a sealing material 712 arranged to surround the driver circuit portion 704 and the gate driver circuit portion 706;
and a second substrate 705 provided to face the first substrate 701 . Note that the first substrate 701 and the second substrate 705 are sealed with a sealing material 712 . That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are
It is sealed with a first substrate 701 , a sealing material 712 and a second substrate 705 . note that,
Although not shown in FIG. 34, a display element is provided between the first substrate 701 and the second substrate 705 .

In the display device 700, a pixel portion 702, a source driver circuit portion 704, a gate driver circuit portion 706, and a gate driver circuit portion are provided in a region different from the region surrounded by the sealant 712 over the first substrate 701. FPC terminal portion 708 electrically connected to 706
(FPC: Flexible printed circuit) is provided. again,
An FPC 716 is connected to the FPC terminal portion 708 , and the pixel portion 702 is connected by the FPC 716 .
, a source driver circuit portion 704, and a gate driver circuit portion 706 are supplied with various signals and the like. In addition, a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706
, and the FPC terminal portion 708 are connected to signal lines 710, respectively. Various signals and the like supplied from the FPC 716 are applied to the pixel portion 702 , the source driver circuit portion 704 , and the gate driver circuit portion 706 through the signal line 710 .

Further, a plurality of gate driver circuit portions 706 may be provided in the display device 700 . Further, as the display device 700, an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the structure is not limited to this. For example, only the gate driver circuit portion 706 may be formed over the first substrate 701 or only the source driver circuit portion 704 may be formed over the first substrate 701 . In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701 . . The method of connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Wiring portions or a plurality of transistors are included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700, and the semiconductor device of one embodiment of the present invention can be applied. can.

Also, the display device 700 can have various elements. The element is, for example, a liquid crystal element, an EL (electroluminescence) element (an EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED).
etc.), transistors (transistors that emit light according to current), electron-emitting devices, electronic ink, electrophoretic devices, grating light valves (GLV), plasma displays (P
DP), display elements using MEMS (micro-electro-mechanical systems),
digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting It has at least one of a display element using a lighting element, a piezoelectric ceramic display, and a display element using carbon nanotubes. In addition to these, it may have a display medium in which contrast, brightness, reflectance, transmittance, etc. are changed by electrical or magnetic action. An example of a display device using an EL element is an EL display. Examples of display devices using electron-emitting devices include a field emission display (FED) or an SED flat panel display (SED: Surface-conduction E
electron-emitter display) and the like. Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct view liquid crystal displays, and projection liquid crystal displays).
and so on. An example of a display device using electronic ink or an electrophoretic element is electronic paper. In order to realize a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may function as reflective electrodes. For example, part or all of the pixel electrode may comprise aluminum, silver, or the like. Furthermore, in that case, it is also possible to provide a storage circuit such as an SRAM under the reflective electrode. Thereby, power consumption can be further reduced.

Note that the display method in the display device 700 can be a progressive method, an interlace method, or the like. In addition, R
It is not limited to three colors of GB (R for red, G for green, and B for blue). For example, it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel. Alternatively, like a pentile array, one color element may be composed of two colors of RGB, and two different colors may be selected according to the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. Note that the size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to a color display device and can also be applied to a monochrome display device.

In addition, white light (
A colored layer (also referred to as a color filter) may be used in order to display full color on the display device using W). The colored layers are, for example, red (R), green (G), blue (B)
, yellow (Y), etc. can be used in combination. By using a colored layer,
Color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, by arranging a region having a colored layer and a region having no colored layer, the white light in the region having no colored layer may be directly used for display. By arranging a region having no colored layer in part, a decrease in luminance due to the colored layer can be reduced in bright display, and power consumption can be reduced by about 20% to 30% in some cases. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and white (W) may be emitted from elements having the respective emission colors. . By using a self-luminous element, power consumption can be further reduced in some cases as compared to the case where a colored layer is used.

In this embodiment mode, a structure using a liquid crystal element and an EL element as a display element will be described with reference to FIGS. Note that FIG. 35 is a cross-sectional view taken along the dashed-dotted line QR shown in FIG. 34, and shows a structure using a liquid crystal element as a display element. FIG. 36 is a cross-sectional view taken along the dashed-dotted line QR shown in FIG. 34, and shows a configuration using an EL element as a display element.

First, the common parts shown in FIGS. 35 and 36 will be explained first, and then the different parts will be explained below.

[Description of Common Parts of Display Device]
A display device 700 shown in FIGS. 35 and 36 has a routing wiring portion 711 , a pixel portion 702 , a source driver circuit portion 704 , and an FPC terminal portion 708 . In addition, the routing wiring portion 711 has a signal line 710 . The pixel portion 702 also includes a transistor 750 and a capacitor 790 (the capacitor 790a or the capacitor 790b). The source driver circuit portion 704 also includes a transistor 752 .

In addition, the signal line 710 is formed in the same process as the conductive films functioning as the source and drain electrodes of the transistors 750 and 752 . Note that the signal line 710 is connected to the transistor 75
A conductive film formed in a process different from that of the source and drain electrodes of 0.752, for example, a conductive film functioning as a gate electrode may be used. For example, when a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small, and display on a large screen is possible.

The transistors described above can be used for the transistors 750 and 752 . Here, an example in which the structure of the transistor 100 illustrated in FIG. 13 is used for the transistors 750 and 752 is shown; however, other transistors described above may be used.

Alternatively, the structure of the transistor 100 illustrated in FIG. 16 may be used for the transistors 750 and 752, for example. In this case, the electrode 203b can be formed using the same process as the formation of the conductive layers 772 and 784, for example. By using the structure of transistor 100 shown in FIG. 16, for example, transistor 750 and transistor 75
2 can be increased, and the circuit operating speed can be increased. In addition, the channel widths of the transistors 750 and 752 can be reduced in some cases, which enables circuit integration.

The transistor used in this embodiment includes a highly purified oxide semiconductor film in which formation of oxygen vacancies is suppressed. The transistor can have a low current value in an off state (off current value). Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long in the power-on state. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

In addition, since the transistor used in this embodiment mode has relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor that can be driven at high speed in a liquid crystal display device, a switching transistor in a pixel portion and a driver transistor used in a driver circuit portion can be formed over the same substrate. That is, since it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate drive circuit, the number of parts of the semiconductor device can be reduced. Also in the pixel portion, a high-quality image can be provided by using a transistor that can be driven at high speed.

In addition, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive layer 780, and an FPC 71.
6. Note that the connection electrode 760 is formed in the same step as the conductive films functioning as source and drain electrodes of the transistors 750 and 752 . In addition, the connection electrode 760 is F
The terminals of the PC 716 are electrically connected through the anisotropic conductive layer 780 .

As the first substrate 701 and the second substrate 705, for example, glass substrates can be used. Alternatively, flexible substrates may be used as the first substrate 701 and the second substrate 705 . Examples of the flexible substrate include plastic substrates.

By using a flexible substrate, a flexible display device can be manufactured. Since the display device has flexibility, it becomes possible to attach it to a curved surface or an irregular shape, and a wide variety of applications are realized.

For example, by using a flexible substrate such as a plastic substrate, it is possible to reduce the thickness and weight of the display device. In addition, a display device using a flexible substrate such as a plastic substrate is less likely to break, and can have improved durability against impact when dropped, for example.

Further, on the second substrate 705 side, a light shielding film 738 functioning as a black matrix,
A colored film 736 functioning as a color filter and an insulating film 734 in contact with the light shielding film 738 and the colored film 736 are provided.

A structure 778 is provided between the first substrate 701 and the second substrate 705 . A structure 778 is a columnar spacer obtained by selectively etching an insulating film.
It is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705 . Note that a spherical spacer may be used as the structure 778 . Also, FIG.
4 illustrates the structure in which the structure 778 is provided on the second substrate 705 side; however, the present invention is not limited to this. For example, as shown in FIG. 36, a structure in which the structure 778 is provided on the first substrate 701 side or a structure in which the structure 778 is provided on both the first substrate 701 and the second substrate 705 may be employed.

35 and 36, over the transistors 750 and 752,
Insulating films 764, 766, and 768 are provided.

As the insulating films 764, 766, and 768, the insulating films 214 described in the above embodiments are used.
, 216 and 218 can be formed using the same material and fabrication method.

[Configuration example of a display device using a liquid crystal element as a display element]
A display device 700 illustrated in FIG. 35 includes a capacitor 790a. The capacitor 790a has a structure having a dielectric between a pair of electrodes. More specifically, as one electrode of the capacitor 790a, a highly conductive oxide semiconductor film formed through the same process as the oxide semiconductor film functioning as the semiconductor layer of the transistor 750 is used. As the other electrode, a conductive layer 772 electrically connected to the transistor 750 is used. An insulating film 768 is used as a dielectric sandwiched between the pair of electrodes.

Here, the highly conductive oxide semiconductor film that functions as one of the pair of electrodes of the capacitor 790a is described below.

[About highly conductive oxide semiconductor film]
When hydrogen is added to an oxide semiconductor in which oxygen vacancies are formed, hydrogen enters the oxygen vacancy sites and a donor level is formed near the conduction band. As a result, the oxide semiconductor becomes highly conductive,
Make it conductive. A conductive oxide semiconductor can be referred to as an oxide conductor. In general, an oxide semiconductor has a large energy gap and thus has a property of transmitting visible light.
On the other hand, an oxide conductor is an oxide semiconductor having a donor level near the conduction band. Therefore, the effect of absorption due to the donor level is small, and the material has a visible light-transmitting property similar to that of an oxide semiconductor.

Here, in each of a film formed using an oxide semiconductor (hereinafter referred to as an oxide semiconductor film (OS)) and a film formed using an oxide conductor (hereinafter referred to as an oxide conductor film (OC)), , describes the temperature dependence of the resistivity.

The temperature dependence of resistivity in the oxide conductor film (OC) is smaller than the temperature dependence of resistivity in the oxide semiconductor film (OS). Typically, the change rate of the resistivity of the oxide semiconductor film (OC) is less than ±20% at 80 K or more and 290 K or less. Or 150K or more 2
The change in resistivity below 50K is less than ±10%. That is, the oxide conductor is a degenerate semiconductor, and it is presumed that the conduction band edge and the Fermi level coincide or substantially coincide.
Therefore, an oxide conductor film can be used for one electrode of the capacitor 790a. Here, the oxide conductor film can be formed, for example, by forming silicon nitride on the In--M--Zn oxide.

The display device 700 shown in FIG. 35 also includes a liquid crystal element 775 . The liquid crystal element 775 is
It has a conductive layer 772 , a conductive layer 774 , and a liquid crystal layer 776 . The conductive layer 774 is provided on the second substrate 705 side and functions as a counter electrode. The display device 700 shown in FIG.
The voltage applied to the conductive layer 772 and the conductive layer 774 changes the orientation state of the liquid crystal layer 776, whereby transmission and non-transmission of light are controlled and an image can be displayed.

In addition, the conductive layer 772 is connected to conductive films functioning as source and drain electrodes of the transistor 750 . A conductive layer 772 is formed over the insulating film 768 and serves as a pixel electrode,
That is, it functions as one electrode of the display element.

Examples of the conductive layer 772 include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. A light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used.

Although not shown in FIG. 35, alignment films may be provided on the sides of the conductive layers 772 and 774 that are in contact with the liquid crystal layer 776 . Although not shown in FIG. 35, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Moreover, a backlight, a sidelight, or the like may be used as the light source.

When a liquid crystal element is used as a display element, thermotropic liquid crystal, low-molecular-weight liquid crystal, polymer liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on conditions.

In the case of adopting the horizontal electric field method, a liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition containing several weight percent or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is
Since it has a short response speed and is optically isotropic, it does not require alignment treatment and has little viewing angle dependency. In addition, rubbing treatment is not required because an alignment film is not required, so that electrostatic damage caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .

When a liquid crystal element is used as a display element, TN (Twisted Nematic
) mode, IPS (In-Plane-Switching) mode, FFS (Frin
ge Field Switching) mode, ASM (Axially Symme
tri-aligned Micro-cell) mode, OCB (Optical
Compensated Birefringence) mode, FLC (Ferroe
lectric Liquid Crystal) mode, AFLC (Anti-Ferr
(electrical Liquid Crystal) mode or the like can be used.

Alternatively, a normally black liquid crystal display device, for example, a transmissive liquid crystal display device employing a vertical alignment (VA) mode may be used. Some vertical alignment modes include, for example, MVA (Multi-Domain Vertical Alignment
) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, and the like can be used.

[Display Device Using Light Emitting Element as Display Element]
A display device 700 illustrated in FIG. 36 includes a capacitor 790b. The capacitor 790b has a structure having a dielectric between a pair of electrodes. In more detail, one electrode of the capacitor 790b is a conductive film formed in the same step as the conductive film functioning as the gate electrode of the transistor 750, and the other electrode of the capacitor 790b is the source of the transistor 750. A conductive film that functions as an electrode or a drain electrode is used. As a dielectric sandwiched between the pair of electrodes, an insulating film functioning as a gate insulating film of the transistor 750 is used.

Further, in FIG. 36, a planarization insulating film 770 is provided over the insulating film 768 .

As the planarization insulating film 770, a heat-resistant organic material such as polyimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Moreover, as shown in FIG.
A configuration in which 0 is not provided may be adopted.

The display device 700 illustrated in FIG. 36 also includes a light-emitting element 782 . The light emitting element 782 is
It has a conductive layer 784 , an EL layer 786 , and a conductive layer 788 . Display device 700 shown in FIG.
can display an image by light emission of the EL layer 786 included in the light-emitting element 782 .

In addition, the conductive layer 784 is connected to conductive films functioning as source and drain electrodes of the transistor 750 . The conductive layer 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element. As the conductive layer 784, a conductive film that transmits visible light or a conductive film that reflects visible light can be used. For the conductive film that transmits visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. For the conductive film that reflects visible light, a material containing aluminum or silver is preferably used, for example.

In addition, the insulating film 730 is provided over the planarization insulating film 770 and the conductive layer 784 in the display device 700 illustrated in FIG. The insulating film 730 partially covers the conductive layer 784 . Note that the light emitting element 782 has a top emission structure. Therefore, the conductive layer 788 has translucency, and E
It transmits light emitted by the L layer 786 . In addition, although the top emission structure is illustrated in the present embodiment, the present invention is not limited to this. For example, a bottom emission structure in which light is emitted to the conductive layer 784 side and a dual emission structure in which light is emitted to both the conductive layer 784 and the conductive layer 788 can be applied.

A colored film 736 is provided at a position overlapping with the light emitting element 782 , and a light shielding film 738 is provided at a position overlapping with the insulating film 730 , the lead wiring portion 711 , and the source driver circuit portion 704 . In addition, the colored film 736 and the light shielding film 738 are covered with an insulating film 734 . A sealing film 732 is filled between the light emitting element 782 and the insulating film 734 . In addition, Fig. 36
Although the structure in which the colored film 736 is provided is illustrated in the display device 700 shown in , the present invention is not limited to this. For example, in the case where the EL layer 786 is formed separately, the colored film 736 may not be provided.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 5)
In this embodiment, a display device including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

The display device shown in FIG. 26A includes a region having pixels of display elements (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) which is arranged outside the pixel portion 502 and has a circuit for driving the pixels.
hereinafter referred to as a drive circuit portion 504) and a circuit having an element protection function (hereinafter referred to as a protection circuit 504).
6) and a terminal portion 507 . Note that the protection circuit 506 may be omitted.

Part or all of the driver circuit portion 504 is preferably formed over the same substrate as the pixel portion 502 . This makes it possible to reduce the number of components and the number of terminals. Drive circuit section 504
is not formed on the same substrate as the pixel portion 502, part or all of the driver circuit portion 504 is formed of COG or TAB (Tape Automated B
onding).

The pixel portion 502 includes circuits (hereinafter referred to as pixel circuits 501) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). , the driving circuit unit 504 includes a circuit for outputting a signal (scanning signal) for selecting pixels (hereinafter referred to as a gate driver 504a), a circuit for supplying a signal (data signal) for driving the display element of the pixel ( Below, it has a driver circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a is
A signal for driving the shift register is input through the terminal portion 507, and the signal is output. For example, the gate driver 504a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 504a has a function of controlling potentials of wirings supplied with scan signals (hereinafter referred to as scan lines GL_1 to GL_X). Note that a plurality of gate drivers 504a may be provided and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, it is not limited to this, and the gate driver 50
4a can also provide other signals.

The source driver 504b has a shift register and the like. The source driver 504b
A signal for driving the shift register and a signal (image signal) that is the source of the data signal are input via the terminal portion 507 . The source driver 504b has a function of generating data signals to be written to the pixel circuits 501 based on image signals. The source driver 504b also has a function of controlling the output of the data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, and the like. The source driver 504b also has a function of controlling potentials of wirings supplied with data signals (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 504b has a function of supplying an initialization signal. However, it is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured using, for example, a plurality of analog switches.
The source driver 504b sequentially turns on a plurality of analog switches to
A signal obtained by time-dividing an image signal can be output as a data signal. Alternatively, the source driver 504b may be configured using a shift register or the like.

Each of the plurality of pixel circuits 501 receives a pulse signal through one of a plurality of scanning lines GL to which a scanning signal is applied, and receives a data signal through one of a plurality of data lines DL to which a data signal is applied. is entered. again. Each of the plurality of pixel circuits 501 is controlled by a gate driver 504a to write and hold the data of the data signal. For example, the pixel circuit 501 of the m-th row and the n-th column receives a pulse signal from the gate driver 504a via the scanning line GL_m (m is a natural number equal to or less than X), and responds to the potential of the scanning line GL_m to the data line DL_n (
A data signal is input from the source driver 504b via n (n is a natural number equal to or smaller than Y).

The protection circuit 506 shown in FIG. 26A includes, for example, the gate driver 504a and the pixel circuit 5
01 is connected to the scanning line GL. Alternatively, the protection circuit 506 is connected to the data line DL, which is wiring between the source driver 504b and the pixel circuit 501 . Alternatively, the protection circuit 506 can be connected to wiring between the gate driver 504 a and the terminal portion 507 . Alternatively, the protection circuit 506 can be connected to wiring between the source driver 504 b and the terminal portion 507 . Note that the terminal portion 507 is a portion provided with terminals for inputting power, control signals, and image signals from an external circuit to the display device.

The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring to which it is connected, brings the wiring into conduction with another wiring.

As shown in FIG. 26A, the pixel portion 502 and the driver circuit portion 504 each have a protection circuit 50 .
6, ESD (Electro Static Discharge:
It is possible to increase the resistance of the display device to overcurrent generated by electrostatic discharge) or the like.
However, the configuration of the protection circuit 506 is not limited to this. For example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b can be employed. Alternatively, a configuration in which a protective circuit 506 is connected to the terminal portion 507 can be employed.

FIG. 26A shows an example in which the driver circuit portion 504 is formed by the gate driver 504a and the source driver 504b; however, the structure is not limited to this. For example, only the gate driver 504a may be formed, and a separately prepared substrate on which a source driver circuit is formed (for example, a driving circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.

Further, the plurality of pixel circuits 501 shown in FIG. 26A can have the structure shown in FIG. 26B, for example.

A pixel circuit 501 illustrated in FIG. 26B includes a liquid crystal element 570 , a transistor 550 , and a capacitor 560 . The transistor described in any of the above embodiments can be applied to the transistor 550 .

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501 . The alignment state of the liquid crystal element 570 is set by written data. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501 . Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 in each row.

For example, methods for driving a display device including the liquid crystal element 570 include TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned M
micro-cell) mode, OCB (Optically Compensated)
Birefringence) mode, FLC (Ferroelectric Liquid)
id Crystal) mode, AFLC (AntiFerroelectric Li
Quid Crystal) mode, MVA mode, PVA (Patterned Veh
alignment) mode, IPS mode, FFS mode, or TBA
(Transverse Bend Alignment) mode or the like may be used.
In addition to the above-described driving method, the driving method of the display device includes an ECB (Electric
fully controlled birefringence) mode, PDLC (P
Polymer Dispersed Liquid Crystal) mode, PNLC
(Polymer Network Liquid Crystal) mode, guest host mode, and the like. However, it is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

In the pixel circuit 501 of the m-th row and the n-th column, one of the source electrode and the drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. be. Also, the gate electrode of the transistor 550 is connected to the scanning line G
electrically connected to L_m. The transistor 550 has a function of controlling data writing of the data signal by turning on or off.

One of the pair of electrodes of the capacitive element 560 is connected to a wiring to which a potential is supplied (hereinafter referred to as a potential supply line VL
) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570 . Note that the potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501 . The capacitor 560 functions as a storage capacitor that retains written data.

For example, in a display device having the pixel circuit 501 shown in FIG.
The pixel circuits 501 in each row are sequentially selected by the gate driver 504a shown in FIG.

The pixel circuit 501 to which data is written enters a holding state when the transistor 550 is turned off. An image can be displayed by sequentially performing this for each row.

Further, the plurality of pixel circuits 501 shown in FIG. 26A can have the structure shown in FIG. 26C, for example.

A pixel circuit 501 illustrated in FIG. 26C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 illustrated in FIG. Transistor 552 and transistor 554
The transistor described in any of the above embodiments can be applied to either one or both of .

One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring supplied with a data signal (hereinafter referred to as a signal line DL_n). Furthermore, the transistor 55
2 is electrically connected to a wiring to which a gate signal is applied (hereinafter referred to as a scanning line GL_m).

The transistor 552 has a function of controlling data writing of the data signal by turning on or off.

One of the pair of electrodes of the capacitive element 562 is connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL
_a), and the other is electrically connected to the other of the source and drain electrodes of the transistor 552 .

The capacitor 562 functions as a storage capacitor that retains written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of transistor 554 is electrically connected to the other of the source and drain electrodes of transistor 552 .

One of the anode and cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source and drain electrodes of the transistor 554 .

As the light-emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) can be used. However, the light-emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

Note that one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.

In a display device having the pixel circuit 501 shown in FIG. 26C, for example, the gate driver 504a shown in FIG. Write.

The pixel circuit 501 to which data is written enters a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 6)
An example of a semiconductor device using an oxide semiconductor of one embodiment of the present invention is described below.

[Examples of semiconductor devices]
FIG. 37A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. A semiconductor device illustrated in FIG. 37A includes a transistor 100, a transistor 130, a capacitor 150, a wiring WBL, a wiring RBL, a wiring WL, a wiring CL, a wiring BG, and a wiring SL. .

One of the source and the drain of the transistor 130 is electrically connected to the wiring RBL,
The other is electrically connected to the wiring SL, and the gate is electrically connected to one of the source and drain of the transistor 100 and one electrode of the capacitor 150 . The transistor 100 has the other of its source and drain electrically connected to the wiring WBL, and its first gate electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. A wiring BG is electrically connected to the second gate of the transistor 100 . Note that the transistor 1
30, one of the source or drain of the transistor 100, and the capacitive element 150
is called a node FN.

In the semiconductor device shown in FIG. 37A, a potential corresponding to the potential of the wiring WBL is applied to the node FN when the transistor 100 is on (on). It also has a function of holding the potential of the node FN when the transistor 100 is off (off). i.e.
The semiconductor device illustrated in FIG. 37A functions as a memory cell of a memory device. Figure 37
By arranging the semiconductor devices illustrated in (A) in matrix, a memory device (memory cell array) can be formed.

Note that a liquid crystal element or organic EL (electroluminescence) electrically connected to the node FN
When a display element such as an essence element is provided, the semiconductor device in FIG. 37A can function as a pixel of the display device.

Selection of an on state or an off state of the transistor 100 can be controlled by a potential applied to the wiring WL or the wiring BG. Further, the threshold of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. By using a transistor with low off-state current as the transistor 100, the potential of the node FN in an off state can be held for a long time. Therefore, the refresh frequency of the semiconductor device can be reduced, and a semiconductor device with low power consumption can be realized. By using a transistor including an oxide semiconductor film, for example, as the transistor 100, a transistor with low off-state current can be realized.

Note that a constant potential such as a reference potential, a ground potential, or an arbitrary fixed potential is applied to the wiring CL. At this time, the apparent threshold voltage of the transistor 100 varies depending on the potential of the node FN. Information on the potential held in the node FN can be read as data by using the fact that the on state and off state of the transistor 130 change due to the change in the apparent threshold voltage.

Note that the potential held at the node FN is kept at 85° C. for 10 years (3.15×10 ⁸ seconds).
In order to maintain the capacitance, it is preferable that the value of the off current per 1 fF of capacitance per 1 μm channel width of the transistor be less than 4.3 yA (yoctampere: 1 yA is 10 ⁻²⁴ A). At this time, it is preferable that the allowable fluctuation of the potential of the node FN is within 0.5V. Alternatively, the off current is preferably less than 1.5 yA at 95°C.

Further, by increasing the capacitance, the potential of the node FN can be held for a longer time. That is, the retention time can be lengthened.

In the semiconductor device illustrated in FIG. 37A, by utilizing the feature that the potential of the gate electrode of the transistor 130 can be held, data can be written, held, and read as follows.

Writing and holding information will be described. First, the potential of the wiring WL is set to the transistor 1
00 is set to an on-state potential, so that the transistor 100 is turned on. This will
The potential of the wiring WBL is applied to the gate electrode of the transistor 130 and the capacitor 150 . That is, a predetermined charge is applied to the gate electrode of the transistor 130 (writing). Here, charges that give two different potential levels (hereinafter referred to as Low level charges, High
h-level charge). After that, the potential of the wiring WL is
By setting the potential at which the transistor 100 is turned off to turn off the transistor 100, the charge applied to the gate electrode of the transistor 130 is held (held).

Since the off-state current of the transistor 100 is extremely low, charge in the gate electrode of the transistor 130 is retained for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the wiring CL while a predetermined potential (constant potential) is applied to the wiring RBL, the potential of the wiring SL varies depending on the amount of charge held in the gate electrode of the transistor 130 . take. In general, if the transistor 130 is an n-channel type, the apparent threshold V _{th_H} when the gate electrode of the transistor 130 is given a high-level charge is This is because it is lower than the apparent threshold value V _{th_L} in the case. Here, the apparent threshold voltage refers to the potential of the wiring CL required to turn on the transistor 130 . Therefore, the potential of the wiring CL is V _t
By setting the potential to _V0 between _{h_H} and _{Vth_L} , charge applied to the gate electrode of the transistor 130 can be determined. For example, when a high-level charge is applied in writing, if the potential of the wiring CL becomes V ₀ (>V _{th — H} ), the transistor 1
30 is in the "on state". When low-level charge is applied, the transistor 130 remains “off” even when the potential of the wiring CL becomes V ₀ (<V _{th — L} ). Therefore, by determining the potential of the wiring SL, the held information can be read. In order to reduce the number of wirings, for example, WBL and RBL shown in FIG. 37(A) may be electrically connected.

Note that when memory cells are arranged in an array and used, it is necessary to be able to read only the information of a desired memory cell. When data is not read in this way, the potential at which the transistor 130 is turned off regardless of the state of the gate electrode, that is, V _{th_H}
A smaller potential may be applied to the wiring CL. Alternatively, a potential at which the transistor 130 is turned on regardless of the state of the gate electrode, that is, a potential higher than _{Vth_L} may be applied to the wiring CL.

The semiconductor device shown in FIG. 37B is mainly similar to that shown in FIG. 37 in that the transistor 130 is not provided.
(A) is different. In this case as well, information can be written and held by operations similar to those described above.

Next, reading of information will be described. When the transistor 100 is turned on, the wiring BL which is in a floating state and the capacitor 150 are electrically connected, and electric charge is redistributed between the wiring BL and the capacitor 150 . As a result, the potential of the wiring BL changes. The amount of change in the potential of the wiring BL is
It takes different values depending on the potential of one electrode of the capacitor 150 (or the charge accumulated in the capacitor 150).

For example, the potential of one electrode of the capacitor 150 is V, the capacitance of the capacitor 150 is C, and the wiring B
Let CB be the capacitance component of L, and let VB0 be the potential of the wiring BL before the charge is redistributed.
The potential of the wiring BL after the charge redistribution is (CB×VB0+C×V)/(CB+C). Therefore, as the state of the memory cell, the potential of one electrode of the capacitor 150 is V1.
and V0 (V1>V0), the wiring BL when the potential V1 is held
(=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the wiring BL (=(CB×VB0+C×V0)/(CB+C)) when the potential V0 is held. I understand.

By comparing the potential of the wiring BL with a predetermined potential, information can be read.

The semiconductor device shown in FIGS. 37A and 37B can also be used as a memory device of a CPU, for example.

FIG. 38 shows an example of a cross-sectional structure of a semiconductor device capable of realizing the circuit shown in FIG. Note that FIG. 38 shows an example in which WBL and RBL are electrically connected in order to reduce the number of wirings. Note that FIG. 38(B) shows a cross section of a plane perpendicular to FIG. 38(A) through the dashed-dotted line AB shown in FIG. 38(A). Further, FIG. 38(C) passes through the dashed-dotted line CD shown in FIG. 38(A),
8(A) and a cross section of a plane perpendicular to FIG.

Transistor 100 is preferably provided above transistor 130 . By stacking the transistor 100 and the transistor 130, for example, the circuit area can be reduced. As the transistor 100, the transistor described in Embodiment 3 can be used, for example. FIG. 38 shows an example using the transistor 100 shown in FIG.

Transistor 130 comprises a first semiconductor material. Also, the transistor 1
00 comprises a second semiconductor material. Examples of semiconductors that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium, and arsenic; compound semiconductor materials containing silicon, germanium, gallium, arsenic, aluminum, and the like; Examples include organic semiconductor materials and oxide semiconductor materials.

The first semiconductor material and the second semiconductor material may be the same material, but are more preferably different semiconductor materials. Here, single crystal silicon is used as the first semiconductor material,
A case where an oxide semiconductor is used as the second semiconductor material will be described.

[First transistor]
The transistor 130 is provided over a semiconductor substrate 131 and includes a semiconductor layer 132 which is part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and low-resistance layers 133a and 133b functioning as a source region or a drain region. have

The transistor 130 may be either a p-channel type or an n-channel type, and an appropriate transistor may be used depending on the circuit configuration and driving method.

A semiconductor such as a silicon-based semiconductor is preferably contained in a region where a channel of the semiconductor layer 132 is formed, a region in the vicinity thereof, the low-resistance layers 133a and 133b serving as a source region or a drain region, and the like. It preferably contains silicon. or G
e (germanium), SiGe (silicon germanium), GaAs (gallium arsenide),
A material containing GaAlAs (gallium aluminum arsenide) or the like may be used. A structure using silicon having a strained crystal lattice may be used. Alternatively, by using GaAs, GaAlAs, or the like, the transistor 130 can be a HEMT (High Electron Mob
It may be used as a power transistor).

Further, the transistor 130 may have regions 176a and 176b, which are LDD (Lightly Doped Drain) regions.

For the low-resistance layers 133a and 133b, in addition to the semiconductor material applied to the semiconductor layer 132, an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron is used. include.

The gate electrode 135 is composed of an element imparting n-type conductivity such as phosphorus, or a p-type conductive element such as boron.
Conductive materials such as semiconductor materials such as silicon containing elements that impart conductivity of type, metal materials, alloy materials, or metal oxide materials can be used.

Here, instead of the transistor 130, a transistor 190 as shown in FIGS. 29A and 29B may be used. FIG. 29(B) shows a cross section of a plane perpendicular to FIG. 29(A) through the dashed-dotted line EF shown in FIG. 29(A). In the transistor 190, a semiconductor layer 132 (part of the semiconductor substrate) in which a channel is formed has a convex shape, and a gate insulating film 134 and a gate electrode 135 are provided along the side and top surfaces thereof. An element isolation layer 181 is provided between the transistors. Such a transistor 190 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate. Note that an insulating film that functions as a mask for forming the projection may be provided in contact with the upper portion of the projection. Further, here, a case where a part of the semiconductor substrate is processed to form a convex portion is shown, but SOI (Silicon OI) is used.
n Insulator) The substrate may be processed to form a semiconductor layer having a convex shape.

An insulating film 136 , an insulating film 137 , and an insulating film 138 are stacked in this order to cover the transistor 130 .

The insulating film 136 is the low-resistance layer 133a and the low-resistance layer 133 in the manufacturing process of the semiconductor device.
It functions as a protective film when activating the element imparting electrical conductivity added to b. Insulating film 13
6 may be omitted if unnecessary.

When a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By performing the heat treatment, hydrogen in the insulating film 137 terminates dangling bonds in the semiconductor layer 132, so that the reliability of the transistor 130 can be improved.

The insulating film 138 functions as a planarization layer that planarizes a step caused by the transistor 130 or the like provided therebelow. The upper surface of the insulating film 138 may be planarized by a CMP method or the like.

Moreover, the insulating film 136, the insulating film 137, and the insulating film 138 include the low-resistance layer 133a and the low-resistance layer 1.
A plug 140 electrically connected to 33b and the like, a plug 139 electrically connected to the gate electrode 135 of the transistor 130, and the like may be embedded.

A barrier film 111 is provided between the transistor 130 and the transistor 100 . The barrier film 111 is a layer having a function of suppressing diffusion of water and hydrogen from a lower layer to an upper layer. Also, the barrier film 111 preferably has low oxygen permeability. Here, "water and hydrogen are less likely to diffuse" means that the permeability of water and hydrogen is lower than that of silicon oxide or the like, which is generally used as an insulating film, for example. Also, low oxygen permeability means that the oxygen permeability is low compared to, for example, silicon oxide or the like generally used as an insulating film.

Materials that can be used for the barrier film 111 include aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr)TiO ₃ (BST). ) and other so-called h
An insulating film containing high-k material can be used in a single layer or a stack of layers. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided to form an oxynitride film. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulating film. In particular, aluminum oxide is more preferable because it has excellent barrier properties against water and hydrogen.

In addition, the materials described above are excellent in barrier properties against oxygen as well as against hydrogen and water. Therefore, oxygen released when the insulating film 114 is heated can be prevented from diffusing into layers below the barrier film 111 . As a result, it is released from the insulating film 114 and the transistor 100
can increase the amount of oxygen that can be supplied to the semiconductor layer of

Here, it is preferable to reduce hydrogen, water, and the like in the layers below the barrier film 111 by heat treatment, for example. The heat treatment conditions may be, for example, an inert gas atmosphere or a reduced pressure atmosphere at 170° C. or higher.

In the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment is treatment for terminating dangling bonds of silicon with hydrogen (also referred to as hydrogenation treatment). can serve as

A conductive layer 151 , a conductive layer 152 a , and a conductive layer 152 b are provided to sandwich the barrier film 111 to form the capacitor 150 . Conductive layer 151 is electrically connected to conductive layer 104 a of transistor 100 .

An insulating film 114 is provided to cover the barrier film 111, the conductive layers 152a, 152b, the conductive layer 105, and the like. For the insulating film 114, refer to the description of the insulating film 114 in FIG. 12, for example.

[Second transistor]
A transistor 100 is provided over the insulating film 114 . In the example shown in FIG. 38, the transistor shown in FIG. 12 is used as the transistor 100. FIG.

In addition, the transistor 100 shown in FIG. 38 has the conductive layer 1 functioning as the second gate electrode.
05. The conductive layer 105 may be formed at the same time as the conductive layers 152 a and 152 b that form part of the capacitor 150 . By forming these conductive layers simultaneously, the process can be simplified, for example.

An insulating film 112 , an insulating film 113 , and an insulating film 116 are provided to cover the transistor 100 .

As with the barrier film 111, the insulating film 112 is preferably made of a material into which water and hydrogen are difficult to diffuse. In particular, it is preferable to use a material that is less permeable to oxygen.

Note that the insulating film 112 may have a stacked structure of two or more layers. In that case, it is preferable that the insulating film 112 has a two-layer structure, and that the upper layer be made of a material that makes it difficult for water or hydrogen to diffuse. For the lower layer, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used. The insulating film provided as a lower layer may be an insulating film from which oxygen is released by heating, similar to the insulating film 114 , and oxygen may be supplied from above the semiconductor layer 101 through the gate insulating film 102 .

By covering the semiconductor layer 101 with the insulating film 112 , release of oxygen from the semiconductor layer 101 above the insulating film 112 can be suppressed. Furthermore, since oxygen released from the insulating film 114 or the like can be confined below the insulating film 112, the amount of oxygen that can be supplied to the semiconductor layer 101 can be increased.

In addition, by providing the insulating film 112, entry of water or hydrogen into the oxide semiconductor from the outside can be suppressed. Therefore, a highly reliable transistor in which variation in electrical characteristics is suppressed can be achieved.

As the insulating film 113, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and a stacked layer or a single layer is provided.

The insulating film 116 covering the transistor 100 functions as a planarization layer covering the uneven shape of the underlying layer. The insulating film 113 may also function as a protective film when the insulating film 116 is formed. The insulating film 113 may be omitted if unnecessary. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used as the insulating film 116, and the insulating film 116 is provided as a stacked layer or a single layer.

Plugs 321, 322, and 123 electrically connected to the conductive layer 104b are embedded in the insulating films 112, 113, and 116, respectively.

A wiring 124 and the like electrically connected to the plug 322 are provided on the insulating film 116 .

Alternatively, as shown in FIG. 38, an insulating film 137 containing a material similar to that of the barrier film 111 may be provided over the insulating film 136 containing hydrogen. With such a structure, upward diffusion of water and hydrogen remaining in the insulating film 136 containing hydrogen can be effectively suppressed.

Wirings such as the wiring 124 and the wiring 166, conductive layers such as the conductive layer 143, the conductive layer 151, the conductive layer 152a, the conductive layer 152b, and the conductive layer 251, and the plugs 123, 139, and 1
The plugs such as 40, plug 164, and plug 165 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. In particular, it is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. Alternatively, a material such as titanium nitride or titanium may be used by being laminated with another material.

[Example of manufacturing method]
Next, an example of a method for manufacturing the semiconductor device in FIG. 38 is described with reference to FIGS.

First, a semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Alternatively, an SOI substrate may be used as the semiconductor substrate 131 . The case where single crystal silicon is used as the semiconductor substrate 131 will be described below.

Subsequently, a device isolation layer (not shown) is formed on the semiconductor substrate 131 . The isolation layer is LOC
OS (Local Oxidation of Silicon) method or STI (Sh
It may be formed using the allow Trench Isolation method, the mesa separation method, or the like.

When forming a p-type transistor and an n-type transistor on the same substrate, a semiconductor substrate 1
A portion of 31 may form an n-well or p-well. For example, n-type semiconductor substrate 13
An impurity element such as boron that imparts p-type conductivity may be added to 1 to form a p-well, and an n-type transistor and a p-type transistor may be formed on the same substrate.

Subsequently, an insulating film to be the gate insulating film 134 is formed on the semiconductor substrate 131 . for example,
The surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, after forming silicon oxide by a thermal oxidation method, the surface of the silicon oxide film may be nitrided by performing nitriding treatment to form a stacked structure of a silicon oxide film and a silicon oxynitride film. Alternatively, silicon oxide, silicon oxynitride, tantalum oxide which is a high dielectric constant substance (also referred to as high-k material), hafnium oxide, hafnium silicate oxide, zirconium oxide,
Metal oxides such as aluminum oxide and titanium oxide, rare earth oxides such as lanthanum oxide, and the like may also be used.

The insulating film is formed by a sputtering method, a CVD (Chemical Vapor Depot
site) method (including thermal CVD method, MOCVD (Metal Organic CVD) method, PECVD (Plasma Enhanced CVD) method, etc.), MBE (Mo
Lecular Beam Epitaxy) method, ALD (Atomic Layer
Deposition) method, or PLD (Pulsed Laser Deposit
It may be formed by forming a film by an ion) method or the like.

Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like, or an alloy material or compound material containing these metals as main components. Alternatively, polycrystalline silicon doped with an impurity such as phosphorus can be used. Alternatively, a laminated structure of a metal nitride film and the above metal film may be used. As metal nitrides, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing the metal nitride film, adhesion of the metal film can be improved and peeling can be prevented.

The conductive film can be formed by a sputtering method, a vapor deposition method, a CVD method (thermal CVD method, MOCVD method, PEC
(including VD method, etc.). Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

Subsequently, a resist mask is formed over the conductive film by a lithography method or the like, and unnecessary portions of the conductive film are removed. After that, the gate electrode 135 can be formed by removing the resist mask.

Here, a method for processing the film to be processed will be described. Various microfabrication techniques can be used as the processing method. For example, a method of performing slimming treatment on a resist mask formed by a photolithography method or the like may be used. Alternatively, a dummy pattern may be formed by photolithography or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the remaining sidewall may be used as a resist mask to etch the film to be processed. In addition, in order to achieve a high aspect ratio as etching of the film to be processed,
Anisotropic dry etching is preferably used. A hard mask made of an inorganic film or a metal film may also be used.

The light used for forming the resist mask is i-line (wavelength 365 nm), g-line (wavelength 43 nm), for example.
6 nm), h-line (wavelength 405 nm), or a mixture thereof can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used.
Moreover, you may expose by a liquid immersion exposure technique. As the light used for exposure, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used. An electron beam can also be used instead of the light used for exposure. The use of extreme ultraviolet light, X-rays, or electron beams is preferable because extremely fine processing is possible. A photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

Further, an organic resin film having a function of improving adhesion between the film to be processed and the resist film may be formed before forming the resist film serving as the resist mask. The organic resin film can be formed by, for example, a spin coating method or the like so as to cover the steps in the lower layer and flatten the surface. can be reduced. Further, particularly when fine processing is performed, it is preferable to use a material that functions as an antireflection film against the light used for exposure as the organic resin film. As an organic resin film having such a function, for example, BARC (Bottom Anti-Reflection
Coating) film and the like. The organic resin film may be removed at the same time as the resist mask is removed, or may be removed after the resist mask is removed.

For the description of processing using a resist mask, the processing method described for the gate electrode 135 may be referred to hereinafter. Further, in this specification, the description of the removal of the resist after etching the film to be processed may be omitted.

After forming the gate electrode 135, sidewalls covering the side surfaces of the gate electrode 135 may be formed. After forming an insulating film thicker than the thickness of the gate electrode 135, the sidewalls are
It can be formed by anisotropic etching so that the insulating film remains only on the side portions of the gate electrode 135 .

FIG. 39 shows an example in which the gate insulating film is not etched when forming the sidewalls, but the insulating film to be the gate insulating film 134 may be etched at the same time when the sidewalls are formed. In this case, a gate insulating film 134 is formed under the gate electrode 135 and sidewalls.

Subsequently, an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron is added to a region of the semiconductor substrate 131 where the gate electrode 135 (and sidewalls) is not provided. do. A schematic cross-sectional view at this stage corresponds to FIG.

Subsequently, after forming the insulating film 136, for example, heat treatment for activating the above-described element imparting conductivity is performed. The heat treatment can be performed in an inert gas atmosphere such as a rare gas or nitrogen gas, or in a reduced pressure atmosphere, for example, at a temperature of 400° C. or more and less than the strain point of the substrate.

The insulating film 136 may be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and is provided as a stacked layer or a single layer. The insulating film 136 can be formed using a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, etc.), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. To reduce plasma damage, thermal CVD, MOCVD, or A
The LD method is preferred.

Transistor 130 is formed at this stage. Also, the third transistor 160 may be formed in a manner similar to that of forming the transistor 130 .

Subsequently, insulating films 137 and 138 are formed.

For the insulating film 137, a material that can be used for the insulating film 136, or silicon nitride containing oxygen and hydrogen (SiNOH) may be used. Insulating film 138 is made of a material that can be used for insulating film 136, or TEOS (Tetra-Ethyl-Ortho-Silicon).
It is preferable to use silicon oxide which is formed by reacting cate) or silane with oxygen, nitrous oxide, or the like and having good step coverage.

The insulating film 137 and the insulating film 138 are formed by, for example, a sputtering method, a CVD method (thermal CVD method,
(including MOCVD, PECVD, etc.), MBE, ALD, PLD, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

Subsequently, the upper surface of the insulating film 138 is planarized using the CMP method or the like. Alternatively, a planarization film may be used as the insulating film 138 . In that case, planarization by a CMP method or the like is not necessarily required.
For forming the planarization film, for example, an atmospheric pressure CVD method, a coating method, or the like can be used. Normal pressure C
Examples of films that can be formed using the VD method include BPSG (Boron Phosphor
US Silicate Glass) and the like. In addition, examples of films that can be formed using a coating method include HSQ (hydrogen silsesquioxane). After that, heat treatment may be performed to terminate dangling bonds in the semiconductor layer 132 with hydrogen released from the insulating film 137 .

Subsequently, openings reaching the low-resistance layers 133a and 133b, the gate electrode 135, and the like are formed in the insulating films 136, 137, and 138 (see FIG. 39B). After that, a conductive film is formed so as to fill the opening (see FIG. 39C). After that, the insulating film 138
The conductive film is planarized so that the top surface of the conductive film is exposed, thereby forming plugs 139, 140, and the like (see FIG. 39D). The conductive film can be formed using, for example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PLD.

Subsequently, an insulating film 215 is formed over the insulating film 138 . The insulating film 215 can be formed using a material and a method similar to those of the insulating film 136 and the like. Heat treatment may be performed after the insulating film 215 is formed.

The third heat treatment can be performed under the conditions exemplified in the description of the laminated structure. For example, the conditions described in the first heat treatment can be used.

Subsequently, an opening is formed in the insulating film 215 . After that, a conductive film is formed so as to fill the opening, and the conductive film is subjected to planarization treatment so that the upper surface of the insulating film 215 is exposed. (See FIG. 39(E)). When forming a conductive film in the opening, for example, a material such as titanium nitride or titanium may be formed in the opening and then another conductive material may be laminated. For example, by using titanium nitride or titanium as the lower layer of the laminated film, the adhesion to the opening can be improved.

Subsequently, a barrier film 111 is formed to form an opening (see FIG. 40A). The barrier film 111 is formed by sputtering, CVD (thermal CVD, MOCVD, PECVD), for example.
method, etc.), MBE method, ALD method, PLD method, or the like.
In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

Subsequently, conductive films to be the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed.
After that, the conductive layer 105, the conductive layer 152a, and the conductive layer 152b are formed by etching or the like (see FIG. 40B).

Next, an insulating film 114 is formed. The insulating film 114 is formed by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PL, for example.
It can be formed using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

In order to make the insulating film 114 contain an excess amount of oxygen, for example, the insulating film 11 is heated under an oxygen atmosphere.
4 may be performed. Alternatively, a region containing excess oxygen may be formed by introducing oxygen into the insulating film 114 after deposition, or both means may be combined.

For example, oxygen (including at least oxygen radicals, oxygen atoms, or oxygen ions) is introduced into the insulating film 114 after deposition to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. or,
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

Further, after the insulating film 114 is formed, planarization treatment using a CMP method or the like may be performed in order to improve the planarity of the upper surface.

Next, a semiconductor film to be the insulator layer 101a and a semiconductor film to be the semiconductor layer 101b are formed in this order (see FIG. 40C). The semiconductor film is preferably formed continuously without being exposed to the air. A semiconductor to be the insulator layer 101a and a semiconductor to be the semiconductor layer 101b may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Note that I
When the n-Ga-Zn oxide layer is formed by the MOCVD method, trimethylindium, trimethylgallium, dimethylzinc, or the like may be used as source gases. Note that the combination of source gases is not limited to the above, and triethylindium or the like may be used instead of trimethylindium. Further, triethylgallium or the like may be used instead of trimethylgallium. Also, diethylzinc or the like may be used instead of dimethylzinc.

Here, oxygen may be introduced into the insulator layer 101a after the insulator layer 101a is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101a after deposition to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. or,
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

Heat treatment may be performed after the insulator layer 101a and the semiconductor layer 101b are formed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 300° C. to 500° C. in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Further, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more in order to compensate for desorbed oxygen after the heat treatment is performed in an inert gas atmosphere. The heat treatment may be performed immediately after the semiconductor film is formed, or the semiconductor film may be processed to form the island-shaped insulator layers 101a and 101b.
may be performed after forming the By the heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film, so that oxygen vacancies in the semiconductor film can be reduced.

After that, using a resist mask, the island-shaped insulator layer 101a and the island-shaped semiconductor layer 101b are formed.
is formed (see FIG. 40(D)). Note that part of the insulating film 114 is etched when the semiconductor film is etched, and the insulating film 114 in a region not covered with the insulating layer 101a and the semiconductor layer 101b is thinned in some cases. Therefore, it is preferable to form the insulating film 114 thick in advance so that the insulating film 114 is not lost by the etching.

Since the resist may disappear during the etching process depending on the etching conditions of the semiconductor film, a so-called hard mask made of a material with high etching resistance such as an inorganic film or a metal film may be used. Here, an example using a conductive film as the hard mask 281 is shown. FIG. 41A shows an example of processing a semiconductor film using a hard mask 281 to form an insulator layer 101a and a semiconductor layer 101b. Here, if a material that can be used for the conductive layers 104a and 104b is used for the hard mask 281, the hard mask 281 can be processed to form the conductive layers 104a and 104b. By using such a method, for example, the transistor 100 shown in FIG. 30 can be manufactured.

After forming the structure shown in FIG. 40D, openings reaching the conductive layers 151, 251, and the like are provided in the insulating film 114 (see FIG. 41B). After that, a conductive film to be the conductive layers 104 a , 104 b , and the like is formed so as to fill the openings provided in the insulating film 114 . conductive layer 1
04a, the conductive layer 104b, etc. can be formed by, for example, a sputtering method, a CVD method (
including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD or PLD
It can be formed using a method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

Next, using a resist mask, unnecessary portions of the conductive film to be the conductive layers 104a, 104b, and the like are removed by etching to form the conductive layers 104a, 104b, and the like (
See FIG. 41(C)). Here, when the conductive film is etched, the semiconductor layer 101b and the insulating film 1 are etched.
A part of the upper part of 14 may be etched, and the part which does not overlap with the conductive layer 104a and the conductive layer 104b may become thin. Therefore, the thickness of the semiconductor film or the like that becomes the semiconductor layer 101b is
It is preferable to form a thick film in advance in consideration of the etching depth.

Next, an insulator layer 101c and a gate insulating film 102 are formed. After that, etching is performed using a resist mask (see FIG. 42A). Next, a conductive film to be the gate electrode 103 is formed and processed using a resist mask to form the gate electrode 103 (see FIG. 42B).

For the method of forming the insulator layer 101c, refer to the insulator layer 101a, for example.

Alternatively, oxygen may be introduced into the insulator layer 101c after the insulator layer 101c is formed. For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulator layer 101c after deposition to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

A gas containing oxygen can be used for the oxygen introduction treatment. As a gas containing oxygen,
For example, oxygen, nitrous oxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. Further, in the oxygen introduction treatment, a gas containing oxygen may contain a rare gas. or,
Hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

Transistor 100 is formed at this stage.

Next, an insulating film 112 is formed. The insulating film 112 is formed by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, or PL, for example.
It can be formed using the D method or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

After the insulating film 112 is formed, heat treatment may be performed. By heat treatment, oxygen can be supplied from the insulating film 114 or the like to the semiconductor layer 101, and oxygen vacancies in the semiconductor layer 101 can be reduced.

Alternatively, the insulating film 112 may have a stacked structure of two or more layers.

Subsequently, an insulating film 113 is formed. The insulating film 113 is formed by sputtering or CVD, for example.
method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed using an LD method or the like. In particular, CVD methods, preferably plasma CVD
It is preferable to form a film by a method because good coverage can be obtained. Thermal CVD, MOCVD, or ALD is preferable for reducing plasma damage.

Subsequently, the insulating film 113, the insulating film 112, the gate insulating film 102, and the insulating layer 101c are
An opening reaching the conductive layer 104a and the like is provided. Next, after forming a conductive film so as to fill the openings, unnecessary portions are removed using a resist mask to form plugs 321 and 322 .

Subsequently, an insulating film 116 is formed. The insulating film 116 is formed by, for example, a sputtering method or a CVD method.
method (including thermal CVD method, MOCVD method, PECVD method, etc.), MBE method, ALD method or P
It can be formed using an LD method or the like. Further, when an organic insulating material such as an organic resin is used as the insulating film 116, a coating method such as a spin coating method may be used. Further, it is preferable to perform planarization treatment on the upper surface of the insulating film 116 after the formation of the insulating film 116 . Alternatively, the insulating film 116 may be formed using the material and formation method of the insulating film 138 .

Subsequently, the plug 12 reaching the plug 322 is formed on the insulating film 116 by a method similar to that described above.
Form 3rd class.

Subsequently, a conductive film is formed over the insulating film 116 . After that, unnecessary portions of the conductive film are removed by etching using a resist mask by a method similar to that described above, so that the wiring 124 and the like can be formed.

Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 7)
In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to drawings.

[Example of circuit configuration]
Various circuits can be formed by changing the connection structures of transistors, wirings, and electrodes in the structure shown in the semiconductor device to which Embodiment 1 is applied. An example of a circuit configuration that can be realized by using a semiconductor device of one embodiment of the present invention is described below.

[CMOS circuit]
The circuit diagram shown in FIG. 37C is a so-called CM transistor in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.
1 shows the configuration of an OS circuit. Note that in the drawings, the transistor to which the second semiconductor material is applied is indicated by the symbol "OS". Here, the CMOS circuit shown in this embodiment has N
AND circuit, NOR circuit, encoder, decoder, MUX (multiplamplif
ier), DEMUX (demultiplexer), etc., as basic elements of logic circuits.

[Analog switch]
The circuit diagram in FIG. 37D shows a structure in which the sources and drains of the transistors 2100 and 2200 are connected. With such a configuration,
It can function as a so-called analog switch.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 8)
In this embodiment, a display module including a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

A display module 8000 shown in FIG.
0, with battery 8011;

A semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

The shape and dimensions of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

As the touch panel 8004 , a resistive or capacitive touch panel can be used by overlapping the display panel 8006 . In addition, it is possible to provide a counter substrate (sealing substrate) of the display panel 8006 with a touch panel function. Also, the display panel 8
An optical sensor can be provided in each pixel of 006 to form an optical touch panel.

The backlight 8007 has a light source 8008 . Note that FIG. 27 illustrates the configuration in which the light source 8008 is arranged over the backlight 8007, but the configuration is not limited to this. For example, the light source 8008 may be arranged at the end of the backlight 8007, and a light diffusion plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element or in the case of a reflective panel or the like, the backlight 8007 may not be provided.

The frame 8009 has a function of protecting the display panel 8006 as well as a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010 . The frame 8009 may also function as a heat sink.

The printed circuit board 8010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. A power supply for supplying power to the power supply circuit may be an external commercial power supply, or may be a power supply using a battery 8011 provided separately. The battery 8011 can be omitted when a commercial power supply is used.

In addition, the display module 8000 may be additionally provided with members such as a polarizing plate, a retardation plate, and a prism sheet.

The display module 8000 described in this embodiment may have flexibility. Having flexibility makes it possible to bond onto a curved surface or an irregular shape, realizing a wide variety of uses.

The structure described in this embodiment can be used in appropriate combination with any of the structures described in other embodiments.

(Embodiment 9)
In this embodiment mode, an R transistor including the transistor or the memory device exemplified in the above embodiment mode is used.
The F tag will be explained with reference to FIG. 28 .

The RF tag according to the present embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means such as wireless communication. Due to such features, RF tags can be used in individual authentication systems that identify articles by reading individual information on the articles. In addition, extremely high reliability is required for use in these applications.

A configuration of the RF tag will be described with reference to FIG. FIG. 28 is a block diagram showing a configuration example of an RF tag.

As shown in FIG. 28, an RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also called interrogator, reader/writer, etc.). The RF tag 800 also has a rectifying circuit 805 , a constant voltage circuit 806 , a demodulating circuit 807 , a modulating circuit 808 , a logic circuit 809 , a memory circuit 810 and a ROM 811 . Note that a material capable of sufficiently suppressing reverse current, such as an oxide semiconductor, may be used for the rectifying transistor included in the demodulation circuit 807 . As a result, it is possible to suppress the deterioration of the rectifying action due to the reverse current and prevent the output of the demodulator from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: the electromagnetic coupling method, in which a pair of coils are placed facing each other and communicate by mutual induction, the electromagnetic induction method, in which communication is performed by an induced electromagnetic field, and the radio wave method, in which communication is performed using radio waves. separated. The RF tag 800 shown in this embodiment can be used for any of these methods.

Next, the configuration of each circuit will be described. Antenna 804 is for transmitting/receiving radio signal 803 to/from antenna 802 connected to communication device 801 . Also, the rectifier circuit 805 rectifies, for example, half-wave double voltage rectification of an input AC signal generated by receiving a radio signal at the antenna 804, and converts the rectified signal by a capacitive element provided in the latter stage. This is a circuit for generating an input potential by smoothing. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805 . A limiter circuit is a circuit for controlling so that power exceeding a certain level is not input to a subsequent circuit when the amplitude of an input AC signal is large and the internally generated voltage is large.

A constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 8
09 reset signal.

The demodulation circuit 807 is a circuit for demodulating the input AC signal by detecting its envelope and generating a demodulation signal. A modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804 .

A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. A memory circuit 810 is a circuit that holds input information, and includes a row decoder, a column decoder, a memory area, and the like. A ROM 811 is a circuit for storing a unique number (ID) and the like, and for outputting according to processing.

It should be noted that each of the circuits described above can be omitted as appropriate, if necessary.

Here, the memory circuit described in the above embodiment can be used for the memory circuit 810 . The memory circuit of one embodiment of the present invention can hold information even when power is shut off; therefore, it can be suitably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention requires significantly less power (voltage) for data writing than conventional nonvolatile memories, so that there is no difference in the maximum communication distance between reading and writing data. is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to power shortage during data writing.

Further, since the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory, it can also be applied to the ROM 811 . In that case, it is preferable that the manufacturer separately prepares a command for writing data into the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped instead of assigning a unique number to all the manufactured RF tags. To facilitate customer management corresponding to products after shipment without discontinuity of unique numbers of products after shipment.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 10)
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device (typically a DVD: Digital Versatile Disc) provided with a recording medium.
It can be used for a device having a display capable of reproducing a recording medium such as c and displaying an image thereof. In addition, electronic devices that can use the semiconductor device of one embodiment of the present invention include mobile phones, game machines including portable types, portable data terminals, electronic books, video cameras,
Cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multi-function printers, automatic teller machines (ATMs) ), vending machines, etc. Specific examples of these electronic devices are shown in FIG.

FIG. 57A shows a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, and a stylus 90.
8 etc. Note that the portable game machine shown in FIG. 57A has two display portions 903 and 904, but the number of display portions in the portable game machine is not limited to this.

FIG. 57B shows a portable data terminal including a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. First display section 91
3 is provided in the first housing 911 and the second display unit 914 is provided in the second housing 912 . The first housing 911 and the second housing 912 are connected by a connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. be. The image on the first display unit 913 may be switched according to the angle between the first housing 911 and the second housing 912 at the connection unit 915 . Also, at least one of the first display unit 913 and the second display unit 914 may be a display device added with a function as a position input device. A function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function of a position input device can be added by providing a photoelectric conversion element, also called a photosensor, in a pixel portion of a display device.

FIG. 57C shows a notebook personal computer including a housing 921, a display portion 922,
It has a keyboard 923, a pointing device 924, and the like.

FIG. 57(D) shows an electric refrigerator-freezer, which includes a housing 931, a refrigerator compartment door 932, and a freezer compartment door 9.
33, etc.

FIG. 57E shows a video camera including a first housing 941, a second housing 942, and a display portion 943.
, operation keys 944, a lens 945, a connection portion 946, and the like. The operation keys 944 and the lens 945 are provided on the first housing 941 , and the display section 943 is provided on the second housing 942 . The first housing 941 and the second housing 942 are connected by a connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. be. The image on the display unit 943 is displayed on the first housing 941 and the second housing 94 on the connection unit 946.
It is good also as a structure which switches according to the angle between 2.

FIG. 57(F) is an ordinary automobile, which includes a vehicle body 951, wheels 952, a dashboard 953,
It has a light 954 and the like.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

(Embodiment 11)
In this embodiment, a usage example of an RF tag according to one embodiment of the present invention will be described with reference to FIGS. RF tags are used in a wide range of applications. bottles, etc., see FIG. 56(C)), recording media (DVDs, video tapes, etc., see FIG. 56(B)), vehicles (bicycles, etc., see FIG. 56(D)), personal items (bags, glasses, etc.) , food,
Plants, animals, human bodies, clothing, daily necessities, medical products including medicines and drugs, or electronic devices (
(liquid crystal display device, EL display device, television device, or mobile phone) or a tag attached to each article (see FIGS. 56(E) and 56(F)).

By sticking or embedding the RF tag 4000 according to one aspect of the present invention on a surface,
Fixed to an article. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF tag 4000 according to one embodiment of the present invention is small, thin, and lightweight, it does not impair the design of the article itself even after it is fixed to the article. In addition, by providing the RF tag 4000 according to one aspect of the present invention to bills, coins, securities, bearer bonds, certificates, or the like, an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one aspect of the present invention to packaging containers, recording media, personal effects, foods, clothes, daily necessities, electronic devices, or the like, the efficiency of systems such as inspection systems can be improved. can be planned. In addition, by attaching the RF tag according to one embodiment of the present invention to vehicles, security against theft or the like can be improved.

As described above, by using the RF tag according to one embodiment of the present invention for each application described in this embodiment, the operating power including writing and reading of information can be reduced, and thus the maximum communication distance can be increased. becomes possible. In addition, since information can be retained for an extremely long period of time even when power is shut off, it can be suitably used for applications in which writing and reading are infrequent.

This embodiment can be implemented by appropriately combining at least part of it with other embodiments described herein.

It should be noted that a drawing (may be a part) described in one embodiment refers to another part of the drawing, another drawing (may be a part) described in the embodiment, and/or one or more By combining the figures (or part of them) described in another embodiment, more figures can be configured.

It should be noted that it is possible to constitute one aspect of the invention in which content that is not specified in the drawings or text in the specification is excluded. Alternatively, if a numerical range is indicated with an upper limit and a lower limit for a certain value, the range may be narrowed by arbitrarily narrowing the range or removing one point in the range. It is possible to define one aspect of the invention excluding some aspects. These can define, for example, that prior art does not fall within the technical scope of one aspect of the present invention.

As a specific example, it is assumed that a circuit diagram using first to fifth transistors is described in a certain circuit. In that case, it is possible to stipulate as an invention that the circuit does not have a sixth transistor. Alternatively, it is possible to specify that the circuit has no capacitive elements. Furthermore, the invention can be constructed by stipulating that the circuit does not have a sixth transistor having a specific connection structure. Alternatively, the invention can be configured by stipulating that the circuit does not have a capacitive element having a specific connection structure. For example, it is possible to define the invention as not having a sixth transistor whose gate is connected to the gate of a third transistor.
Alternatively, for example, it is possible to define the invention as not having a capacitive element whose first electrode is connected to the gate of the third transistor.

As another specific example, regarding the property of a certain substance, for example, "a certain film is an insulating film"
Suppose that it is described as In that case, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an organic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the insulating film is an inorganic insulating film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a conductive film. Alternatively, for example, one embodiment of the invention can be defined as excluding the case where the film is a semiconductor film.

As another specific example, for a certain laminated structure, it is assumed that "a certain film is provided between the A film and the B film". In that case, for example, it is possible to define the invention as excluding the case where the film is a laminated film of four or more layers. Alternatively, for example, it is possible to define the invention as excluding the case where a conductive film is provided between the A films.

Note that, in this specification and the like, it is possible to configure one aspect of the invention by extracting a part of a diagram or text described in one embodiment. Therefore, when a figure or text describing a certain part is described, the content of the part of the figure or text is also disclosed as one aspect of the invention, and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, active elements (transistors, diodes, etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operation methods, manufacturing methods In the drawings or sentences in which one or more of etc. are described, a part thereof can be taken out to constitute one aspect of the invention. For example, N (N
is an integer) of circuit elements (transistors, capacitive elements, etc.), M (M is an integer, M<N) circuit elements (transistors, capacitive elements, etc.) are extracted, It is possible to configure one aspect of the invention. As another example, one embodiment of the invention is configured by extracting M layers (M is an integer and M<N) from a cross-sectional view configured with N layers (N is an integer). It is possible to As yet another example, one aspect of the invention is constructed by extracting M elements (M is an integer and M<N) from a flow chart having N elements (N is an integer). It is possible to As yet another example, from a sentence that states "A has B, C, D, E, or F," some elements can be arbitrarily extracted to read, "A has B and E has", "A has E and F", "A has C and E and F"
, or one aspect of the invention such as "A has B, C, D and E".

In this specification and the like, when at least one specific example is described in a diagram or text described in a certain embodiment, it is easy for a person skilled in the art to derive a generic concept of the specific example. be understood by Therefore, when at least one specific example is described in a drawing or text described in a certain embodiment, the broader concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. And one aspect of the invention can be said to be clear.

In addition, in this specification etc., at least the contents described in the figure (may be part of the figure)
is disclosed as one aspect of the invention, and can constitute one aspect of the invention. Therefore, as long as a certain content is described in a drawing, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention even if it is not described using sentences. It is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. and,
It can be said that one aspect of the invention is clear.

Example 1 In this example, evaluation results of an oxide semiconductor film that is one embodiment of the present invention will be described.

[Manufacturing method]
A silicon wafer was thermally oxidized to form a silicon oxide film with a thickness of 100 nm. After that, as an oxide semiconductor film, an In--Ga--Zn oxide was formed with a thickness of 100 nm by a sputtering method. As conditions for the sputtering method, a polycrystalline In--Ga--Zn oxide of In:Ga:Zn=1:1:1 (atomic ratio) was used as the target, the power supply was 0.5 kW (DC), and the substrate and The distance between targets was 60 mm. Argon and oxygen are used as film forming gases,
The respective flow rates were 30 sccm for argon and 15 sccm for oxygen. pressure is 0.4
Pa. The substrate temperature was 170° C. for the sample E1-1 and 300° C. for the sample F1-1.

Next, heat treatment was performed. The heat treatment conditions were as follows: heat treatment was performed at 450° C. in a nitrogen atmosphere for 1 hour, and then heat treatment was performed in the same treatment chamber at 450° C. in an oxygen atmosphere for 1 hour.

[XRD evaluation]
Next, the results of evaluation using an XRD apparatus will be described. The XRD device is a multifunctional thin film material evaluation X-ray diffraction device D8 DISCOVER Hybrid (manufactured by Bruker AXS).
was used to evaluate each sample. FIG. 43 shows the analysis results by the Out-Of-Plane method. FIG. 43A shows the results of the sample E1-1, and FIG. 43B shows the results of the sample F1-1. A peak was observed near 2θ=31° in all samples. There was a tendency for the peak to be broad under the condition of film formation at 170°C, and to become sharper under the condition of film formation at 300°C. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, it is suggested that the number of crystals in the oxide semiconductor film having c-axis orientation increases as the film formation temperature increases.

[Film density evaluation]
Next, the film density was measured. XRR (X-ray reflectance method: X-ray R
(reflectometry) was used. The resulting film density was 6.18 [g for sample E1-1.
/cm ³ ], and sample F1-1 was 6.36 [g/cm ³ ]. A fine and good film was obtained under any conditions.

[Nanobeam electron diffraction]
Next, samples E1-1 and F1-1 were analyzed by nanobeam electron diffraction. "HF-2000" manufactured by Hitachi High-Technologies was used for the acquisition of electron diffraction. The acceleration voltage was set to 200 kV.

A transmission electron diffraction pattern was obtained while the top surface of each sample having an oxide semiconductor film was scanned by gradually moving the sample stage. Probe diameter is 1 nm as electron beam
of nanobeam electron beam was used. Also, the same measurement was performed at three locations for each sample. That is, each sample was scanned a total of three times from scan1 to scan3.

A diffraction pattern was observed while scanning at a speed of 5 nm/sec, and a moving image was acquired. next,
The diffraction pattern observed in the obtained moving image was converted into a still image every 0.5 seconds. The converted still images were analyzed and classified into three patterns: nc-OS film patterns, CAAC-OS film patterns, and spinel-type crystal structure patterns. Table 3 shows the number of images classified into each pattern in Scan1 to Scan3 for sample E1-1 and sample F1-1. Also, the results of scan 1 of the electron diffraction pattern of sample E1-1 are shown in FIGS.
The results of -1 scan1 are shown in FIGS. Among the results of electron diffraction shown in FIGS. 44 to 48, those judged to be the patterns of the CAAC-OS film are shown enclosed by dashed lines. In addition, among the results of electron diffraction shown in FIGS. 49 to 53, those judged to be patterns of the nc-OS film are shown surrounded by broken lines.

Sample E1-1 exhibited a high nc ratio of 90% or more. It was found that the nc ratio was increased by lowering the deposition temperature. Also, in any sample, n
The sum of the c ratio and the CAAC ratio was 100%.

In this example, the film density evaluation result of In-Ga-Zn oxide and TDS (Thermal
Desorption Spectroscopy (Temperature Desorption Spectroscopy) analysis results are shown.

An In--Ga--Zn oxide film was formed by a sputtering method on a quartz substrate that had been cleaned in advance. The target is polycrystalline In- of In:Ga:Zn=1:1:1 (atomic ratio)
Ga--Zn oxide was used. The film formation conditions were as follows: power source power was 100 W; argon and oxygen were used as film formation gases;
%. The pressure was set to 0.4 Pa or 1.0 Pa. The substrate temperature was room temperature. Table 4 shows film formation conditions and film densities. sampleB and sample
In D, a heat treatment was performed at 450° C. after forming an In—Ga—Zn oxide film by a sputtering method. XRR was used to evaluate film density. As shown in Table 4, sample C exhibited a high density of 6 [g/cm ³ ] or more.

Next, TDS analysis was performed on sampleA to sampleD. molecular weight is 1
54(A) and (B) show the amount of degassing of No. 8. Outgassing with a molecular weight of 18 is believed to be from _H2O . The release amount was large in sample A, and the release amount was decreased in sample B subjected to heat treatment. Sample C, which has a high film density, is considered to have a small amount of gas released even without heat treatment and a small amount of water contained in the film.

Next, for sampleA to sampleD, the crystal size (
crystal size) was evaluated. The crystal size was calculated by observing the cross section using a TEM. FIG. 55 shows the results of evaluating the relationship between the cumulative dose and the crystal size by performing electron beam irradiation using a TEM. In sample A, crystals tended to grow larger each time electron beam irradiation was performed. Here, the crystal size before electron beam irradiation may be set to a value where the cumulative dose is 0 [e ⁻ /nm ² ] on the approximate line shown in FIG. 55, for example. In sample B subjected to heat treatment, the change in crystal size was small. In addition, sample C and sample with high film density
In D, no significant change in the crystal size was observed in the range of the cumulative dose of the electron beam up to 4.2×10 ⁸ [e ⁻ /nm ² ].

In this example, the stability of the oxide semiconductor film was evaluated. Sample 1, Sample 2 and Sample 3
is shown below.

First, an In--Ga--Z film having a thickness of 100 nm was formed on a quartz substrate by RF sputtering.
An n-oxide is deposited. The target is a polycrystalline In--Ga--Zn oxide (In:Ga:Z
n=1:1:1 [atomic number ratio]) was used. The deposition gas was oxygen gas at 2 sccm and argon gas at 98 sccm. Moreover, electric power was set to 100W. Also, the substrate temperature during film formation was room temperature. Here, sample 1 was formed at a film forming pressure of 0.4 Pa. In addition, sample 2 was formed at a film forming pressure of 1.0 Pa.

In Sample 3, In—Ga with a thickness of 100 nm was deposited on a quartz substrate by a DC sputtering method.
- Deposit Zn oxide. The target is In--Ga--Zn oxide (In:Ga:Zn=
1:1:1 [atomic ratio]) was used. As the film forming gas, 10 sccm of oxygen gas and 20 sccm of argon gas were used. Moreover, electric power was set to 200W. Also, the substrate temperature during film formation was set to 300.degree. The film formation pressure was set to 0.4 Pa.

Next, heat treatment was performed for 1 hour in an atmosphere containing oxygen and nitrogen. The heat treatment temperature is 25
Five conditions of 0°C, 300°C, 350°C, 400°C, and 450°C were used. After that, the film densities of Samples 1, 2, and 3 were measured, including the condition where no heat treatment was performed. For measurement of the film density, XRR using an X-ray diffractometer D8 ADVANCE manufactured by Bruker AXS
was used. The results of sample 1 are shown in FIG. 58(A), the results of sample 2 are shown in FIG. 58(B), and the results of sample 3 are shown in FIG. 58(C). The horizontal axis is the temperature of the heat treatment. The film density of sample 1 is 5.9 g/c
m ³ to 6.1 g/cm ³ . The film density of sample 2 is from 5.6 g/ ^cm3 to 5.8 g/cm3.
cm ³ range. The film density of Sample 3 ranged from 6.2 g/cm ³ to 6.4 g/cm ³ .

Next, samples 1, 2 and 3 were etched using an aqueous solution obtained by diluting phosphoric acid 100 times with pure water. The etching rate was measured by measuring the thickness before and after etching. The results of sample 1 are shown in FIG. 59A, the results of sample 2 are shown in FIG. 59B, and the results of sample 3 are shown in FIG. 59C. It was found that sample 1 and sample 2 had lower etching rates as the heat treatment temperature was higher. It was found that Sample 3 showed little difference due to the heat treatment temperature. In addition, the sample 1 not subjected to heat treatment than the sample 2 subjected to heat treatment,
It was found that the etching rate was lowered. It was also found that the etching rate of sample 3, which was not subjected to heat treatment, was lower than that of sample 1, which was subjected to heat treatment.

Next, samples 1, 2 and 3 were subjected to TDS analysis, and the amount of released gas (water) with a mass-to-charge ratio of 18 was measured. For TDS analysis, a temperature programmed desorption spectrometer TDS-12 manufactured by Electronic Science Co., Ltd.
00 was used. The results of sample 1 are shown in FIG. 60(A), the results of sample 2 are shown in FIG.
The results are shown in FIG. 60(C). Samples 1, 2 and 3 showed that the higher the heat treatment temperature, the less the amount of degassing with a mass-to-charge ratio of 18. In addition, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in sample 1, which was not subjected to heat treatment, than in sample 2, which was subjected to heat treatment. In addition, it was found that the amount of degassing with a mass-to-charge ratio of 18 was smaller in Sample 3, which was not subjected to heat treatment, than in Sample 1, which was subjected to heat treatment.

Next, the hydrogen concentrations of samples 1 and 2 were measured. The hydrogen concentration was measured by SIMS.
For SIMS, IMS 7fR manufactured by CAMECA was used. The results of sample 1 are shown in FIGS. 61(A) and 68(A), and the results of sample 2 are shown in FIGS. 61(B) and 68(B). here,
In FIGS. 68A and 68B, the horizontal axis indicates the depth from the film surface, and the vertical axis indicates the hydrogen concentration. In addition, FIGS. 61A and 61B show average values of hydrogen concentrations from a depth of 10 nm to 60 nm. In addition, in FIGS. 68A and 68B, after the region where the hydrogen concentration abruptly changes near the depth of 80 nm, the In—Ga—Zn oxide film does not remain and the quartz substrate is measured. There is a possibility that In addition, the region of less than 10 nm may be affected by surface conditions. Therefore, the hydrogen concentration of the In--Ga--Zn oxide film is, for example, 10 mm deep.
It is preferable to represent the mean value from nm to 60 nm. It was found that in Samples 1 and 2, the higher the heat treatment temperature, the lower the hydrogen concentration. Further, it was found that the hydrogen concentration of sample 1, which was not subjected to heat treatment, was lower than that of sample 2, which was subjected to heat treatment.

Next, changes in crystal size due to heat treatment of samples 1, 2 and 3 were measured by TEM. The crystal size is indicated by an average value of 20 to 45 points. Hitachi transmission electron microscope H-9000NAR was used as the TEM. The results of sample 1 are shown in FIG. 62(A), and the results of sample 2 are shown in FIG.
2(B) and sample 3 are shown in FIG. 62(C). It was found that sample 1 had a crystal size of about 1.4 nm regardless of the heat treatment temperature. Sample 2 had a crystal size of about 1.2 nm when heat treatment was not performed (see FIG. 67), but grew to about 1.3 nm by heat treatment at 250° C. and further heated at 300° C. It grew to about 1.6 nm by the treatment. Also, no change in crystal size was observed in the range of 300°C to 450°C. Also in sample 3, the crystal size was 1.5 to 1.6 nm regardless of the heat treatment temperature.
Met.

Next, changes in crystal size of samples 1, 2 and 3 due to electron beam irradiation were measured by TEM. The results of Sample 1 are shown in FIG. 63A, the results of Sample 2 are shown in FIG. 63B, and the results of Sample 3 are shown in FIG. 63C. Samples 1 and 3 showed almost no change in crystal size regardless of the temperature of heat treatment and even with electron beam irradiation. Sample 2 showed an increase in crystal size due to electron beam irradiation. In addition, this tendency was more conspicuous as the heat treatment temperature was lower.

Looking at the change in crystal size due to heat treatment and the change in crystal size due to electron beam irradiation,
It can be seen that samples 1 and 3 have higher stability than sample 2. When the samples 1, 2, and 3 are compared with the above-described structure classification, the sample 1 is an nc-OS film, the sample 2 is an a-like OS film, and the sample 3 is a CAAC-OS.

Thus, the nc-OS film has a higher film density, a lower etching rate, less water outgassing, and a lower hydrogen concentration than the a-like OS film. Moreover, the difference cannot be filled by heat treatment after film formation. That is, it is important to use an oxide semiconductor film, which is an nc-OS film, for a transistor.

In this example, the localized levels of the nc-OS film were evaluated. Evaluation of the localized level is based on CPM (Con
stunt photocurrent method) measurement.

For CPM measurement, the gate electrode (tungsten) on the glass substrate and the nc-
an OS film, a gate insulator (silicon oxynitride) between the gate electrode and the nc-OS film, n
A pair of electrodes (laminated body formed of tungsten, aluminum, and titanium in this order) in contact with the c-OS film; Laminate) and a sample having the above were prepared. Note that nc-OS
Film formation was performed with a thickness of 35 nm by an AC sputtering method. The target is In
-Ga--Zn oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) was used. The film forming gas was 10% by volume oxygen gas and 90% by volume argon gas. Also, the power is 2
. 5 kW. Also, the substrate temperature during film formation was room temperature. Moreover, the film-forming pressure was set to 0.6 Pa.

Next, heat treatment was performed on the manufactured sample. The heat treatment was performed in a nitrogen atmosphere for 1 hour and then in an atmosphere containing oxygen and nitrogen for 1 hour.

In the CPM measurement, a voltage is applied between a pair of electrodes provided in contact with the nc-OS film, and the amount of light irradiated to the sample surface between the terminals is adjusted so that the photocurrent value is constant. Derive the absorption coefficient. Here, the absorption coefficient was derived for each wavelength. In CPM measurement, the absorption coefficient increases at energy (converted from wavelength) according to the localized level density. By multiplying the increment of the absorption coefficient by a constant, the localized level density of the sample can be derived.

Further, by removing the light absorption due to the band tail (Urbach tail) from the curve of the light absorption spectrum, the absorption coefficient α due to the local level can be calculated from the following equation.

α=∫[(α(E)−α _u )/E]dE

Here, E is the energy, α(E) is the absorption coefficient at each energy, and α _u is the absorption coefficient due to the Urbach tail.

The inclination of the Urbach tail is called Urbach energy. It can be said that the lower the Urbach energy is, the less the defects are, and the more ordered the semiconductor film is, in which the tail of the level at the band edge of the valence band is steeper.

FIG. 64 shows the result of fitting the absorption coefficient (dotted line) measured by the spectrophotometer and the absorption coefficient (solid line) measured by CPM in an energy range equal to or higher than the energy gap of the oxide semiconductor film. FIG. 64A shows the result of a sample heat-treated at 300° C. after film formation, FIG. 64B shows the result of a sample heat-treated at 400° C. after film formation, and FIG.
C) shows the results of a sample heat-treated at 450° C. after film formation. The Urbach energies obtained from the absorption coefficients measured by CPM are 72.65 meV and 69 meV, respectively.
. 45 meV and 70.32 meV.

Further, the integral value of the absorption coefficient was derived by subtracting the background (thin dotted line) from the absorption coefficient derived by the CPM measurement in FIG. The results are shown in FIG. The absorption coefficients due to localized levels are 6.27×10 ⁻¹ cm ⁻¹ , 4.19×10 ⁻¹ cm ⁻¹ and 2.29, respectively.
×10 ⁻¹ cm ⁻¹ . FIG. 66 shows the relationship between the heat treatment temperature and the absorption coefficient. Figure 66
From this, it can be seen that the higher the temperature of the heat treatment, the smaller the absorption coefficient, and hence the smaller the localized level density.

11 Region 12 Region 13 Region 14 Region 15 Region 16 Region 21 Perpendicular line 22 Perpendicular line 23 Perpendicular line 50 Substrate 51 Insulating film 100 Transistor 101 Semiconductor layer 101a Insulator layer 101b Semiconductor layer 101c Insulator layer 102 Gate insulating film 103 Gate electrode 104a Conductive layer 104b Conductive layer 105 Conductive layer 111 Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 116 Insulating film 123 Plug 124 Wiring 130 Transistor 131 Semiconductor substrate 132 Semiconductor layer 133a Low resistance layer 133b Low resistance layer 134 Gate insulating film 135 Gate electrode 136 Insulating film 137 Insulating film 138 Insulating film 139 Plug 140 Plug 143 Conductive layer 150 Capacitive element 151 Conductive layer 152a Conductive layer 152b Conductive layer 160 Transistor 164 Plug 165 Plug 166 Wiring 171a Low resistance layer 171b Low resistance layer 176a Region 176b Region 181 Element isolation layer 190 Transistor 191 Transistor 201 Semiconductor layer 201a Semiconductor layer 201b Semiconductor layer 202 Gate insulating film 202a Gate insulating film 202b Gate insulating film 203a Gate electrode 203b Electrode 204a Conductive layer 204b Conductive layer 214 Insulating film 215 Insulating film 216 Insulating film 218 Insulating film 251 Conductive layer 281 hard mask 321 plug 322 plug 324 region 501 pixel circuit 502 pixel portion 504 driver circuit portion 504a gate driver 504b source driver 506 protection circuit 507 terminal portion 550 transistor 552 transistor 554 transistor 560 capacitive element 562 capacitive element 570 liquid crystal element 572 light emitting element 610 Electron gun chamber 612 Optical system 614 Sample chamber 616 Optical system 618 Camera 620 Observation chamber 622 Film chamber 624 Electron 632 Fluorescent plate 700 Display device 701 Substrate 702 Pixel unit 704 Source driver circuit unit 705 Substrate 706 Gate driver circuit unit 708 FPC terminal unit 710 Signal Wire 711 Wiring portion 712 Sealing material 716 FPC
730 insulating film 732 sealing film 734 insulating film 736 colored film 738 light shielding film 750 transistor 752 transistor 760 connection electrode 764 insulating film 766 insulating film 768 insulating film 770 planarization insulating film 772 conductive layer 774 conductive layer 775 liquid crystal element 776 liquid crystal layer 778 Structural body 780 Anisotropic conductive layer 782 Light emitting element 784 Conductive layer 786 EL layer 788 Conductive layer 790 Capacitor element 790a Capacitor element 790b Capacitor element 800 RF tag 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM
901 housing 902 housing 903 display unit 904 display unit 905 microphone 906 speaker 907 operation keys 908 stylus 911 housing 912 housing 913 display unit 914 display unit 915 connection unit 916 operation keys 921 housing 922 display unit 923 keyboard 924 pointing device 931 Housing 932 Door for refrigerator compartment 933 Door for freezer compartment 941 Housing 942 Housing 943 Display section 944 Operation key 945 Lens 946 Connection section 951 Vehicle body 952 Wheel 953 Dashboard 954 Light 2100 Transistor 2200 Transistor 4000 RF tag 5100 Pellet 5100a Pellet 5100b pellet 5101 ion 5120 substrate 5130 target 8000 display module 8001 upper cover 8002 lower cover 8003 FPC
8004 Touch panel 8005 FPC
8006 display panel 8007 backlight 8008 light source 8009 frame 8010 printed circuit board 8011 battery

Claims (6)

a first layer having a first channel forming region;
a first insulating layer on the first layer;
a first conductive layer on the first insulating layer;
a second insulating layer on the first conductive layer;
a second conductive layer on the second insulating layer;
a second layer having a second channel forming region;
a third insulating layer over the second layer;
a third conductive layer on the third insulating layer;
a fourth insulating layer on the third insulating layer and on the third conductive layer;
a fourth conductive layer in contact with the first layer through openings in the first insulating layer and the second insulating layer;
the first layer comprises silicon;
the second conductive layer has a region that functions as one of the source or drain of a transistor;
the second layer is electrically connected to the second conductive layer;
the second layer comprises indium, gallium and zinc;
the third conductive layer has a region that functions as a gate of the transistor;
In a cross-sectional view, the third insulating layer extends beyond the edge of the third conductive layer;
the second conductive layer overlaps the first conductive layer;
The semiconductor device, wherein the fourth insulating layer is in contact with the top surface and side surfaces of the third conductive layer, and is in contact with the top surface and side surfaces of the third insulating layer. a first layer having a first channel forming region;
a first insulating layer on the first layer;
a first conductive layer on the first insulating layer;
a second insulating layer on the first conductive layer;
a second conductive layer on the second insulating layer;
a second layer having a second channel forming region;
a third insulating layer over the second layer;
a third conductive layer on the third insulating layer;
a fourth conductive layer in contact with the first layer through openings in the first insulating layer and the second insulating layer;
the first layer comprises silicon;
the second conductive layer has a region that functions as one of the source or drain of a transistor;
the second layer is electrically connected to the second conductive layer;
the second layer comprises indium, gallium and zinc;
the third conductive layer has a region that functions as a gate of the transistor;
The semiconductor device, in cross-sectional view, wherein the third insulating layer extends beyond the edge of the third conductive layer. a first layer having a first channel forming region;
a first insulating layer on the first layer;
a first conductive layer on the first insulating layer;
a second insulating layer on the first conductive layer;
a second conductive layer on the second insulating layer;
a second layer having a second channel forming region;
a third insulating layer over the second layer;
a third conductive layer on the third insulating layer;
a fifth conductive layer electrically connected to the first layer through openings in the first insulating layer and the second insulating layer;
the first layer comprises silicon;
the second conductive layer has a region that functions as one of the source or drain of a transistor;
the second layer is electrically connected to the second conductive layer;
the second layer comprises indium, gallium and zinc;
the third conductive layer has a region that functions as a gate of the transistor;
In a cross-sectional view, the third insulating layer extends beyond the edge of the third conductive layer;
The fifth conductive layer includes a region overlapping with the first layer, a region overlapping with the first conductive layer, a region overlapping with the second conductive layer, a region overlapping with the second layer, and a region overlapping with the third conductive layer. In claim 2 or claim 3,
a fourth insulating layer on the third insulating layer and on the third conductive layer;
The semiconductor device, wherein the fourth insulating layer is in contact with the top surface and side surfaces of the third conductive layer, and is in contact with the top surface and side surfaces of the third insulating layer. In any one of claims 1 to 4,
The semiconductor device, wherein the first conductive layer functions as a gate electrode of the second transistor. In any one of claims 1 to 5,
The second layer has a plurality of crystals,
the second layer comprises indium, gallium, and zinc;
The atomic ratio of indium to gallium and zinc contained in the second layer satisfies indium:element M:zinc=x:y:z,
The x, the y, and the z are the first coordinate (x: y: z = 8: 14: 7) and the second coordinate in the equilibrium diagram with the three elements of indium, gallium, and zinc as vertices. (x: y: z = 2: 4: 3), the third coordinate (x: y: z = 2: 5: 7), and the fourth coordinate (x: y: z = 51: 149: 300 ), fifth coordinates (x:y:z=46:288:833), sixth coordinates (x:y:z=0:2:11), and seventh coordinates (x:y: z = 0:0:1), the eighth coordinate (x:y:z = 1:0:0), and the first coordinate are connected in order with a line segment. ratio, wherein the range includes the first coordinate to the sixth coordinate and excludes the seventh coordinate and the eighth coordinate;
The electron diffraction pattern observed by irradiating the formation surface of the second layer with an electron beam having a probe diameter half-width of 1 nm is a pattern in which the spots are not arranged symmetrically or the spots are circular. A semiconductor device, which is a pattern arranged to draw

Images