JP6602579B2 - 半導体装置およびシステム - Google Patents
半導体装置およびシステム Download PDFInfo
- Publication number
- JP6602579B2 JP6602579B2 JP2015141224A JP2015141224A JP6602579B2 JP 6602579 B2 JP6602579 B2 JP 6602579B2 JP 2015141224 A JP2015141224 A JP 2015141224A JP 2015141224 A JP2015141224 A JP 2015141224A JP 6602579 B2 JP6602579 B2 JP 6602579B2
- Authority
- JP
- Japan
- Prior art keywords
- reception
- transmission
- data
- mode
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8053—Vector processors
- G06F15/8076—Details on data register access
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/502—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two
- H03K23/507—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits with a base or a radix other than a power of two with a base which is a non-integer
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/44—Transmit/receive switching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Information Transfer Systems (AREA)
- Microcomputers (AREA)
- Communication Control (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015141224A JP6602579B2 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置およびシステム |
| US15/144,580 US10409749B2 (en) | 2015-07-15 | 2016-05-02 | Semiconductor device and system provided with a communication interface |
| CN201610478818.3A CN106354674B (zh) | 2015-07-15 | 2016-06-27 | 半导体装置和系统 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015141224A JP6602579B2 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置およびシステム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017021749A JP2017021749A (ja) | 2017-01-26 |
| JP2017021749A5 JP2017021749A5 (enExample) | 2018-07-05 |
| JP6602579B2 true JP6602579B2 (ja) | 2019-11-06 |
Family
ID=57775925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015141224A Active JP6602579B2 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置およびシステム |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10409749B2 (enExample) |
| JP (1) | JP6602579B2 (enExample) |
| CN (1) | CN106354674B (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6786449B2 (ja) * | 2017-06-29 | 2020-11-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US10474822B2 (en) * | 2017-10-08 | 2019-11-12 | Qsigma, Inc. | Simultaneous multi-processor (SiMulPro) apparatus, simultaneous transmit and receive (STAR) apparatus, DRAM interface apparatus, and associated methods |
| US20240078312A1 (en) * | 2017-10-08 | 2024-03-07 | Qsigma, Inc. | Simultaneous Multi-Processor (SiMulPro) Apparatus, Simultaneous Transmit And Receive (STAR) Apparatus, DRAM Interface Apparatus, and Associated Methods |
| WO2019117960A1 (en) * | 2017-12-15 | 2019-06-20 | Hewlett-Packard Development Company, L.P. | Actuation of data transmission lanes between states |
| JP7172217B2 (ja) * | 2018-07-17 | 2022-11-16 | 大日本印刷株式会社 | セキュアエレメント、通信方法、通信プログラム及び通信システム |
| CN110412913A (zh) * | 2019-07-17 | 2019-11-05 | 江苏吉泰科电气股份有限公司 | 上位机在线切换dsp烧写程序控制系统 |
| JP7295780B2 (ja) * | 2019-11-05 | 2023-06-21 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその動作方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2544385B2 (ja) * | 1987-05-27 | 1996-10-16 | 株式会社日立製作所 | 通信制御装置 |
| JP3019740B2 (ja) * | 1994-12-27 | 2000-03-13 | 日本電気株式会社 | シリアルインターフェースおよびシリアルデータ転送システム |
| US5790895A (en) * | 1996-10-18 | 1998-08-04 | Compaq Computer Corporation | Modem sharing |
| US6381661B1 (en) * | 1999-05-28 | 2002-04-30 | 3Com Corporation | High throughput UART to DSP interface having Dual transmit and receive FIFO buffers to support data transfer between a host computer and an attached modem |
| KR100480084B1 (ko) * | 2003-07-23 | 2005-04-06 | 엘지전자 주식회사 | 범용 직렬버스를 이용한 데이터 전송 시스템 |
| JP4138693B2 (ja) | 2004-03-31 | 2008-08-27 | 株式会社東芝 | フロー制御の初期化方法および情報処理装置 |
| DE102004057756B4 (de) * | 2004-11-30 | 2009-08-06 | Advanced Micro Devices Inc., Sunnyvale | USB-Steuerungseinrichtung mit OTG-Steuerungseinheit |
| JP5179834B2 (ja) * | 2007-10-31 | 2013-04-10 | ルネサスエレクトロニクス株式会社 | 半導体装置及びデータ処理システム |
| JP2010257280A (ja) * | 2009-04-27 | 2010-11-11 | Renesas Electronics Corp | シリアル制御装置、半導体装置及びシリアルデータの転送方法 |
| JP5414479B2 (ja) | 2009-11-27 | 2014-02-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US9296009B2 (en) * | 2012-07-13 | 2016-03-29 | Nordson Corporation | Adhesive dispensing system having metering system including variable frequency drive and closed-loop feedback control |
| US9059779B2 (en) * | 2012-11-27 | 2015-06-16 | Aviacomm Inc. | Serial digital interface between an RF transceiver and a baseband chip |
| JP6316593B2 (ja) * | 2014-01-07 | 2018-04-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6354387B2 (ja) * | 2014-06-30 | 2018-07-11 | 富士通株式会社 | 情報処理装置、情報処理システム及び割込装置制御方法 |
-
2015
- 2015-07-15 JP JP2015141224A patent/JP6602579B2/ja active Active
-
2016
- 2016-05-02 US US15/144,580 patent/US10409749B2/en active Active
- 2016-06-27 CN CN201610478818.3A patent/CN106354674B/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017021749A (ja) | 2017-01-26 |
| US10409749B2 (en) | 2019-09-10 |
| CN106354674B (zh) | 2021-05-07 |
| CN106354674A (zh) | 2017-01-25 |
| US20170019142A1 (en) | 2017-01-19 |
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