JP6555082B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6555082B2 JP6555082B2 JP2015215110A JP2015215110A JP6555082B2 JP 6555082 B2 JP6555082 B2 JP 6555082B2 JP 2015215110 A JP2015215110 A JP 2015215110A JP 2015215110 A JP2015215110 A JP 2015215110A JP 6555082 B2 JP6555082 B2 JP 6555082B2
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- electrode
- semiconductor device
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Nonlinear Science (AREA)
- Junction Field-Effect Transistors (AREA)
Description
(半導体装置)
次に、第1の実施の形態における半導体装置について説明する。本実施の形態における半導体装置は、基板の上に核形成層、バッファ層、電子走行層、電子供給層等の窒化物半導体膜が形成されており、電子供給層の上には、ゲート電極、ソース電極、ドレイン電極が形成されている。本実施の形態においては、これらを形成した後、基板をダイシング加工し、半導体装置ごとに分離したものを半導体チップ10と記載する。尚、半導体装置における半導体層の構造については後述する。
次に、本実施の形態における半導体装置の半導体層における構造について説明する。本実施の形態における半導体装置は、高出力化のため、半導体材料としてバンドギャップの広い窒化物半導体が用いられている。具体的には、図8に示されるように、シリコン(Si)基板等の基板110の上に、不図示の核形成層、バッファ層111、電子走行層121、電子供給層122が形成されている。電子供給層122の上には、ゲート電極21、ソース電極22、ドレイン電極23が形成されている。ソース電極22及びドレイン電極は23は、2つに分割されているが、便宜上、図8では、各々その一方のみが描かれている。また、図8に示されるゲート電極21は、櫛歯状のゲート電極21における櫛歯の部分21aである。本願においては、電子走行層121を第1の半導体層と記載し、電子供給層122を第2の半導体層と記載する場合がある。
次に、第2の実施の形態について説明する。本実施の形態における半導体装置は、図9に示されるように、ソース電極及びドレイン電極がすべて分割されており、分割されたソース電極及びドレイン電極の間には、各々高熱伝導部が形成されている構造の半導体装置である。
次に、第3の実施の形態について説明する。本実施の形態は、半導体デバイス、電源装置及び高周波増幅器である。
(付記1)
基板の上に形成された第1の半導体層と、
前記第1の半導体層の上に形成された第2の半導体層と、
前記第2の半導体層の上に形成されたゲート電極、ソース電極及びドレイン電極と、
を有する半導体チップを含む半導体装置において、
前記ゲート電極は、複数の櫛歯の部分を有する櫛形状に形成されており、
前記ゲート電極における前記櫛歯の部分の間隔は、前記半導体チップの中央部分から周辺部分に向かって狭くなっており、
前記ゲート電極における前記櫛歯の部分の両側のうちの一方には前記ソース電極が、他方には前記ドレイン電極が、各々形成されており、
前記ゲート電極における前記櫛歯の部分の間に形成された各々の前記ソース電極及び前記ドレイン電極の平面視における面積は略同一であることを特徴とする半導体装置。
(付記2)
前記櫛歯の部分の間に形成された各々の前記ソース電極及び前記ドレイン電極の面積の平均に対する各々の前記ソース電極及び前記ドレイン電極の面積は、0.7以上、1.6以下であることを特徴とする、付記1に記載の半導体装置。
(付記3)
前記櫛歯の部分の間に形成された各々の前記ソース電極及び前記ドレイン電極の面積の平均に対する各々の前記ソース電極及び前記ドレイン電極の面積は、0.85以上、1.25以下であることを特徴とする付記1に記載の半導体装置。
(付記4)
各々の前記ソース電極及び前記ドレイン電極のうちの一部または全部は、2つに分割されていることを特徴とする付記1から3のいずれかに記載の半導体装置。
(付記5)
前記ソース電極の2つに分割されている部分は電気的に接続されており、前記ドレイン電極の2つに分割されている部分は電気的に接続されていることを特徴とする付記4に記載の半導体装置。
(付記6)
前記ソース電極の2つに分割されている部分の間、及び、前記ドレイン電極の2つに分割されている部分の間には、絶縁体材料により高熱伝導部が形成されていることを特徴とする付記4または5に記載の半導体装置。
(付記7)
前記ゲート電極、前記ソース電極及びドレイン電極の上には、パッシベーション膜が形成されており、
前記高熱伝導部は、前記パッシベーション膜の上にも形成されていることを特徴とする付記6に記載の半導体装置。
(付記8)
前記ソース電極の2つに分割されている部分の電極幅、及び、前記ドレイン電極の2つに分割されている部分の電極幅は、0.6μm以上であることを特徴とする付記4から7のいずれかに記載の半導体装置。
(付記9)
前記ゲート電極における各々の櫛歯の部分のゲート幅は一定であり、
前記ゲート電極の櫛歯の部分と、前記櫛歯の部分に最も近い前記ソース電極との間隔は一定であり、
前記ゲート電極の櫛歯の部分と、前記櫛歯の部分に最も近い前記ドレイン電極との間隔は一定であることを特徴とする付記1から8のいずれかに記載の半導体装置。
(付記10)
前記第1の半導体層及び前記第2の半導体層は、窒化物半導体により形成されていることを特徴とする付記1から9のいずれかに記載の半導体装置。
(付記11)
前記第1の半導体層は、GaNを含む材料により形成されており、
前記第2の半導体層は、AlGaN、InAlN、InAlGaNのいずれかを含む材料により形成されていることを特徴とする付記1から9のいずれかに記載の半導体装置。
(付記12)
付記1から11のいずれかに記載の半導体装置を有することを特徴とする電源装置。
(付記13)
付記1から11のいずれかに記載の半導体装置を有することを特徴とする増幅器。
21 ゲート電極
21a 櫛歯の部分
21b 接続部分
22 ソース電極
23 ドレイン電極
110 基板
111 バッファ層
121 電子走行層(第1の半導体層)
121a 2DEG
122 電子供給層(第2の半導体層)
Claims (7)
- 基板の上に形成された第1の半導体層と、
前記第1の半導体層の上に形成された第2の半導体層と、
前記第2の半導体層の上に形成されたゲート電極、ソース電極及びドレイン電極と、
を有する半導体チップを含む半導体装置において、
前記ゲート電極は、複数の櫛歯の部分を有する櫛形状に形成されており、
前記ゲート電極における前記櫛歯の部分の間隔は、前記半導体チップの中央部分から周辺部分に向かって狭くなっており、
前記ゲート電極における前記櫛歯の部分の両側のうちの一方には前記ソース電極が、他方には前記ドレイン電極が、各々形成されており、
平面視において、前記ゲート電極における前記櫛歯の部分の間に形成された各々の前記ソース電極及び前記ドレイン電極の面積の平均に対する各々の前記ソース電極及び前記ドレイン電極の面積は、0.7以上、1.6以下であることを特徴とする半導体装置。 - 前記櫛歯の部分の間に形成された各々の前記ソース電極及び前記ドレイン電極の面積の平均に対する各々の前記ソース電極及び前記ドレイン電極の面積は、0.85以上、1.25以下であることを特徴とする請求項1に記載の半導体装置。
- 各々の前記ソース電極及び前記ドレイン電極のうちの一部または全部は、2つに分割されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記ソース電極の2つに分割されている部分の間、及び、前記ドレイン電極の2つに分割されている部分の間には、絶縁体材料により高熱伝導部が形成されていることを特徴とする請求項3に記載の半導体装置。
- 前記ゲート電極、前記ソース電極及びドレイン電極の上には、パッシベーション膜が形成されており、
前記高熱伝導部は、前記パッシベーション膜の上にも形成されていることを特徴とする請求項4に記載の半導体装置。 - 前記ソース電極の2つに分割されている部分の電極幅、及び、前記ドレイン電極の2つに分割されている部分の電極幅は、0.6μm以上であることを特徴とする請求項3から5のいずれかに記載の半導体装置。
- 前記第1の半導体層及び前記第2の半導体層は、窒化物半導体により形成されていることを特徴とする請求項1から6のいずれかに記載の半導体装置。
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