JP6534851B2 - インタフェースユニット - Google Patents

インタフェースユニット Download PDF

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Publication number
JP6534851B2
JP6534851B2 JP2015084375A JP2015084375A JP6534851B2 JP 6534851 B2 JP6534851 B2 JP 6534851B2 JP 2015084375 A JP2015084375 A JP 2015084375A JP 2015084375 A JP2015084375 A JP 2015084375A JP 6534851 B2 JP6534851 B2 JP 6534851B2
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JP
Japan
Prior art keywords
data
unit
memory
interface unit
descriptor
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JP2015084375A
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English (en)
Japanese (ja)
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JP2015207288A (ja
JP2015207288A5 (enExample
Inventor
ブルーネ、アンドレアス
ポール、クリストファー
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Robert Bosch GmbH
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Robert Bosch GmbH
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Publication of JP2015207288A publication Critical patent/JP2015207288A/ja
Publication of JP2015207288A5 publication Critical patent/JP2015207288A5/ja
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Publication of JP6534851B2 publication Critical patent/JP6534851B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G06F13/34—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
JP2015084375A 2014-04-17 2015-04-16 インタフェースユニット Active JP6534851B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014207417.7 2014-04-17
DE102014207417.7A DE102014207417A1 (de) 2014-04-17 2014-04-17 Schnittstelleneinheit

Publications (3)

Publication Number Publication Date
JP2015207288A JP2015207288A (ja) 2015-11-19
JP2015207288A5 JP2015207288A5 (enExample) 2018-04-05
JP6534851B2 true JP6534851B2 (ja) 2019-06-26

Family

ID=54249919

Family Applications (1)

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JP2015084375A Active JP6534851B2 (ja) 2014-04-17 2015-04-16 インタフェースユニット

Country Status (4)

Country Link
US (1) US9880955B2 (enExample)
JP (1) JP6534851B2 (enExample)
CN (1) CN105022707B (enExample)
DE (1) DE102014207417A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105530153B (zh) * 2015-12-11 2019-02-05 上海新时达电气股份有限公司 网络内的从设备通信方法、通信网络、主设备及从设备
JP7363344B2 (ja) * 2019-10-15 2023-10-18 オムロン株式会社 メモリ制御装置、および制御方法
WO2025235430A1 (en) * 2024-05-08 2025-11-13 Micron Technology, Inc. Vendor specific sub block access according to sub block descriptor

Family Cites Families (34)

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US5781799A (en) * 1995-09-29 1998-07-14 Cirrus Logic, Inc. DMA controller arrangement having plurality of DMA controllers and buffer pool having plurality of buffers accessible to each of the channels of the controllers
US5875352A (en) * 1995-11-03 1999-02-23 Sun Microsystems, Inc. Method and apparatus for multiple channel direct memory access control
KR0170500B1 (ko) * 1995-11-18 1999-03-30 양승택 멀티프로세서 시스템
US6188699B1 (en) * 1997-12-11 2001-02-13 Pmc-Sierra Ltd. Multi-channel encoder/decoder
US7000244B1 (en) * 1999-09-02 2006-02-14 Broadlogic Network Technologies, Inc. Multi-threaded direct memory access engine for broadcast data demultiplex operations
US6418489B1 (en) * 1999-10-25 2002-07-09 Motorola, Inc. Direct memory access controller and method therefor
US7003093B2 (en) * 2000-09-08 2006-02-21 Intel Corporation Tone detection for integrated telecommunications processing
US6738358B2 (en) * 2000-09-09 2004-05-18 Intel Corporation Network echo canceller for integrated telecommunications processing
US20020116186A1 (en) * 2000-09-09 2002-08-22 Adam Strauss Voice activity detector for integrated telecommunications processing
KR100403620B1 (ko) * 2001-02-28 2003-10-30 삼성전자주식회사 채널 활용율을 높이는 통신 시스템 및 그 방법
US20030172190A1 (en) * 2001-07-02 2003-09-11 Globespanvirata Incorporated Communications system using rings architecture
US6754732B1 (en) * 2001-08-03 2004-06-22 Intervoice Limited Partnership System and method for efficient data transfer management
US7043579B2 (en) * 2002-12-05 2006-05-09 International Business Machines Corporation Ring-topology based multiprocessor data access bus
US7085859B2 (en) * 2003-05-14 2006-08-01 International Business Machines Corporation Method, apparatus and program storage device for automatically presenting status from a host bus adapter until an error is detected
US20050080945A1 (en) * 2003-10-14 2005-04-14 International Business Machines Corporation Transferring message packets from data continued in disparate areas of source memory via preloading
US7117308B1 (en) * 2004-04-06 2006-10-03 Cisco Technology, Inc. Hypertransport data path protocol
US9264384B1 (en) * 2004-07-22 2016-02-16 Oracle International Corporation Resource virtualization mechanism including virtual host bus adapters
US7577772B2 (en) * 2004-09-08 2009-08-18 Qlogic, Corporation Method and system for optimizing DMA channel selection
US7370123B2 (en) * 2004-10-12 2008-05-06 Nec Electronics Corporation Information processing apparatus
JP2006338538A (ja) * 2005-06-03 2006-12-14 Nec Electronics Corp ストリームプロセッサ
US7496699B2 (en) * 2005-06-17 2009-02-24 Level 5 Networks, Inc. DMA descriptor queue read and cache write pointer arrangement
JP4724494B2 (ja) * 2005-08-26 2011-07-13 キヤノン株式会社 Ｐｃｉブリッジ及ｐｃｉブリッジを搭載するシステム
US7502873B2 (en) * 2006-10-10 2009-03-10 International Business Machines Corporation Facilitating access to status and measurement data associated with input/output processing
JP4347350B2 (ja) * 2007-02-15 2009-10-21 富士通株式会社 データ暗号転送装置、データ復号転送装置、データ暗号転送方法およびデータ復号転送方法
US7694035B2 (en) * 2007-06-26 2010-04-06 International Business Machines Corporation DMA shared byte counters in a parallel computer
US7886084B2 (en) * 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US20090083392A1 (en) * 2007-09-25 2009-03-26 Sun Microsystems, Inc. Simple, efficient rdma mechanism
US8103809B1 (en) * 2009-01-16 2012-01-24 F5 Networks, Inc. Network devices with multiple direct memory access channels and methods thereof
US20110153877A1 (en) * 2009-12-23 2011-06-23 King Steven R Method and apparatus to exchange data via an intermediary translation and queue manager
JP2011193242A (ja) * 2010-03-15 2011-09-29 Renesas Electronics Corp 通信制御装置および通信制御方法
US8615614B2 (en) * 2011-11-30 2013-12-24 Freescale Semiconductor, Inc. Message passing using direct memory access unit in a data processing system
US9251107B2 (en) * 2013-06-27 2016-02-02 Silicon Laboratories Inc. Immediate direct memory access descriptor-based write operation
KR102180972B1 (ko) * 2014-04-23 2020-11-20 에스케이하이닉스 주식회사 메모리 컨트롤 유닛 및 그것을 포함하는 데이터 저장 장치

Also Published As

Publication number Publication date
CN105022707A (zh) 2015-11-04
JP2015207288A (ja) 2015-11-19
CN105022707B (zh) 2020-03-17
US20150301965A1 (en) 2015-10-22
DE102014207417A1 (de) 2015-10-22
US9880955B2 (en) 2018-01-30

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