JP2015207288A5 - - Google Patents

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Publication number
JP2015207288A5
JP2015207288A5 JP2015084375A JP2015084375A JP2015207288A5 JP 2015207288 A5 JP2015207288 A5 JP 2015207288A5 JP 2015084375 A JP2015084375 A JP 2015084375A JP 2015084375 A JP2015084375 A JP 2015084375A JP 2015207288 A5 JP2015207288 A5 JP 2015207288A5
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JP
Japan
Prior art keywords
data
interface unit
unit
memory
descriptor
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JP2015084375A
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English (en)
Japanese (ja)
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JP2015207288A (ja
JP6534851B2 (ja
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Priority claimed from DE102014207417.7A external-priority patent/DE102014207417A1/de
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Publication of JP2015207288A publication Critical patent/JP2015207288A/ja
Publication of JP2015207288A5 publication Critical patent/JP2015207288A5/ja
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Publication of JP6534851B2 publication Critical patent/JP6534851B2/ja
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JP2015084375A 2014-04-17 2015-04-16 インタフェースユニット Active JP6534851B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014207417.7 2014-04-17
DE102014207417.7A DE102014207417A1 (de) 2014-04-17 2014-04-17 Schnittstelleneinheit

Publications (3)

Publication Number Publication Date
JP2015207288A JP2015207288A (ja) 2015-11-19
JP2015207288A5 true JP2015207288A5 (enExample) 2018-04-05
JP6534851B2 JP6534851B2 (ja) 2019-06-26

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ID=54249919

Family Applications (1)

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JP2015084375A Active JP6534851B2 (ja) 2014-04-17 2015-04-16 インタフェースユニット

Country Status (4)

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US (1) US9880955B2 (enExample)
JP (1) JP6534851B2 (enExample)
CN (1) CN105022707B (enExample)
DE (1) DE102014207417A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105530153B (zh) * 2015-12-11 2019-02-05 上海新时达电气股份有限公司 网络内的从设备通信方法、通信网络、主设备及从设备
JP7363344B2 (ja) * 2019-10-15 2023-10-18 オムロン株式会社 メモリ制御装置、および制御方法
WO2025235430A1 (en) * 2024-05-08 2025-11-13 Micron Technology, Inc. Vendor specific sub block access according to sub block descriptor

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