JP6505540B2 - 半導体装置及び半導体装置の製造方法 - Google Patents

半導体装置及び半導体装置の製造方法 Download PDF

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Publication number
JP6505540B2
JP6505540B2 JP2015147882A JP2015147882A JP6505540B2 JP 6505540 B2 JP6505540 B2 JP 6505540B2 JP 2015147882 A JP2015147882 A JP 2015147882A JP 2015147882 A JP2015147882 A JP 2015147882A JP 6505540 B2 JP6505540 B2 JP 6505540B2
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Prior art keywords
lead frame
resin layer
lead
semiconductor device
opening
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JP2015147882A
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Japanese (ja)
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JP2017028200A5 (https=
JP2017028200A (ja
Inventor
真太郎 林
真太郎 林
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2015147882A priority Critical patent/JP6505540B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2015147882A 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法 Active JP6505540B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015147882A JP6505540B2 (ja) 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015147882A JP6505540B2 (ja) 2015-07-27 2015-07-27 半導体装置及び半導体装置の製造方法

Publications (3)

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JP2017028200A JP2017028200A (ja) 2017-02-02
JP2017028200A5 JP2017028200A5 (https=) 2018-04-26
JP6505540B2 true JP6505540B2 (ja) 2019-04-24

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JP (1) JP6505540B2 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6909629B2 (ja) * 2017-05-10 2021-07-28 ローム株式会社 半導体装置
JP7022541B2 (ja) * 2017-09-11 2022-02-18 ローム株式会社 半導体装置
JP2019110278A (ja) * 2017-12-20 2019-07-04 株式会社デンソー 半導体装置
TWI737505B (zh) * 2020-09-29 2021-08-21 力成科技股份有限公司 封裝結構
JP7450575B2 (ja) * 2021-03-18 2024-03-15 株式会社東芝 半導体装置及びその製造方法
JPWO2024203110A1 (https=) * 2023-03-24 2024-10-03

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3436159B2 (ja) * 1998-11-11 2003-08-11 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
JP3046024B1 (ja) * 1999-04-23 2000-05-29 松下電子工業株式会社 リ―ドフレ―ムおよびそれを用いた樹脂封止型半導体装置の製造方法
JP5122835B2 (ja) * 2007-02-27 2013-01-16 ローム株式会社 半導体装置、リードフレームおよび半導体装置の製造方法
JP5126687B2 (ja) * 2009-02-16 2013-01-23 大日本印刷株式会社 樹脂封止型半導体装置、リードフレーム、リードフレームの製造方法、および樹脂封止型半導体装置の製造方法
JP5319571B2 (ja) * 2010-02-12 2013-10-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8389330B2 (en) * 2010-06-24 2013-03-05 Stats Chippac Ltd. Integrated circuit package system with package stand-off and method of manufacture thereof

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Publication number Publication date
JP2017028200A (ja) 2017-02-02

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