JP6502452B1 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP6502452B1 JP6502452B1 JP2017198197A JP2017198197A JP6502452B1 JP 6502452 B1 JP6502452 B1 JP 6502452B1 JP 2017198197 A JP2017198197 A JP 2017198197A JP 2017198197 A JP2017198197 A JP 2017198197A JP 6502452 B1 JP6502452 B1 JP 6502452B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000008878 coupling Effects 0.000 abstract description 11
- 238000010168 coupling process Methods 0.000 abstract description 11
- 238000005859 coupling reaction Methods 0.000 abstract description 11
- 230000007257 malfunction Effects 0.000 abstract description 4
- 239000002184 metal Substances 0.000 description 93
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 16
- 229920005591 polysilicon Polymers 0.000 description 16
- 238000010586 diagram Methods 0.000 description 9
- 230000008859 change Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
Description
110:メモリセルアレイ
112:ビット線選択回路
120:入出力バッファ
130:アドレスレジスタ
140:データレジスタ
150:コントローラ
160:ワード線選択回路
170:ページバッファ/センス回路
180:列選択回路
190:内部電圧発生回路
200−1〜200−4:矩形領域
210:細長の矩形領域
212:PMOS領域
214:NMOS領域
216、218:素子形成領域
230、232、234、236:Nウエル領域
LAT_A、LAT_B:ラッチ回路
IV1_A、IV2_A、IV1_B、IV2_B:インバータ
Claims (11)
- 複数のメモリセルが形成されたメモリセルアレイと、
前記メモリセルアレイの選択されたページから読み出されたデータを保持し、または前記メモリセルアレイの選択されたページにプログラムするデータを保持するページバッファ/センス回路とを有し、
前記メモリセルアレイ上を延在するp本のビット線により規定される行方向の1ピッチ内に、前記ページバッファ/センス回路がn列×m段(nは、2以上の整数、mは、2以上の整数)に配置され、
前記ページバッファ/センス回路は、ラッチ回路を含み、前記1ピッチ内の同一平面上には、電源に電気的に接続された複数の電源用配線と、n組のラッチ回路に電気的に接続されたn組のラッチ用配線と、n組のセンスノードに電気的に接続されたセンス用配線とが形成され、前記電源用配線の線幅は、前記ラッチ用配線およびセンス用配線の線幅よりも広い、半導体記憶装置。 - 前記複数の電源用配線は、少なくとも1ピッチ内の両端側に配置され、前記ラッチ用配線および前記センス用配線は、両端側に配置された電源用配線の間に配置される、請求項1に記載の半導体装置。
- n組のラッチ回路が第1および第2のラッチ回路を含むとき、第1のラッチ回路がデータを保持する第1のノードに接続された第1のラッチ用配線が、第2のラッチ回路がデータを保持する第2のノードに接続された第2のラッチ用配線から離間されるように配置される、請求項1に記載の半導体記憶装置。
- 前記第1のラッチ用配線と前記第2のラッチ用配線との間に、第1のページバッファ/センス回路の第1のセンスノードに接続された第3のセンス用配線と、第2のページバッファ/センス回路の第2のセンスノードに接続された第4のセンス用配線とが形成される、請求項3に記載の半導体記憶装置。
- 前記第3のセンス用配線と前記第4のセンス用配線との間に、GNDに接続された第5の配線が形成される、請求項4に記載の半導体記憶装置。
- 前記第1のラッチ用配線と前記第2のラッチ用配線は、前記第5の配線に関して線対称に配置される、請求項4に記載の半導体記憶装置。
- 前記第1のノードは、第1の転送トランジスタを介して前記第1のセンスノードから電荷を受け取り、前記第2のノードは、第2の転送トランジスタを介して前記第2のセンスノードから電荷を受け取る、請求項4に記載の半導体記憶装置。
- n組のラッチ回路は、前記1ピッチで規定されるNウエル領域およびPウエル領域内に形成される、請求項1に記載の半導体記憶装置。
- 前記Nウエル領域には、n組のラッチ回路のPMOSトランジスタが形成され、前記Pウエル領域には、n組のラッチ回路のNMOSトランジスタが形成される、請求項8に記載の半導体記憶装置。
- 前記ページバッファ/センス回路は、1ピッチ内に2列×4段のレイアウトで配置される、請求項1に記載の半導体記憶装置。
- 前記1ピッチ内には、一対の電源用配線の内側に、第1のラッチ回路の一方のノードに接続されたラッチ用配線、第1のラッチ回路の他方のノードに接続されたラッチ用配線、第1のセンスノードに接続されたセンス用配線、グランドに接続された配線、第2のセンスノードに接続されたセンス用配線、第2のラッチ回路の一方のノードに接続されたラッチ用配線、第2のラッチ回路の他方のノードに接続されたラッチ用配線が順に形成される、請求項10に記載の半導体記憶装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017198197A JP6502452B1 (ja) | 2017-10-12 | 2017-10-12 | 半導体記憶装置 |
TW107100582A TWI644316B (zh) | 2017-10-12 | 2018-01-05 | 半導體儲存裝置 |
CN201810336667.7A CN109658965B (zh) | 2017-10-12 | 2018-04-16 | 半导体存储装置 |
US16/111,157 US10497448B2 (en) | 2017-10-12 | 2018-08-23 | Semiconductor memory device |
KR1020180102012A KR102123736B1 (ko) | 2017-10-12 | 2018-08-29 | 반도체 기억장치 |
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JP2017198197A JP6502452B1 (ja) | 2017-10-12 | 2017-10-12 | 半導体記憶装置 |
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JP6502452B1 true JP6502452B1 (ja) | 2019-04-17 |
JP2019075397A JP2019075397A (ja) | 2019-05-16 |
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US (1) | US10497448B2 (ja) |
JP (1) | JP6502452B1 (ja) |
KR (1) | KR102123736B1 (ja) |
CN (1) | CN109658965B (ja) |
TW (1) | TWI644316B (ja) |
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KR20210091479A (ko) | 2020-01-14 | 2021-07-22 | 에스케이하이닉스 주식회사 | 페이지 버퍼를 구비하는 반도체 메모리 장치 |
KR20210099796A (ko) * | 2020-02-05 | 2021-08-13 | 에스케이하이닉스 주식회사 | 페이지 버퍼를 포함하는 반도체 장치 |
KR20220010360A (ko) | 2020-07-17 | 2022-01-25 | 삼성전자주식회사 | 페이지 버퍼 회로 및 이를 포함하는 메모리 장치 |
Family Cites Families (14)
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JPH11176177A (ja) | 1997-12-12 | 1999-07-02 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR100706248B1 (ko) * | 2005-06-03 | 2007-04-11 | 삼성전자주식회사 | 소거 동작시 비트라인 전압을 방전하는 페이지 버퍼를구비한 낸드 플래시 메모리 장치 |
KR100879387B1 (ko) * | 2006-09-22 | 2009-01-20 | 삼성전자주식회사 | 플래시 메모리 장치 및 그것의 프로그램 방법 |
CN101740125B (zh) | 2006-09-30 | 2013-04-17 | 莫塞德技术公司 | Nand型快闪存储器的读写方法及其相关页缓冲区 |
US7889553B2 (en) * | 2007-04-24 | 2011-02-15 | Novelics, Llc. | Single-poly non-volatile memory cell |
KR100935593B1 (ko) * | 2008-02-12 | 2010-01-07 | 주식회사 하이닉스반도체 | 페이지 버퍼를 제어하는 비휘발성 메모리 장치 |
JP5129309B2 (ja) * | 2010-09-22 | 2013-01-30 | 株式会社東芝 | 半導体記憶装置 |
JP5539916B2 (ja) * | 2011-03-04 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2014049472A (ja) * | 2012-08-29 | 2014-03-17 | Toshiba Corp | 半導体記憶装置 |
JP5667143B2 (ja) * | 2012-10-11 | 2015-02-12 | ウィンボンド エレクトロニクス コーポレーション | 不揮発性半導体メモリ |
KR101986696B1 (ko) * | 2012-12-28 | 2019-06-10 | 에스케이하이닉스 주식회사 | 메모리 |
JP5714681B2 (ja) | 2013-10-25 | 2015-05-07 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
JP6114796B1 (ja) | 2015-10-05 | 2017-04-12 | 力晶科技股▲ふん▼有限公司 | 不揮発性記憶装置のためのセンス回路及び不揮発性記憶装置 |
JP6181218B2 (ja) * | 2016-02-09 | 2017-08-16 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
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- 2017-10-12 JP JP2017198197A patent/JP6502452B1/ja active Active
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2018
- 2018-01-05 TW TW107100582A patent/TWI644316B/zh active
- 2018-04-16 CN CN201810336667.7A patent/CN109658965B/zh active Active
- 2018-08-23 US US16/111,157 patent/US10497448B2/en active Active
- 2018-08-29 KR KR1020180102012A patent/KR102123736B1/ko active IP Right Grant
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Publication number | Publication date |
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KR102123736B1 (ko) | 2020-06-17 |
TW201916044A (zh) | 2019-04-16 |
CN109658965B (zh) | 2020-11-24 |
US20190115084A1 (en) | 2019-04-18 |
US10497448B2 (en) | 2019-12-03 |
KR20190041397A (ko) | 2019-04-22 |
JP2019075397A (ja) | 2019-05-16 |
TWI644316B (zh) | 2018-12-11 |
CN109658965A (zh) | 2019-04-19 |
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