JP6460422B2 - 異種半導体材料集積化技術 - Google Patents
異種半導体材料集積化技術 Download PDFInfo
- Publication number
- JP6460422B2 JP6460422B2 JP2016526928A JP2016526928A JP6460422B2 JP 6460422 B2 JP6460422 B2 JP 6460422B2 JP 2016526928 A JP2016526928 A JP 2016526928A JP 2016526928 A JP2016526928 A JP 2016526928A JP 6460422 B2 JP6460422 B2 JP 6460422B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- semiconductor
- oxide
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 210
- 239000000463 material Substances 0.000 title claims description 46
- 230000010354 integration Effects 0.000 title description 14
- 238000005516 engineering process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims description 135
- 238000000034 method Methods 0.000 claims description 110
- 230000007547 defect Effects 0.000 claims description 26
- 150000002500 ions Chemical class 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 238000012876 topography Methods 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 5
- 208000012868 Overgrowth Diseases 0.000 claims description 5
- 230000032798 delamination Effects 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 5
- 238000001534 heteroepitaxy Methods 0.000 claims description 5
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 229910044991 metal oxide Inorganic materials 0.000 claims description 5
- 150000004706 metal oxides Chemical class 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 4
- -1 hydrogen (H + ) ions Chemical class 0.000 claims description 3
- 238000001657 homoepitaxy Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 288
- 238000004891 communication Methods 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 238000003776 cleavage reaction Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 230000007017 scission Effects 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 3
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- YZCKVEUIGOORGS-UHFFFAOYSA-N Hydrogen atom Chemical compound [H] YZCKVEUIGOORGS-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 238000004299 exfoliation Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 238000001802 infusion Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000004627 transmission electron microscopy Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02634—Homoepitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02642—Mask materials other than SiO2 or SiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
Description
概要
方法論
システムの例
更なる例示的実施形態
Claims (28)
- 基板と、
前記基板の一部の表面に形成される酸化物構造と、
前記酸化物構造上に形成され、前記酸化物構造の上側表面内に埋め込まれる、前記酸化物構造と格子不整合の半導体構造と、を備え、
前記格子不整合の半導体構造は、前記酸化物構造の前記上側表面内に埋め込まれた複数の結晶性ファセットエッジを含む
集積回路。 - 基板と、
前記基板の一部の上に形成される酸化物構造と、
前記酸化物構造上に形成され、前記酸化物構造の上側表面内に埋め込まれる、前記酸化物構造と格子不整合の半導体構造と、
前記基板上に形成され、前記酸化物構造の1又は複数の側壁を少なくとも部分的に覆う半導体材料の層と、を備え、
前記格子不整合の半導体構造は複数の結晶性ファセットエッジを含む
集積回路。 - 基板と、
前記基板の一部の表面に形成される酸化物構造と、
前記酸化物構造上に形成され、前記酸化物構造の上側表面内に埋め込まれる、前記酸化物構造と格子不整合の半導体構造と、を備え、
前記格子不整合の半導体構造は複数の結晶性ファセットエッジを含み、
前記半導体構造は、転位欠陥を全く含まない
集積回路。 - 基板と、
前記基板の一部の表面に形成される酸化物構造と、
前記酸化物構造上に形成され、前記酸化物構造の上側表面内に埋め込まれる、前記酸化物構造と格子不整合の半導体構造と、を備え、
前記格子不整合の半導体構造は複数の結晶性ファセットエッジを含み、
前記基板は、少なくとも部分的に前記酸化物構造の1又は複数の側壁を覆う
集積回路。 - 前記半導体構造及び前記酸化物構造は、一体となって、追加の層及び/又はコンポーネントが配置され得る平坦な表面を提供する
請求項1から4の何れか一項に記載の集積回路。 - 前記基板上に形成され、前記酸化物構造の1又は複数の側壁を少なくとも部分的に覆う半導体材料の層を更に備える
請求項1、3または4の何れか一項に記載の集積回路。 - 前記半導体構造、前記酸化物構造、及び前記半導体材料の層は、一体となって、追加の層及び/又はコンポーネントが配置され得る平坦な表面を提供する
請求項6に記載の集積回路。 - 前記基板は、少なくとも部分的に前記酸化物構造の1又は複数の側壁を覆う
請求項1または3に記載の集積回路。 - 前記半導体構造、前記酸化物構造、及び前記基板は、一体となって、追加の層及び/又はコンポーネントが配置され得る平坦な表面を提供する
請求項8に記載の集積回路。 - 前記半導体構造は、転位欠陥を全く含まない
請求項1、2または4の何れか一項に記載の集積回路。 - 前記基板は、シリコン(Si)、ゲルマニウム(Ge)、サファイア(Al2O3)、及び/又は誘電材料のうちの少なくとも1つを備える
請求項1から10の何れか一項に記載の集積回路。 - 前記半導体構造は、ゲルマニウム(Ge)、ヒ化ガリウム(GaAs)、ヒ化ガリウムインジウム(InGaAs)、窒化ガリウム(GaN)、及び/又はリン化インジウム(InP)のうちの少なくとも1つを備える
請求項1から11の何れか一項に記載の集積回路。 - 前記酸化物構造は、二酸化シリコン(SiO2)及び/又は酸化アルミニウム(Al2O3)のうちの少なくとも1つを備える
請求項1から12の何れか一項に記載の集積回路。 - 集積回路を形成する方法であって、
第1の基板の上に第1の半導体層を形成する段階と、
前記第1の半導体層の一部を前記第1の基板から第2の基板へと移動させる段階と、を備え、
前記第1の半導体層は前記第1の基板とは格子不整合であり、
前記第1の半導体層の前記移動させられた部分は、複数の結晶性ファセットエッジを含む、
方法。 - 前記第1の基板の上に前記第1の半導体層を形成する段階は、
ヘテロエピタキシプロセスを使用して、前記第1の基板の上に形成される誘電体層の中にパターン化される1又は複数の開口部内の前記第1の基板上に前記第1の半導体層を成長させる段階と、
エピタキシャル・ラテラル・オーバーグロース(ELO)プロセスを使用して、前記誘電体層の上側表面の少なくとも一部の上に前記第1の半導体層を更に成長させる段階と、を有する
請求項14に記載の方法。 - 前記誘電体層の中にパターン化される前記1又は複数の開口部は、前記第1の基板の、前記格子不整合の第1の半導体層との界面から発生する複数の転位欠陥のアスペクト比トラッピング(ART)を提供する高さ対幅のアスペクト比を有する
請求項15に記載の方法。 - ヘテロエピタキシプロセスを使用して、前記第2の基板上に第2の半導体層を形成する段階を更に備える
請求項14に記載の方法。 - ホモエピタキシプロセスを使用して、前記第2の基板を更に形成する段階を更に備える
請求項14に記載の方法。 - 集積回路を形成する方法であって、
第1の基板の上に誘電体層を形成し、前記誘電体層の中に1又は複数の開口部をパターン化する段階と、
前記第1の基板及び前記パターン化された誘電体層の上に第1の半導体層を形成する段階であって、前記第1の半導体層は前記第1の基板とは格子不整合である、段階と、
前記第1の半導体層を平坦化する段階と、
前記平坦化された第1の半導体層及びパターン化された誘電体層によって提供されるトポグラフィの上に第1の酸化物層を形成する段階と、
前記第1の酸化物層を、第2の基板の上に形成される第2の酸化物層と接合させる段階と、
結果として得られた前記接合させられた酸化物層、及び、前記平坦化された第1の半導体層の各々のうちの少なくとも一部を前記第2の基板に移動させる段階と、
前記接合させられた酸化物層及び前記第1の半導体層の複数の前記移動させられた部分を平坦化する段階と、
下にある前記第2の基板の上側表面を露出させるべく、結果として得られた前記平坦化された接合させられた酸化物層をエッチングする段階と、を備える
方法。 - 前記誘電体層の中にパターン化される前記1又は複数の開口部は、約2:1から5:1の範囲の高さ対幅のアスペクト比を有する
請求項19に記載の方法。 - 前記第1の基板及び前記パターン化された誘電体層の上に前記第1の半導体層を形成する段階は、
ヘテロエピタキシプロセスを使用して、前記誘電体層の中にパターン化される前記1又は複数の開口部内の前記第1の基板上に前記第1の半導体層を成長させる段階と、
エピタキシャル・ラテラル・オーバーグロース(ELO)プロセスを使用して、前記パターン化された誘電体層の上側表面の少なくとも一部の上に前記第1の半導体層を更に成長させる段階と、を有する、
請求項19に記載の方法。 - 前記接合させられた酸化物層及び前記平坦化された第1の半導体層の各々のうちの少なくとも一部を前記第2の基板に移動させる段階は、
前記平坦化された第1の半導体層内に複数の水素(H+)イオンを注入する段階と、
約350−400℃の範囲の温度で水素を利用した層剥離を実行する段階と、を備える
請求項19に記載の方法。 - 前記複数のH+イオンを注入する段階は、約5×1016H+イオン/cm2から3×1017H+イオン/cm2の範囲の注入量を使用して実行される
請求項22に記載の方法。 - 前記複数のH+イオンを注入する段階は、約30−100keVの範囲の注入エネルギーを使用して実行される
請求項22に記載の方法。 - 前記第2の基板上に第2の半導体層をヘテロエピタキシャル成長させる段階
を更に備える
請求項19に記載の方法。 - 前記第2の基板をホモエピタキシャル成長させる段階
を更に備える
請求項19に記載の方法。 - 請求項19から26の何れか一項に記載の方法を使用して形成されるp型金属酸化膜半導体(PMOS)デバイス。
- 請求項19から26の何れか一項に記載の方法を使用して形成されるn型金属酸化膜半導体(NMOS)デバイス。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/139,954 US9177967B2 (en) | 2013-12-24 | 2013-12-24 | Heterogeneous semiconductor material integration techniques |
US14/139,954 | 2013-12-24 | ||
PCT/US2014/066293 WO2015099904A1 (en) | 2013-12-24 | 2014-11-19 | Heterogeneous semiconductor material integration techniques |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017508266A JP2017508266A (ja) | 2017-03-23 |
JP6460422B2 true JP6460422B2 (ja) | 2019-01-30 |
Family
ID=53400928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016526928A Active JP6460422B2 (ja) | 2013-12-24 | 2014-11-19 | 異種半導体材料集積化技術 |
Country Status (7)
Country | Link |
---|---|
US (2) | US9177967B2 (ja) |
EP (1) | EP3087583A4 (ja) |
JP (1) | JP6460422B2 (ja) |
KR (1) | KR102355273B1 (ja) |
CN (1) | CN105765695B (ja) |
TW (1) | TWI603383B (ja) |
WO (1) | WO2015099904A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102146449B1 (ko) * | 2013-12-18 | 2020-08-20 | 인텔 코포레이션 | 이종 층 디바이스 |
US9177967B2 (en) | 2013-12-24 | 2015-11-03 | Intel Corporation | Heterogeneous semiconductor material integration techniques |
JP6706414B2 (ja) * | 2015-11-27 | 2020-06-10 | 国立研究開発法人情報通信研究機構 | Ge単結晶薄膜の製造方法及び光デバイス |
KR102430501B1 (ko) * | 2015-12-29 | 2022-08-09 | 삼성전자주식회사 | 반도체 단결정구조, 반도체 디바이스 및 그 제조방법 |
EP3288067B1 (en) * | 2016-08-25 | 2021-10-27 | IMEC vzw | Method for transferring a group iii-iv semiconductor active layer |
CN111244227B (zh) * | 2020-01-19 | 2023-07-18 | 中国科学院上海微系统与信息技术研究所 | 一种硅基光子集成模块及其制备方法 |
CN112529873B (zh) * | 2020-12-09 | 2021-11-30 | 深圳市芯汇群微电子技术有限公司 | 一种基于art神经网络的晶圆缺陷检测方法 |
CN113097163B (zh) * | 2021-03-31 | 2022-12-06 | 深圳市红与蓝企业管理中心(有限合伙) | 一种半导体hemt器件及其制造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2388736A1 (en) | 1999-10-22 | 2001-04-26 | Washington University | Oligodendrocyte cell cultures and methods for their preparation and use |
JP4649819B2 (ja) * | 2003-03-06 | 2011-03-16 | ソニー株式会社 | 半導体集積素子の製造方法 |
US7138309B2 (en) * | 2005-01-19 | 2006-11-21 | Sharp Laboratories Of America, Inc. | Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US20060292719A1 (en) * | 2005-05-17 | 2006-12-28 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US9153645B2 (en) * | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
WO2007014294A2 (en) * | 2005-07-26 | 2007-02-01 | Amberwave Systems Corporation | Solutions integrated circuit integration of alternative active area materials |
WO2007030368A2 (en) | 2005-09-07 | 2007-03-15 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures on insulators and their fabrication methods |
US7638842B2 (en) * | 2005-09-07 | 2009-12-29 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures on insulators |
US8173551B2 (en) | 2006-09-07 | 2012-05-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Defect reduction using aspect ratio trapping |
WO2008039534A2 (en) * | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures |
WO2008039495A1 (en) * | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
US8502263B2 (en) | 2006-10-19 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Light-emitter-based devices with lattice-mismatched semiconductor structures |
CN102160145B (zh) * | 2008-09-19 | 2013-08-21 | 台湾积体电路制造股份有限公司 | 通过外延层过成长的元件形成 |
ATE555494T1 (de) | 2009-02-19 | 2012-05-15 | S O I Tec Silicon | Relaxation und übertragung von verspannten materialschichten |
JP5244650B2 (ja) * | 2009-02-26 | 2013-07-24 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP4638958B1 (ja) * | 2009-08-20 | 2011-02-23 | 株式会社パウデック | 半導体素子の製造方法 |
US9177967B2 (en) | 2013-12-24 | 2015-11-03 | Intel Corporation | Heterogeneous semiconductor material integration techniques |
-
2013
- 2013-12-24 US US14/139,954 patent/US9177967B2/en not_active Expired - Fee Related
-
2014
- 2014-11-17 TW TW103139771A patent/TWI603383B/zh active
- 2014-11-19 JP JP2016526928A patent/JP6460422B2/ja active Active
- 2014-11-19 KR KR1020167013762A patent/KR102355273B1/ko active IP Right Grant
- 2014-11-19 WO PCT/US2014/066293 patent/WO2015099904A1/en active Application Filing
- 2014-11-19 EP EP14873496.5A patent/EP3087583A4/en not_active Withdrawn
- 2014-11-19 CN CN201480064142.2A patent/CN105765695B/zh active Active
-
2015
- 2015-11-02 US US14/930,171 patent/US9548320B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR102355273B1 (ko) | 2022-01-26 |
JP2017508266A (ja) | 2017-03-23 |
US20160056180A1 (en) | 2016-02-25 |
TW201537622A (zh) | 2015-10-01 |
TWI603383B (zh) | 2017-10-21 |
EP3087583A1 (en) | 2016-11-02 |
US9177967B2 (en) | 2015-11-03 |
CN105765695B (zh) | 2019-08-20 |
KR20160098202A (ko) | 2016-08-18 |
US20150179664A1 (en) | 2015-06-25 |
CN105765695A (zh) | 2016-07-13 |
WO2015099904A1 (en) | 2015-07-02 |
EP3087583A4 (en) | 2017-08-09 |
US9548320B2 (en) | 2017-01-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6460422B2 (ja) | 異種半導体材料集積化技術 | |
TWI544518B (zh) | 矽晶圓上之iii-v族裝置的集成 | |
US10979012B2 (en) | Single-flipped resonator devices with 2DEG bottom electrode | |
CN105874587B (zh) | Si沟槽中的ⅲ-n器件 | |
TWI578383B (zh) | 溝渠侷限的磊晶成長裝置層 | |
TWI582831B (zh) | 用於III-N磊晶之具有Si(111)平面於Si(100)晶片上的奈米結構及奈米特徵 | |
TWI564939B (zh) | 在選擇性磊晶期間防止側壁缺陷的方法及結構 | |
TWI540649B (zh) | 形成一對電子裝置鰭的方法 | |
TWI697125B (zh) | 異質磊晶n型電晶體與p型電晶體之以井為基礎之集成 | |
US20170256408A1 (en) | Methods and structures to prevent sidewall defects during selective epitaxy |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20171108 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20180629 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180710 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181003 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20181127 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20181219 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6460422 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |