JP6434872B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6434872B2 JP6434872B2 JP2015152626A JP2015152626A JP6434872B2 JP 6434872 B2 JP6434872 B2 JP 6434872B2 JP 2015152626 A JP2015152626 A JP 2015152626A JP 2015152626 A JP2015152626 A JP 2015152626A JP 6434872 B2 JP6434872 B2 JP 6434872B2
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
なお、本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1は、第1の実施形態に係る半導体装置を例示する模式的断面図である。
図1に表したように、本実施形態に係る半導体装置101は、第1半導体層10と、第2半導体層20と、第3半導体層30と、第1電極40と、を含む。半導体装置101は、さらに、第4半導体層34、絶縁膜43、絶縁層51及び絶縁層52を含む。半導体装置101は、例えば薄膜トランジスタである。
第2半導体層20は、第3層13と第4層14とを含む。第4層14は、第3層13と第3半導体層30との間に設けられる。
絶縁層51には、例えば、酸化シリコン、窒化シリコンまたはポリシラザン(Polysilazane:PSZ)が用いられる。絶縁層52には、例えば、酸化シリコン、窒化シリコンまたはポリシラザンが用いられる。
例えば、第3半導体層30は、特定の結晶配向性を有する。第1半導体層10及び第2半導体層20は、例えば、特定の結晶配向性を有さない。第1半導体層10及び第2半導体層20においては、例えば結晶がランダムに配向している。
第1結晶方位は、例えば、<100>方向、<110>方向及び<111>方向のいずれかである。
第1端部E1は、第1方向と交差する方向(例えばX軸方向)において、第3半導体層30及び第2層12のいずれかと重なる。この例では、第1端部E1は、X軸方向において第2層12と重なっている。第1端部E1は、X軸方向において第1層11とは重ならない。
これに対して、チャネル中を垂直に粒界が横切らないような結晶粒の配向制御によって、キャリアの移動度の低下などを抑制することができる。前述したように、実施形態に係る半導体装置101においては、第3半導体層30における第1結晶方位の配向性は、第1半導体層10における第1結晶方位の配向性よりも高い。例えば、半導体装置101のチャネルにおいては、電流が流れる方向と平行となるように結晶配向が揃っている。これにより、キャリアがソースからドレインへ移動する際に、粒界を横切る確率が低下する。したがって、粒界ポテンシャルのキャリアへの影響が低減され、移動度を向上させることができる。閾値のシフトやS値の低下を抑制することができ、良好なサブスレッショルド特性を得ることができる。
図2(a)に表した半導体装置101aにおいては、第1電極40の第1端部E1は、X軸方向において、第2層12と第4半導体層34との境界と重なっている。第2端部E2は、X軸方向において第4層14と第3半導体層30との境界と重なっている。すなわち、第1電極40の端部は、結晶がランダムに配向した領域と特定の配向性を有する領域との境界と重なっている。
図2(b)に表した半導体装置101bにおいては、第1端部E1及び第2端部E2は、それぞれ、X軸方向において第3半導体層30と重なっている。
上記以外については、半導体装置101a及び101bには、図1に関して説明した半導体装置101と同様の説明を適用することができる。
なお、メモリセルアレイは、複数の半導体装置101cの下側に配置されてもよい。例えば、基板50と絶縁膜60との間にメモリセルアレイが配置されてもよい。また、基板50には、CMOS等の回路が形成されていてもよい。
これ以外については、半導体装置101cには、図1に関して説明した半導体装置101と同様の説明を適用することができる。例えば、複数の第3半導体層30における第1結晶方位の配向性は、複数の第1半導体層10における第1結晶方位の配向性よりも高い。また、複数の第3半導体層30のうちチャネル方向が第1結晶方位に沿った領域の割合は、複数の第3半導体層30のうちチャネル方向が第1結晶方位とは異なる方位に沿った領域の割合よりも高い。
絶縁層60は、基板50の上に設けられ、複数の半導体装置101cと基板50との間に配置されている。絶縁層60は、酸化シリコン(SiO2)、窒化シリコン(SiN)または酸化アルミニウム(Al2O3)を含む。
図4(a)〜図4(c)は、実施形態に係る半導体装置の製造方法を例示する工程順模式的断面図である。
これらの図は、図4(c)に続く、半導体装置102の製造工程を例示している。図5(a)に表したように、反応性イオンエッチング(Reactive Ion Etching:RIE)プロセスにて、第1〜第4半導体層をエッチングする。これにより、複数の柱状の縦型FET構造80を形成する。
これらの図は、図5(c)に続く、半導体装置102の製造工程を例示している。図6(a)に表したように、絶縁膜43を第1〜第3半導体層及び絶縁層51の上に、ALDプロセスまたはCVDプロセスによって形成する。
例えば、アモルファスシリコン層30f中の不純物濃度は、1×1018cm−3以上である。ここで、チャネル中の不純物濃度は、ソース・ドレイン領域と同程度(例えば1×1020cm−3以上)でもよいが、チャネル厚(チャネル長)によってはカットオフ特性が劣化する。このため、チャネル幅が10nm以下でない場合は、濃度を低めに設定することが好ましい。蓄積型のトランジスタにおいても、チャネル中の欠陥を終端するためにFやH等の不純物を導入してもよい。この後、結晶化アニールとして650℃以下の熱処理を行うことで、シード層34fとアモルファスシリコン層30fとを結晶化する。これにより、第3半導体層30及び第4半導体層34としてポリシリコン層を形成する。
結晶化により第3半導体層30を形成した後には、ドレイン領域を形成し、ポリシリコン層をピラー形状に加工する。以降の工程は、反転型トランジスタの形成と同様であるため省略する。
図9は、第2の実施形態に係る半導体装置を例示する模式的断面図である。
図9に示した半導体装置103においても、第1半導体層10、第2半導体層20、第3半導体層30、第4半導体層34、第1電極40、絶縁膜43、が設けられる。これらについては、図1の半導体装置101における説明と、同様の説明を適用することができる。半導体装置103は、さらに、基板70、絶縁層71、絶縁層72、絶縁層73、絶縁層75及び第5半導体層35を含む。
図10(a)〜図10(d)は、第2の実施形態に係る半導体装置の製造方法を例示する工程順模式的断面図である。
図10(a)に表したように、基板70の上に絶縁層71を形成する。絶縁層71の形成においては、まず基板70上に絶縁膜を形成し、リソグラフィ及びRIEプロセスによって、この絶縁膜をパターニングする。これにより、絶縁層71には凹部71eが形成される。多結晶半導体層(第1〜第3半導体層)を含むTFT構造は、この凹部71eに埋め込まれる。
図10(d)に表したように、例えば、少なくとも第3半導体層30の上に、絶縁膜43及び第1電極40を積層して、ゲートスタック構造を形成する。ゲートスタック構造の形成には、リソグラフィ及びRIEプロセスを用いることができる。
横型のTFTである半導体装置103においても、縦型のTFTである半導体装置101と同様に、チャネル中のみ結晶粒の配向性が高い。このため、閾値のシフトやキャリアの移動度低下などのトランジスタ特性の劣化を抑制することができる。
横型のTFTにおいては、側壁の形成後にソース・ドレイン領域の不純物注入が行われる。このため、チャネル方向に対して垂直な方向において、第1電極40は、不純物濃度の高いソース・ドレイン領域と重ならない。これにより、GIDLを抑制することができ、リーク電流を低減することができる。さらに、第1の実施形態と同様に、第1電極の端部の直下には、配向性の低い第1半導体層10及び第2半導体層20が位置する。このため、ソース・ドレイン領域からチャネルへの不純物の拡散が抑制される。したがって、この点からもGIDLが抑制され、リーク電流を低減することができる。
また、各具体例のいずれか2つ以上の要素を技術的に可能な範囲で組み合わせたものも、本発明の要旨を包含する限り本発明の範囲に含まれる。
Claims (16)
- 第1半導体層と、
第2半導体層と、
前記第1半導体層と前記第2半導体層との間に設けられた第3半導体層と、
前記第1半導体層と前記第3半導体層との間に設けられたシード層と、
前記第3半導体層と対向する第1電極と、
を備え、
前記第1半導体層は、
第1導電型の不純物を含む第1層と、
前記第1層と前記シード層との間に設けられた第2層と、
を含み、
前記第1層における前記不純物の濃度は、前記第2層における前記不純物の濃度よりも高く、
前記第3半導体層における配向性は、前記第1層における配向性よりも高く、前記第2層における配向性よりも高い、半導体装置。 - 前記第3半導体層中の粒界の密度は、前記第1半導体層中の粒界の密度よりも低い請求項1記載の半導体装置。
- 前記第3半導体層中の結晶粒の大きさの平均は、前記第1半導体層中の結晶粒の大きさの平均よりも大きい請求項1または2に記載の半導体装置。
- 前記第3半導体層のうち第1結晶方位に配向した領域の密度は、前記第1半導体層のうち前記第1結晶方位に配向した領域の密度よりも高い請求項1〜3のいずれか1つに記載の半導体装置。
- 前記第3半導体層における前記配向性は、前記第2半導体層における配向性よりも高い請求項1〜4のいずれか1つに記載の半導体装置。
- 前記第1電極は、第1端部と、前記第1半導体層から前記第2半導体層へ向かう第1方向において前記第1端部と離間した第2端部と、を含み、
前記第1端部は、前記第1方向と交差する方向において、前記第3半導体層および前記第2層のいずれかと重なる請求項1〜5のいずれか1つに記載の半導体装置。 - 前記第1端部は、前記交差する方向において前記第2層と重なる請求項6記載の半導体装置。
- 前記第2半導体層は、
前記第1導電型の前記不純物を含む第3層と、
前記第3層と前記第3半導体層との間に設けられた第4層と、
を含み、
前記第3層における前記不純物の濃度は、前記第4層における前記不純物の濃度よりも高く、
前記第3半導体層における前記配向性は、前記第4層における配向性よりも高い請求項1〜5のいずれか1つに記載の半導体装置。 - 前記第1電極は、第1端部と、前記第1半導体層から前記第2半導体層へ向かう第1方向において前記第1端部と離間した第2端部と、を含み、
前記第1端部は、前記第1方向と交差する方向において、前記第3半導体層および前記第2層のいずれかと重なり、
前記第2端部は、前記交差する方向において、前記第3半導体層および前記第4層のいずれかと重なる請求項8記載の半導体装置。 - 前記第3半導体層のうち前記第1半導体層から前記第2半導体層へ向かう第1方向が第1結晶方位に沿った領域の割合は、前記第3半導体層のうち前記第1方向が前記第1結晶方位とは異なる第2結晶方位に沿った領域の割合よりも高い請求項1〜3のいずれか1つに記載の半導体装置。
- 前記第1結晶方位は、<100>方向、<110>方向および<111>方向のいずれかである請求項10記載の半導体装置。
- 前記第3半導体層は、第1材料の結晶を含み、
前記第1材料は、Si、Ge、SixGe1−x(0<x<1)、InxGa1−xAs(0≦x≦1)およびInxGa1−xSb(0≦x≦1)のいずれかである請求項1〜11のいずれか1つに記載の半導体装置。 - 前記第3半導体層は、前記第1材料の多結晶を含む請求項12記載の半導体装置。
- 前記第3半導体層中の前記第1半導体層から前記第2半導体層へ向かう第1方向に沿って延在する粒界は、前記第3半導体層中の前記第1方向と交差する方向に沿って延在する粒界よりも多い請求項13記載の半導体装置。
- 前記第1半導体層および前記第2半導体層は、前記第1材料の多結晶を含む請求項12〜14のいずれか1つに記載の半導体装置。
- 第1面を有する基板をさらに備え、
前記第1半導体層は、前記第1面の上に設けられ、
前記第1半導体層から前記第2半導体層へ向かう方向は、前記第1面に対して垂直である請求項1〜15のいずれか1つに記載の半導体装置。
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KR100492727B1 (ko) * | 2001-11-15 | 2005-06-07 | 엘지.필립스 엘시디 주식회사 | 포토레지스트의 잔사불량이 방지된 반도체 도핑방법 및이를 이용한 액정표시소자 제조방법 |
KR100483985B1 (ko) * | 2001-11-27 | 2005-04-15 | 삼성에스디아이 주식회사 | 박막 트랜지스터용 다결정 실리콘 박막 및 이를 사용한디바이스 |
US6847050B2 (en) * | 2002-03-15 | 2005-01-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor element and semiconductor device comprising the same |
JP2009212331A (ja) | 2008-03-05 | 2009-09-17 | Seiko Epson Corp | 半導体装置の製造方法、電気光学装置の製造方法 |
WO2012090799A1 (en) * | 2010-12-28 | 2012-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP2014093319A (ja) | 2012-10-31 | 2014-05-19 | Toshiba Corp | 半導体装置およびその製造方法 |
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- 2015-07-31 JP JP2015152626A patent/JP6434872B2/ja not_active Expired - Fee Related
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