JP6429549B2 - 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 - Google Patents

半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 Download PDF

Info

Publication number
JP6429549B2
JP6429549B2 JP2014190384A JP2014190384A JP6429549B2 JP 6429549 B2 JP6429549 B2 JP 6429549B2 JP 2014190384 A JP2014190384 A JP 2014190384A JP 2014190384 A JP2014190384 A JP 2014190384A JP 6429549 B2 JP6429549 B2 JP 6429549B2
Authority
JP
Japan
Prior art keywords
clock
frequency
circuit
clock signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2014190384A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016062352A5 (enExample
JP2016062352A (ja
Inventor
央章 新妻
央章 新妻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2014190384A priority Critical patent/JP6429549B2/ja
Priority to US14/856,253 priority patent/US9432011B2/en
Publication of JP2016062352A publication Critical patent/JP2016062352A/ja
Publication of JP2016062352A5 publication Critical patent/JP2016062352A5/ja
Application granted granted Critical
Publication of JP6429549B2 publication Critical patent/JP6429549B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Memory System (AREA)
JP2014190384A 2014-09-18 2014-09-18 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。 Expired - Fee Related JP6429549B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014190384A JP6429549B2 (ja) 2014-09-18 2014-09-18 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。
US14/856,253 US9432011B2 (en) 2014-09-18 2015-09-16 Semiconductor integrated circuit, apparatus with semiconductor integrated circuit, and clock control method in semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014190384A JP6429549B2 (ja) 2014-09-18 2014-09-18 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。

Publications (3)

Publication Number Publication Date
JP2016062352A JP2016062352A (ja) 2016-04-25
JP2016062352A5 JP2016062352A5 (enExample) 2017-11-02
JP6429549B2 true JP6429549B2 (ja) 2018-11-28

Family

ID=55526720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014190384A Expired - Fee Related JP6429549B2 (ja) 2014-09-18 2014-09-18 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。

Country Status (2)

Country Link
US (1) US9432011B2 (enExample)
JP (1) JP6429549B2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6410538B2 (ja) * 2014-09-18 2018-10-24 キヤノン株式会社 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。
JP6681244B2 (ja) * 2016-03-30 2020-04-15 キヤノン株式会社 画像処理装置、その制御方法、及びプログラム
JP6808414B2 (ja) * 2016-09-21 2021-01-06 キヤノン株式会社 情報処理装置、その制御方法、及びプログラム
KR102406669B1 (ko) * 2017-11-08 2022-06-08 삼성전자주식회사 메모리 컨트롤러 및 이를 포함하는 스토리지 장치
US10747470B2 (en) * 2018-05-10 2020-08-18 Micron Technology, Inc. Semiconductor device with pseudo flow through scheme for power savings
JP7243172B2 (ja) * 2018-12-18 2023-03-22 富士フイルムビジネスイノベーション株式会社 画像処理装置
US12135668B2 (en) * 2022-11-16 2024-11-05 Stmicroelectronics S.R.L. Asynchronous controller for processing unit

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3468592B2 (ja) * 1994-08-10 2003-11-17 富士通株式会社 クロック信号発生回路
JPH11306074A (ja) * 1998-04-23 1999-11-05 Sharp Corp 情報処理装置
JP3800164B2 (ja) * 2002-10-18 2006-07-26 ソニー株式会社 情報処理装置、情報記憶装置、情報処理方法、及び情報処理プログラム
US20100005214A1 (en) * 2008-07-01 2010-01-07 International Business Machines Corporation Enhancing bus efficiency in a memory system
JP5431290B2 (ja) 2010-10-29 2014-03-05 インターナショナル・ビジネス・マシーンズ・コーポレーション クロック・ドメイン・クロッシングのデータ転送回路および方法
WO2012166829A2 (en) * 2011-05-31 2012-12-06 Lightlab Imaging, Inc. Multimodal imaging system, apparatus, and methods

Also Published As

Publication number Publication date
US9432011B2 (en) 2016-08-30
JP2016062352A (ja) 2016-04-25
US20160087618A1 (en) 2016-03-24

Similar Documents

Publication Publication Date Title
JP6429549B2 (ja) 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。
US10296065B2 (en) Clock management using full handshaking
US11789515B2 (en) Semiconductor device
US8589611B2 (en) Asynchronous logic circuit, semiconductor circuit, and path calculation method in asynchronous logic circuit
JP5438371B2 (ja) 画像処理装置および画像処理方法
KR20170088768A (ko) 반도체 장치
JP2008178017A (ja) クロック同期システム及び半導体集積回路
CN107068177B (zh) 控制存储器的控制设备及其控制方法
US20010027503A1 (en) Clock generator suitably interfacing with clocks having another frequency
JP2009075973A (ja) 電子機器及び当該電子機器の電力制御方法
US8510576B2 (en) Semiconductor integrated circuit and control method of semiconductor integrated circuit
JP2005100269A (ja) 半導体集積回路
JP6410538B2 (ja) 半導体集積回路、半導体集積回路を備えた装置、半導体集積回路におけるクロックの制御方法、並びにプログラム。
JP2014107585A (ja) 画像形成装置
JP2016115979A (ja) 画像処理装置、その制御方法及びプログラム
JP2003157228A (ja) データ転送回路
JP2007048264A (ja) 複数チップ間の同期合わせ機能を有したデータ処理装置
CN223193306U (zh) 时钟域跨越同步电路和电子系统
JP4965161B2 (ja) メモリーカードコントローラ
JP7087509B2 (ja) 情報処理装置及び回路装置
JP2015111377A (ja) クロック生成回路
JP4730051B2 (ja) 半導体ディジタル回路、ｆｉｆｏバッファ回路及びそれらに用いるデータ受け渡し方法
JP2017004070A (ja) 画像形成装置に搭載されるｃｐｕの省電力制御
JP2004013799A (ja) クロック切り替えシステム
JP2020127161A (ja) 情報処理装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170914

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170914

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20180524

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20180612

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180802

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20181002

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20181030

R151 Written notification of patent or utility model registration

Ref document number: 6429549

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

LAPS Cancellation because of no payment of annual fees