JP6378115B2 - 半導体装置、及び、半導体装置の製造方法 - Google Patents
半導体装置、及び、半導体装置の製造方法 Download PDFInfo
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Description
第2絶縁膜IN2は、半導体層S2上において、第3配線L3の周囲を取り囲むように設けられている。特に、第2絶縁膜IN2は、半導体層S2上において、第3配線L3の側面から規定距離までの一定の幅で、第3配線L3の周囲を取り囲むように設けられていてもよい。
これにより、半導体装置100は、所定の配線の特性を得ることが可能になる。
次に、既述の第2導電材料(例えば、Cu又はAl)を第2絶縁膜IN2の開口部110に埋め込むように、半導体層S2上に堆積させて、導電膜102を形成する(図5)。
以上のように、本第1の実施形態に係る半導体装置によれば、所定の配線の特性を得ることができる。
先ず、半導体層S2上に、既述の第1導電材料からなる導電膜(図示せず)を形成する。その後、例えば、リソグラフィー技術とRIE法を用いて、該導電膜を選択的にエッチングする。これにより、半導体層S2上に、第1導電材料を含む第1配線L1(ここでは図示せず)及び第1導電材料を含む第2配線L2を形成する(図13)。
次に、既述の第2導電材料(例えば、Cu又はAl)を第2絶縁膜IN2の開口部110に埋め込むように、半導体層S2上に堆積させて、導電膜102を形成する(図16)。
S1 半導体基板
S2 半導体層
L1 第1配線
L2 第2配線
L3 第3配線
IN 絶縁膜
IN1 第1絶縁膜
IN2 第2絶縁膜
Claims (12)
- 半導体層と、
前記半導体層上に設けられ、第1導電材料を含む第1配線と、
前記半導体層上に設けられ、前記第1導電材料を含む第2配線と、
前記半導体層上に設けられ、細線効果が顕在化する前記第1配線の線幅よりも太い線幅を有し、前記第1導電材料と異なる第2導電材料を含む第3配線と、
前記半導体層上に設けられ、前記第1配線と前記第2配線との間に配置された第1絶縁膜と、
前記半導体層上に設けられ、前記第2配線と前記第3配線との間に配置された第2絶縁膜と、を備え、
前記第2配線は、前記第3配線の両側に設けられ、
前記第1導電材料は、平均自由行程が前記第2導電材料の平均自由行程よりも短い自由電子による電気伝導機構を有する材料であり、若しくは、前記第1導電材料は、量子化伝導を示す材料であり、
前記第1配線、前記第2配線、前記第3配線、前記第1絶縁膜、及び、前記第2絶縁膜は、前記半導体層上に設けられた1つの配線層に設けられ、
前記第2配線は、前記半導体層上において、前記第3配線が延びる第1方向と並行に、断続的に設けられ、
前記第3配線の領域うち、前記第1方向と直交する第2方向に前記第2配線が存在する領域の第1幅よりも、前記第3配線の領域のうち、前記第2方向において前記第2配線が存在していない前記第3配線の領域の第2幅の方が、太くなっている
ことを特徴とする半導体装置。 - 前記配線層上又は前記配線層下に設けられ、前記第1配線及び前記第3配線と電気的に接続されたコンタクト配線をさらに備える
ことを特徴とする請求項1に記載の半導体装置。 - 前記半導体層は、半導体素子を含むことを特徴とする請求項1に記載の半導体装置。
- 前記第1配線は、NAND型フラッシュメモリのメモリセル領域に配置され、
前記第2配線及び前記第3配線は、前記NAND型フラッシュメモリの周辺回路領域に配置されていることを特徴とする請求項1に記載の半導体装置。 - 半導体基板をさらに備え、
前記半導体層は、前記半導体基板上に設けられていることを特徴とする請求項1に記載の半導体装置。 - 半導体層上に、第1導電材料を含む複数の第1配線及び前記第1導電材料を含み領域を囲む形状を有する第2配線を形成することと、
前記半導体層上に、前記複数の第1配線間に第1絶縁膜を埋め込むように堆積させるとともに、前記第2配線に隣接し、前記領域に開口部を有する第2絶縁膜を形成することと、
前記第1導電材料と異なる第2導電材料を前記第2絶縁膜の開口部に埋め込むように、前記半導体層上に堆積させて、前記第2導電材料からなる第1導電膜を形成し、前記第1絶縁膜上、前記第2絶縁膜上、前記第1配線上、及び、前記第2配線上の前記第1導電膜が除去されるまで平坦化することで、前記半導体層上に、細線効果が顕在化する前記第1配線の線幅よりも太い線幅を有し、前記第2導電材料を含む第3配線を形成することと、を備え、
前記第2絶縁膜は、前記第2配線と前記第3配線との間であって、前記第3配線に隣接して前記第3配線の周囲を囲むように配置され、
前記第2配線は、前記第3配線の両側に設けられ、
前記第1導電材料は、平均自由行程が前記第2導電材料の平均自由行程よりも短い自由電子による電気伝導機構を有する材料であり、若しくは、前記第1導電材料は、量子化伝導を示す材料であり、
前記第1配線、前記第2配線、前記第3配線、前記第1絶縁膜、及び、前記第2絶縁膜は、前記半導体層上に設けられた1つの配線層に設けられている
ことを特徴とする半導体装置の製造方法。 - CVD法を用いて、前記第1配線及び第2配線が形成された前記半導体層上に絶縁膜を形成し、その後、前記絶縁膜を異方性エッチングすることで、前記第1絶縁膜及び前記第2絶縁膜を形成する
ことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記半導体層上に、前記第1導電材料からなる第2導電膜を形成し、その後、前記第2導電膜上にマスク膜を形成し、前記マスク膜上にレジスト膜を選択的に形成し、前記レジスト膜をマスクとして、前記第2導電膜及び前記マスク膜を異方性エッチングすることで、前記第1配線及び前記第2配線を形成する
ことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第1導電材料は、Rh、Mo、Al、Ru、Cd、W、Ir、Zn、Ga、Pt、Pd、Nb、In、Co、 Ni、Cr、Tc、Os、Ta、Fe、Sn、Tl、Reの何れかの第1金属、若しくは、前記第1金属を主成分とする第1合金、若しくは、前記第1金属又は第1合金のシリサイド、若しくは、グラフェンである
ことを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第2導電材料は、Cu又はAlのいずれかの第2金属、若しくは前記第2金属を主成分とする第2合金である
ことを特徴とする請求項9に記載の半導体装置の製造方法。 - 前記第2絶縁膜は、前記半導体層上において、前記第3配線に隣接して前記第3配線の周囲を囲むように設けられていることを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記第2配線は、前記半導体層上において、前記第2絶縁膜の周囲を取り囲むように設けられている
ことを特徴とする請求項11に記載の半導体装置の製造方法。
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